forked from auracaster/openocd
flash/stm32l4x: support STM32WBA6xx devices
STM32WBA6xx support, based on ST Reference Manual RM0515 Rev 4. Change-Id: I0ddeadd5008a9f81ec638c9ad230b2f6f0349b5a Signed-off-by: Guillaume Faussard <guillaume.faussard@withings.com> Reviewed-on: https://review.openocd.org/c/openocd/+/9329 Reviewed-by: Ahmed Haoues <ahmed.haoues@st.com> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Guillaume Faussard
committed by
Antonio Borneo
Antonio Borneo
parent
b074fea079
commit
df14f58662
@@ -287,7 +287,7 @@ struct stm32l4_wrp {
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};
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/* human readable list of families this drivers supports (sorted alphabetically) */
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static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U0/U3/U5/WB/WL";
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static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U0/U3/U5/WB/WBA/WL";
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static const struct stm32l4_rev stm32l47_l48xx_revs[] = {
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{ 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
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@@ -400,6 +400,10 @@ static const struct stm32l4_rev stm32wba5x_revs[] = {
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{ 0x1000, "A" },
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};
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static const struct stm32l4_rev stm32wba6x_revs[] = {
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{ 0x1000, "A" }, { 0x1001, "Z" },
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};
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static const struct stm32l4_rev stm32wb1xx_revs[] = {
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{ 0x1000, "A" }, { 0x2000, "B" },
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};
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@@ -758,6 +762,19 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
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.otp_base = 0x0BF90000,
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.otp_size = 512,
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},
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{
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.id = DEVID_STM32WBA6X,
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.revs = stm32wba6x_revs,
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.num_revs = ARRAY_SIZE(stm32wba6x_revs),
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.device_str = "STM32WBA6x",
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.max_flash_size_kb = 2048,
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.flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ
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| F_HAS_L5_FLASH_REGS | F_WRP_HAS_LOCK,
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.flash_regs_base = 0x40022000,
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.fsize_addr = 0x0BFA07A0,
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.otp_base = 0x0BFA0000,
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.otp_size = 512,
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},
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{
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.id = DEVID_STM32WB1XX,
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.revs = stm32wb1xx_revs,
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@@ -2210,10 +2227,21 @@ static int stm32l4_probe(struct flash_bank *bank)
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}
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break;
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case DEVID_STM32WBA5X:
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/* single bank flash */
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case DEVID_STM32WBA6X:
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/* according to RM0493 Rev 7, Chapter 7.3.1
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* WBA5xx have 8K page size and are always
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* single bank.
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* According to RM0515 Rev 4, Chapter 7.3.1
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* WBA6xx have 8K page size and are always
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* DUAL BANK
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*/
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page_size_kb = 8;
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num_pages = flash_size_kb / page_size_kb;
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stm32l4_info->bank1_sectors = num_pages;
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if (stm32l4_info->optr & FLASH_U5_DUALBANK) {
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stm32l4_info->dual_bank_mode = true;
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stm32l4_info->bank1_sectors = num_pages / 2;
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}
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break;
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case DEVID_STM32WB5XX:
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case DEVID_STM32WB3XX:
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@@ -120,6 +120,7 @@
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#define DEVID_STM32WB5XX 0x495
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#define DEVID_STM32WB3XX 0x496
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#define DEVID_STM32WLE_WL5XX 0x497
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#define DEVID_STM32WBA6X 0x4B0
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/* known Flash base addresses */
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#define STM32_FLASH_BANK_BASE 0x08000000
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@@ -0,0 +1,106 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32wba6x family
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#
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# stm32wba6x devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32wba6x
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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# jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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set _CPUTAPID 0x6ba00477
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} else {
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# SWD IDCODE (single drop, arm)
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set _CPUTAPID 0x6ba02477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x0bfa0000 0 0 0 $_TARGETNAME
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# Common knowledges tells JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
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# the safe side.
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#
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# Note that there is a pretty wide band where things are
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# more or less stable, see http://openocd.zylin.com/#/c/3366/
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adapter speed 500
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event reset-init {
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# CPU comes out of reset with HSION | HSIRDY.
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# Use HSI 16 MHz clock, compliant even with VOS == 2.
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# 1 WS compliant with VOS == 2 and 16 MHz.
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mmw 0x40022000 0x00000001 0x0000000E ;# FLASH_ACR: Latency = 1
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mmw 0x56020C00 0x00000100 0x00000000 ;# RCC_CR |= HSION
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mmw 0x56020C1C 0x00000000 0x00000002 ;# RCC_CFGR1: SW=HSI16
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# Boost JTAG frequency
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adapter speed 4000
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}
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$_TARGETNAME configure -event reset-start {
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# Reset clock is HSI (16 MHz)
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adapter speed 2000
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}
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$_TARGETNAME configure -event examine-end {
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# Enable debug during low power modes (uses more power)
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# DBGMCU_SCR |= DBG_STANDBY | DBG_STOP
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mmw 0xE0044004 0x00000006 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0044008 0x00001800 0
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}
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tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
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lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
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proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
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targets $_targetname
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}
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$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
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