Commit Graph

8791 Commits

Author SHA1 Message Date
Tomas Vanek
3e7a7092d4 target/arm_dpm: report vector catch as breakpoint
Commit 4afa32ece1 ("aarch64: unify armv7-a and armv8
debug entry decoding")
probably unintentionally removed DSCR_ENTRY_VECT_CATCH from
reported debug entry reasons. Note the discrepancy between
'case DSCR_ENTRY_BKPT_INSTR:' and its comment.

Hitting vector catch was reported as DBG_REASON_UNDEFINED.
DBG_REASON_UNDEFINED disturbed hwthread/gdb cooperation and
gdb reported the wrong thread as stopped by SIGTRAP.

Revert to the original functionality and report vector
catch as a breakpoint.

Change-Id: I12e938182cff8f633decba340000cfbb7b112ae3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9209
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-11-19 17:57:02 +00:00
Tomas Vanek
5d8a142703 target/armv4_5: mark registers as 'save-restore'
gdb uses this mark when creating a dummy frame for
manual call of a function by gdb command.
With the original setting all registers as caller_save = false
call command in gdb always clobbers r0, r1 and pc
and some other registers depending on the called function.

Set 'save-restore' for all registers but banked ones.

Change-Id: I16c49e4bf8001e38d18ce8861ca65988b08ccc88
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9208
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-11-19 17:56:45 +00:00
Tomas Vanek
d044affba5 target/armv4_5: fix register numbering overlap
Commit b5d2b1224f ("target/cortex_a: add hypervisor mode")
added sp_hyp, spsr_hyp registers with gdb_index 51 and 52
but did not moved FP regs enum base starting from 51.

Move FP registers indices to make room for added registers.

Change-Id: I4338777545918fdf62016e06764308dacea61e98
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9235
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-11-19 17:56:29 +00:00
Tomas Vanek
83052c86e9 target/cortex_a: report target in some LOG_xx calls
Switch to LOG_TARGET_DEBUG() and LOG_TARGET_ERROR()
to make analyzing logs of multicore system easier.

Not changed completely in the whole file, the changes were focused
to halt and resume.

Change-Id: I055ad682d3098d5c301a111605d57e504f877b4c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9207
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-11-19 17:56:13 +00:00
Vincent Fazio
0021ee2f5d jtag/drivers/bcm2835gpio: Support all 54 GPIO pins
Previously, only the first 32 GPIO were supported on the BCM2835.

Performance was cited as being the primary justification for not
supporting all 54 pins, notably:

  1. There is overhead for calculating the memory offset for the pin
  2. GPIO values cannot be written in bulk if pins span memory offsets

Now, all 54 GPIO pins are supported by the driver.

Since pins may use different offsets, multiple pins cannot be toggled
with one memory store. Multiple stores now need to occur when one
sufficed before.

To offset some of the performance overhead for the additional stores,
memory addresses, masks, and shift bits are calculated once and cached
into struct. Calculating these once reduces the number of instructions
a function needs to run in order to manipulate a given GPIO.

The following functions have been updated to leverage the new struct
as they represent some of the hottest paths:

  bcm2835_swdio_drive
  bcm2835_swdio_read
  bcm2835gpio_swd_write_fast
  bcm2835gpio_read
  bcm2835gpio_write

For `bcm2835gpio_swd_write_fast`, performance should be roughly the same
as the number of memory stores hasn't changed.

For `bcm2835_write`, there is a slight performance degradation since
TMS/TDI/TCK are set separately which incurs an additional memory store.

Instruction counts across the above functions are reduced by ~10-40%.

Macros to access registers have been reworked into inline functions to
support access to all pins and to avoid checkpatch headaches.

The `initial_gpio_state.output_level` member has been retyped to bool to
better align with the expected values.

Support for adjusting pads for the expanded pin range has been left out
as support for manipulating these settings should be moved out of this
driver and into its own utility.

Change-Id: I18853d1a2c86776658630326c71a6bf236fcc6da
Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7732
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-11-18 06:28:05 +00:00
Evgeniy Naydanov
4e78563a00 target/riscv: fix progbuf memory writes in case last write is busy
Restarting the program buffer memory write pipeline when the write of
the last element resulted in the busy response triggers an extra memory
wrtite, that is cought by an assertion:
```
src/target/riscv/riscv-013.c:5048: write_memory_progbuf_inner: Assertion
`next_addr_on_target - args.address <= (target_addr_t)args.size *
args.count' failed.
```

Change-Id: I0f27145cad24686cf539aebfea7f6578b7cd78ab
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9233
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:53:02 +00:00
Parshintsev Anatoly
12ab80ab45 target/riscv: fix SV57 translation for kernel address space
Fixes address translation for SV57 addresses.

See [1] for details.

Link: https://github.com/riscv-collab/riscv-openocd/pull/1285 [1]
Change-Id: I53f7062f16c0b9e8595f38c07810b2dbc300980b
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9187
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:52:25 +00:00
Tim Newsome
68b0f7bdff server: rtos: don't fake step for hwthread rtos.
This is a cherry-pick of:
Link: efce094b40

Fake step is a hack introduced to make things work with real RTOSs that
have a concept of a current thread. The hwthread rtos always has access
to all threads, so doesn't need it.

This fixes a bug when running my MulticoreRegTest against HiFive
Unleashed where OpenOCD would return the registers of the wrong thread
after gdb stepped a hart.

Change-Id: I64f538a133fb078c05a0c6b8121388b0b9d7f1b8
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9177
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-11-12 20:37:01 +00:00
Antonio Borneo
52ac91a73e target: riscv: move the SMP commands under riscv
For all the targets that support SMP, the sub-commands 'smp' and
'smp_gdb' are under the arch name:
- aarch64 smp
- cortex_a smp
- cortex_m smp
- esp32 smp
- mips_m4k smp

Keep consistency among OpenOCD commands, and move under the arch
name 'riscv' the SMP subcommands.

Change-Id: Iede7841c2df8161ff2c6fea3be561d1f26ad6cd0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9165
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-11-12 20:35:14 +00:00
Antonio Borneo
8c41070415 target: riscv: fix double free() in parse_reg_ranges()
The buffer 'args' is allocated and freed in the caller function
parse_reg_ranges().
There is no reason to free it, only in some special case, in the
called function parse_reg_ranges_impl().
Scan build reports:
	src/target/riscv/riscv.c:4537:2: warning: Attempt to free
	released memory [unix.Malloc]

Drop the free() in the called function.

Change-Id: I2e308670c502f8e140603b4e5c16fc568088e1a8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9164
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:34:40 +00:00
Antonio Borneo
be083909b7 target: riscv: fix memory leak in riscv_openocd_step_impl()
The array 'wps_to_enable' is never freed.
Scan build reports:
	src/target/riscv/riscv.c:4271:6: warning: Potential leak
	of memory pointed to by 'wps_to_enable' [unix.Malloc]

Add the needed free().
While there, check if the allocation is successful.

Change-Id: I00e7ade37a43a97dcc245113ad93c48784fce609
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9163
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-11-12 20:34:21 +00:00
Tomas Vanek
18734bcf95 target/riscv: fix get mode filed for vsatp and hgatp
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1258
developed by Mark Zhuang <mark.zhuang@spacemit.com>

Add the necessary get_filed and add a comment to indicate
this section is for VU/VS mode

Change-Id: I898bba6250258c5076a98eb95411fcabccc52b96
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9144
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
2025-11-12 20:33:15 +00:00
Tomas Vanek
ffdbdf6b03 target/riscv: fix address translation in hypervisor mode
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1258
developed by zhefan.lv <zhefan.lv@spacemit.com>

address translation don't need to care hstatus.HU

Change-Id: I40a15ec17347dffaa6e663a637150dfb393471a0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9143
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2025-11-12 20:32:57 +00:00
Sriram Shanmuga
f5ce311103 target/riscv: improve error messaging in case sbasize is zero
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1274

From: Sriram Shanmuga <sriramharshalee@gmail.com>

RISC-V Debug Specification v1.0 [3.14.22. System Bus Access Control and
Status (`sbcs`, at 0x38)] states in `sbasize` field description:
> Width of system bus addresses in bits. (0 indicates there is no bus
access support.)

Before the patch, the error message did not include the information
about `sbcs.sbasize` being zero wich made it quite undescriptive:
```
[riscv.cpu] Turning off memory sampling because it failed.

```

Fixes #1270

Change-Id: I5402dd57dc9a81f65ee4c67d24e11c366006427c
Signed-off-by: Sriram Shanmuga <sriramharshalee@gmail.com>
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9142
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:32:33 +00:00
Tomas Vanek
3483756cba target/riscv: check nextdm address in abits range
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1257
developed by Mark Zhuang <mark.zhuang@spacemit.com>

When abits not correctly configured, we hope to detect it
as soon as possible.

Change-Id: I0b7b170c39761fb531dda0747f88ace3f39ae03b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9141
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
2025-11-12 20:32:10 +00:00
Tim Newsome
4447fa4c98 gdb_server,rtos: Differentiate rtos_get_gdb_reg failing and not implemented
If it fails, then pass that failure on. If it's simply not implemented,
then we can fall through and try target_get_gdb_reg_list_noread().

This difference matters when the target representing the current
hwthread is unavailable, but the target that is linked to the gdb
connection is available. In that case we want the operation to return an
error to gdb, instead of reading the register from the target that is
available.

Change-Id: I9c84ca556f818c5580e25ab349a34a226fcf0f43
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9138
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:31:37 +00:00
Tomas Vanek
31b2660152 rtos: introduce rtos_put_gdb_reg()
and use it in rtos_get_gdb_reg() after get_thread_reg_value()
to allow passing long register value without hackish use of
struct rtos_reg.

Fixes: 9123: rtos: Dynamically allocate memory for RTOS registers
Link: https://review.openocd.org/c/openocd/+/9123
Change-Id: I30a51dcca60d67a0f01aa957c9c6076f266b5758
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9135
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2025-11-12 20:31:06 +00:00
Tomas Vanek
ab8fb1d981 target/riscv: fix checking of number of parameters
in command 'riscv resume_order' to prevent segfault
on issuing the command without a parameter.

Change-Id: I5d7f4f92c2fa8e9effaba2c000d111e491b7b64f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9132
Tested-by: jenkins
2025-11-12 20:30:12 +00:00
Tomas Vanek
a0eac82708 target, flash: utility for riscv repeat_read command
Imported non-riscv part from
https://github.com/riscv-collab/riscv-openocd/pull/510
developed by Tim Newsome <tim@sifive.com>

Introduce target_handle_md_output() parameter include_address.
All callers set it true but riscv repeat_read command.

Change-Id: I67b5aad15a33ad149d4047998b22407cb60098fd
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9127
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2025-11-12 20:29:03 +00:00
Tomas Vanek
f354d259ff target/riscv: return ERROR_TARGET_NOT_HALTED
instead of ERROR_FAIL where appropriate.

Change-Id: I1881c0c6c437355007c3844556489162666023dc
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9171
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2025-11-12 20:27:27 +00:00
Tim Newsome
6d764f5b09 rtos: Dynamically allocate memory for RTOS registers
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/647

FreeRTOS part of patch dropped as it depends on other
riscv-collab specific changes.

This makes things work on RISC-V cores with large vector registers
(which can be up to kilobytes in size).

Change-Id: Ie53cb43a88e2a475f695cd5c1e28605569926817
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9123
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2025-11-12 20:25:37 +00:00
Tim Newsome
6127077613 target/breakpoints: better wording for error reason
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/767

Extracted small part of
target/riscv: Don't resume unavailable harts.

Change-Id: Id6617230cfdadf93ba402e60fb704bdfe7af5c1e
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8921
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:19:28 +00:00
Antonio Borneo
da96d3d41b target: riscv-011: don't change 'debug_level' during target polling
In the riscv fork, [1] has disable the debug log during target
polling, with message:
	Improve low-level logging.

	Now logging is consistent and more readable.
	I did remove most logging during riscv_poll() since it clutters
	up the log/screen and is not generally helpful.

This is questionable, because if the user enables the debug log,
the messages should all be logged.

Drop the code that overwrites the 'debug_level'.

Link: https://github.com/riscv-collab/riscv-openocd/commit/54c65a9a4b71 [1]
Change-Id: Ia86b998cf654760f36c2f217d44bcb9ffd9c3a94
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9072
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:18:36 +00:00
Antonio Borneo
768b4084eb target: riscv: don't test 'debug_level' directly
Use the macro 'LOG_LEVEL_IS()' to test 'debug_level'.

Change-Id: Ic931fd2eff0fa97a7a315b4b276f85dfc5fc8d5f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9071
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-11-12 20:17:21 +00:00
Antonio Borneo
bd303d6a3d target: riscv: align switch and case statements
The coding style requires the 'case' to be at the same indentation
level of its 'switch' statement.

Align the code accordingly.

While there, put at newline the command after the 'case'.

No changes are reported by
	git log -p -w --ignore-blank-lines --patience
apart from the newline after 'case'.

Change-Id: Id856e24100de6fb0442afe8bc51545b0138ef02d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9069
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:16:51 +00:00
Bernhard Rosenkränzer
56141bb349 target: riscv: Drop new typedefs added by the updated riscv-debug-spec files
The advantage of this patch is that it brings the new code closer to
OpenOCD coding style - the disadvantage is that it involves modifying
autogenerated files, making it harder to drop in new versions when
riscv-debug-spec changes.

Change-Id: I4c317e11ab1652333b0bb44168f953ef452d3ef5
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8896
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-11-12 20:16:13 +00:00
Bernhard Rosenkränzer
5754aebc49 target: riscv: Sync with the RISC-V fork
Regenerate autogenerated debug_defines.{c,h} files from current
riscv-debug-spec, sync remaining RISC-V target files with the
RISC-V fork.

This is based on the work of (in alphabetic order):

Aleksey Lotosh <lotosh@gmail.com>
Alexander Rumyantsev <cetygamer@gmail.com>
Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Bernhard Rosenkränzer <bero@baylibre.com>
bluew <bluewww@users.noreply.github.com>
Carsten Gosvig <40368726+cgsfv@users.noreply.github.com>
cgsfv <cgsfv@users.noreply.github.com>
Craig Blackmore <craig.blackmore@embecosm.com>
Dan Robertson <danlrobertson89@gmail.com>
Darius Rad <darius@bluespec.com>
dave-estes-syzexion <53795406+dave-estes-syzexion@users.noreply.github.com>
Dmitry Ryzhov <dmitry.ryzhov@cloudbear.ru>
Dolu1990 <charles.papon.90@gmail.com>
Emmanuel Blot <emmanuel.blot@free.fr>
Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>
Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Farid Khaydari <f.khaydari@syntacore.com>
Gleb Gagarin <gleb@sifive.com>
Greg Savin <43152568+SiFiveGregS@users.noreply.github.com>
Hang Xu <xuhang@eswincomputing.com>
Hsiangkai <Hsiangkai@gmail.com>
Jan Matyas <jan.matyas@codasip.com>
jhjung81 <48940114+jhjung81@users.noreply.github.com>
Jiuyang Liu <liu@jiuyang.me>
Kaspar Schleiser <kaspar@schleiser.de>
Khem Raj <raj.khem@gmail.com>
Kirill Radkin <kirill.radkin@syntacore.com>
liangzhen <zhen.liang@spacemit.com>
Liviu Ionescu <ilg@livius.net>
Marc Schink <openocd-dev@marcschink.de>
Megan Wachs <megan@sifive.com>
Nils Wistoff <git@wistoff.net>
Palmer Dabbelt <palmer@dabbelt.com>
panciyan <panciyan@eswincomputing.com>
Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Paul George <command.paul@gmail.com>
Pavel S. Smirnov <Paul.Smirnov.aka.sps@gmail.com>
Philipp Wagner <mail@philipp-wagner.com>
Ryan Macdonald <rmac@sifive.com>
Samuel Obuch <samuel.obuch17@gmail.com>
Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tim Newsome <tim@casualhacker.net>
Tobias Kaiser <mail@tb-kaiser.de>
Tom Hebb <tommyhebb@gmail.com>
Tommy Murphy <tommy_murphy@hotmail.com>
wxjstz <wxjstz@126.com>
wzgpeter <wzgpeter@outlook.com>
Xiang W <wxjstz@126.com>
zhusonghe <zhusonghe@eswincomputing.com>

Checkpatch-ignore MULTISTATEMENT_MACRO_USE_DO_WHILE is added to allow a
macro in riscv-013.c that can't use do/while because it expands to a
"case ...:" statement.

Checkpatch-ignore TRAILING_SEMICOLON is added to allow a construct in
riscv-013.c where a macro expands to either code (where it needs the
semicolon) or a member of an enum (where it needs a comma).

Checkpatch-ignore LONG_LINE_COMMENT and NEW_TYPEDEFS lines are added for
the sake of the autogenerated files from riscv-debug-spec.
All non-autogenerated files have been updated for checkpatch compliance.

Checkpatch-ignore: LONG_LINE_COMMENT
Checkpatch-ignore: NEW_TYPEDEFS
Checkpatch-ignore: MULTISTATEMENT_MACRO_USE_DO_WHILE
Checkpatch-ignore: TRAILING_SEMICOLON
Change-Id: Ie594915a4d6e6f9d9dad6016b176ab76409a099a
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8893
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:14:47 +00:00
Antonio Borneo
ab22b0bf8f target: cortex-m: don't query cache on hla targets
The cache handling code is written and optimized for dap queuing.
On hla targets it causes a segmentation fault due to uninitialized
AP pointer still set to NULL.

While it's possible to modify the code to cope with hla targets,
this would lower the OpenOCD performance on modern adapters.

Make cache handling not available on hla targets.

Reported-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Ief4499caedcee477b9517a7ad4597d06b5cb061e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 04da6e2c62 ("target: cortex-m: add support for armv8m caches")
Reviewed-on: https://review.openocd.org/c/openocd/+/9202
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-11-08 16:00:22 +00:00
Daniel Anselmi
52ea420dd2 ipdbg: simplify command chains
simplify ipdbg commands:
$hub_name ipdbg start -> $hub_name start

ipdbg/fix: While there, handle the multi-word deprecated commands
by adding quotes.

Change-Id: I5a56df2dbf2a5710442242727fa9384e5541ed53
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Fixes: https://sourceforge.net/p/openocd/tickets/434/
Reported-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8873
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-11-08 15:57:05 +00:00
HAOUES Ahmed
03b79387cc flash/stm32h7x: support STM32H7R/H7Sx
The STM32H7R/H7Sx has a flash size up to 64 Kb
Change-Id: I2e9d80758d1bc88defdd6bbd1787026373b39fa4
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8890
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-11-06 08:10:15 +00:00
HAOUES Ahmed
b8dc15f43b flash/stm32h7x: use BIT macro whenever possible
Use the BIT() macro in place of bare shifts
Change-Id: Iad66e12354fc3c76c718a793eb6689258d497b00
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9012
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-06 08:09:36 +00:00
HAOUES Ahmed
fe3c626b3f flash/stm32h7x: Rename functions and variable names
Prepare support for STM32H7R/S
Rename methods to follow the STM32l4 driver naming

Change-Id: Iad14ba89a48a63c158dae05a53dcbf92f6fe2f53
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8889
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-06 08:09:06 +00:00
HAOUES Ahmed
e4e0faeba6 flash/stm32h7x: Refactor STM32H7 flash register definitions to use enum
Replace individual #define constants for STM32H7 flash registers with an
enum to improve code readability and maintainability.

While there, replace a magic number with the macro
MASS_ERASE_TIMEOUT.

while there, remove the unneeded inline attribute

Change-Id: Ib35cbdace5c2f4d12aa91c370d6ec0ce348b397f
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8888
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-06 08:08:29 +00:00
Lucien Dufour
22afaae7fa Use C99 style for loop var
Use ARRAY_SIZE() to ensure ranges are correct.
Also, the C99 style is hopefully more readable.

Change-Id: I3d6bfbdc8e723791ba14d5a32e311c61bc2dfd77
Signed-off-by: Lucien Dufour <lucien.buchmann@dufour.aero>
Reviewed-on: https://review.openocd.org/c/openocd/+/9097
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
2025-11-02 13:50:21 +00:00
kryvosheiaivan
1ee0499cd8 armv8m: Add support for msplim/psplim for targets with no secext
When armv8m does not have security extension, it still has
msplim/psplim regs implemented, which is described in Cortex-M33
Devices Generic User Guide.
Document ID: 100235_0100_06_en, or at the link:
https://developer.arm.com/documentation/100235/latest/
Tested on cyw20829 along with gdb v14.2.1

Change-Id: I4f060e4df742c6773e79ce0481697361202d544c
Signed-off-by: kryvosheiaivan <Ivan.Kryvosheia@infineon.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8887
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-11-02 13:46:35 +00:00
Jonathan Steinert
914b855780 xmc4xxx: Correct some flash sector layouts
I think this may have been a typo/thinko from first implementation, but
for the 4200 the layout is 8 16KB chunks and then 1 128KB chunk. We were
previously only writing 240KB

Signed-off-by: Jonathan Steinert <hachi@kuiki.net>
Change-Id: Ic3cff75ba21f6bc6ac440dfb30e24c328c7cd47c
Reviewed-on: https://review.openocd.org/c/openocd/+/9172
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.au>
Tested-by: jenkins
2025-11-02 13:39:56 +00:00
Marc Schink
165e578d2b adapter/cmsis-dap: Add driver for TCP backend
The cmsis-dap driver is not added to the list of drivers if none of the
USB backends is available.

Add cmsis-dap driver also if TCP backend is available.

Change-Id: I877fac528e7102af74ee54dfcca77c5aded6a7ce
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9162
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-11-02 13:39:04 +00:00
Antonio Borneo
88b9bd396d target: cortex-m: fix support for armv8m caches
Scan-build is unable to correctly follow the deferred loading of
queued read, finalized by the atomic write, thus it incorrectly
claims that the arrays d_u_ccsidr[] and i_ccsidr[] could carry
not initialized values:

	armv7m_cache.c:154:31: warning: 1st function call argument
	is an uninitialized value [core.CallAndMessage]
	   cache->arch[cl].d_u_size = decode_ccsidr(d_u_ccsidr[cl]);

	armv7m_cache.c:172:29: warning: 1st function call argument
	is an uninitialized value [core.CallAndMessage]
	   cache->arch[cl].i_size = decode_ccsidr(i_ccsidr[cl]);

Initialize the arrays to zero to hide these false positive.

Change-Id: I6d1e88093cb8807848643139647a571c1b566aa8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 04da6e2c62 ("target: cortex-m: add support for armv8m caches")
Reviewed-on: https://review.openocd.org/c/openocd/+/9167
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-10-18 08:59:44 +00:00
Antonio Borneo
85542c1c5c helper/log: mark 'fmt' argument of alloc_*printf() as not NULL
Even after commit e12ceddd5e ("helper/log: mark `fmt` argument
of `alloc_vprintf()` as format string"), the GCC compiler still
reports that alloc_vprintf() could call vsnprintf() with a NULL
format parameter.

Inform the compiler that alloc_vprintf() cannot accept NULL as
format string.
Add an assert() in alloc_vprintf() so even compilers that do not
use the function attribute 'nonnull' will play safe.
While there, extend the same fixes to alloc_printf() too.

Change-Id: Idfa4fe9c6dfb2acfbf434c392237937ae03f0e8a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9166
Tested-by: jenkins
Reviewed-by: Anatoly P <anatoly.parshintsev@syntacore.com>
2025-10-18 08:58:55 +00:00
Antonio Borneo
557a2082b1 openocd: don't test 'debug_level' directly
Use the macro 'LOG_LEVEL_IS()' to test 'debug_level'.

While there, use the macro 'LOG_LVL_*' in place of the numeric
value.

Skip all riscv code, as it is going to be updated soon from the
external fork.

Change-Id: Icad7e879e040d3b9cf1cc004c433f28725017493
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9070
Tested-by: jenkins
2025-10-18 08:37:13 +00:00
Marc Schink
3fd9759415 adapters/cmsis-dap: Fix build without libusb
The cmsis-dap core driver depends on libusb-related code which breaks
the build when libusb is not available.

Remove libusb dependency of the core driver to fix the build issue. For
now, use an own timeout #define with the value of LIBUSB_TIMEOUT_MS but
timeout handling should be better moved to the backends. However, this
should be addressed in a dedicated patch.

Change-Id: Ic5da392f8ab26b47466be199432432cdc08712ab
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9161
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: <niklaus.leuenb@gmail.com>
Tested-by: jenkins
2025-10-13 07:56:35 +00:00
Marc Schink
910e6ba2f0 adapter/parport: Add device file support
Allow to specify the parallel port by its device file. Deprecate port
number support but keep it for backward compatibility.

This is one necessary step to remove direct I/O support for the parallel
port driver.

While at it, consistently return ERROR_JTAG_INIT_FAILED in case of a
failure in parport_init().

Change-Id: Ie68087f05ece4b32ccab9d9bdfbf7e1a779e9031
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9152
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-10-11 16:15:10 +00:00
Marc Schink
39ed0b0bba adapter/parport: Deprecate direct I/O support
We deprecate direct I/O support in favor of ppdev for the following
reasons:

  - Linux supports ppdev since ~2.4 (released ~24 years ago) and it is
    enabled by default on major distros (Ubuntu, Fedora). So it is
    effectively ubiquitous
  - FreeBSD provides no direct I/O support, so ppdev (ppi) is the only
    viable option
  - Direct I/O requires root/elevated privileges which is inadvisable
  - Removing direct I/O reduces build and driver complexity and yields
    a smaller, easier-to-maintain codebase
  - Supporting only ppdev allows us to simplify the codebase by using
    device files (e.g., /dev/parport0) instead of numeric identifiers

Windows is the only rationale to keep direct I/O, but the user base
appears minimal to nonexistent and no active contributors can test the
Windows driver.

Change-Id: Ia6d5ed6e8c5faa2a9b4919ca97c5cf9033372a64
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9151
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-10-11 16:14:07 +00:00
EasyDevKits
5fa74d4ee8 jtag/ch347: Refine driver and configs for EasyDevKits adapters
This commit improves support for CH347-based JTAG adapters:

- configure.ac: removed "Mode3" restriction (CH347F does not require mode).
- configs: added board config for ESP32-WROVER-E WCH JTAG DevKit and
  ESP32-WROVER-E FTDI JTAG DevKit
- ch347 driver: removed `ch347 activity_led` command; activity LED
  is now controlled via the generic `adapter gpio led` command.
- doc/openocd.texi: updated documentation accordingly.

Change-Id: I5524290297adcc004e00af919181868d2b6303af
Signed-off-by: EasyDevKits <info@easydevkits.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9015
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-10-11 16:02:18 +00:00
Antonio Borneo
8b43a967e5 target: cortex_m: add comment for breakpoint of length 3
Add a comment in the breakpoint code to clarify the check for the
odd breakpoint length of 3 bytes, introduced by [1].

[1]: commit 0a5e03c12a ("cortex_m.c: Use two byte breakpoint for
     32bit Thumb-2 request").

Change-Id: I024863d10078b5d9062c876aa59ccf70a81bf641
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9139
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-10-11 15:57:06 +00:00
Antonio Borneo
04da6e2c62 target: cortex-m: add support for armv8m caches
Cores like Cortex-M7, Cortex-M55 and Cortex-M85 can have either
D-Cache and/or I-Cache.
Using SW breakpoints in RAM requires handling these caches.

Detect the presence of cache at examine.
Detect cache state (enable/disable) at debug entry.
Take care of caches synchronization through the PoC (usually the
SRAM) while setting and removing SW breakpoints.
Add command 'cache_info' to check cache presence and size.

Change-Id: Ice637c215fe3042c8fff57edefbab1b86515ef4b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9077
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-10-11 15:56:41 +00:00
Marc Schink
2abf8daa80 target/cortex_m: Remove echo of 'reset_config' command
Do not echo the selected reset config. This is one of many changes to
make the behavior of Tcl commands more consistent.

This also avoids stray and confusing messages in the output of OpenOCD.
For example, the "reset_config" line here:

  Open On-Chip Debugger 0.12.0+dev-00802-gb7f0145fc-dirty
  Licensed under GNU GPL v2
  For bug reports, read
  	http://openocd.org/doc/doxygen/bugs.html
  cortex_m reset_config sysresetreq
  Info : Listening on port 6666 for tcl connections
  Info : Listening on port 4444 for telnet connections

While at it, fix some coding style and command handling issues.

Change-Id: I3b3d8687af1d23a2dc1764f29b52dc607b80cb59
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8638
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-10-11 15:51:37 +00:00
Samuel Obuch
e5888bda38 target/breakpoints: drop duplicate breakpoint/watchpoint "clear_target" functions
We need to cleanup watchpoints on all targets in SMP group when GDB
connects. Otherwise, the targets will not be consistent.
Once thats fixed, both *_clear_target functions clearly duplicate
the corresponding *_remove_all functions.

Change-Id: I8e85dbc66fd3e596990d631ed2aed22959a8ca60
Signed-off-by: Samuel Obuch <samuel.obuch@espressif.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9086
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-09-30 07:22:37 +00:00
Brian Kuschak
896738264e jtag/drivers/cmsis_dap_tcp: fix socket handling for Windows
Windows does not support socket recv() with a combination of MSG_PEEK
and MSG_WAITALL flags. Work around this limitation in a way that works
for both Windows and other platforms.

Change-Id: Ib77e2cc872e5fe3d1fc41034010b86390131fff3
Fixes: https://sourceforge.net/p/openocd/tickets/457/
Signed-off-by: Brian Kuschak <bkuschak@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9136
Reviewed-by: IRON ALEKS <8ironaleks8@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-09-27 15:22:27 +00:00
Tomas Vanek
32afb0ab04 jtag: linuxgpiod: log memory allocation errors
Log error in case of NULL calloc() return.

Change-Id: I40c5cba5b92cd39e9a8f7e6d420e11afc8747b3e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9119
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-09-27 14:56:40 +00:00