Commit Graph

391 Commits

Author SHA1 Message Date
Liviu Ionescu 45921eecd8 target/riscv: fix trailing spaces 2018-06-12 23:58:56 +03:00
Liviu Ionescu 8022a315a6 target/riscv: explain why arm commands are used 2018-06-12 23:54:41 +03:00
Liviu Ionescu 08a814686d target/riscv: add semihosting support
- use the semihosting_common code
- to enable it, use the same commands as for arm

Signed-off-by: Liviu Ionescu <ilg@livius.net>
2018-06-12 18:21:01 +03:00
Tim Newsome 2a6332f620 Update debug defines to match spec
The main difference is we need to deal with hartsello/hartselhi. (Note
that there's a compile-time limit to 16 harts, but that can be changed.)
My largest target has 4 harts, so I can't tell how well this really
works. But it doesn't break anything.

Fixes #240.

Change-Id: Ie1a2a789b5e00f55174994568749da1cf3a33b92
2018-06-06 13:43:35 -07:00
Tim Newsome ab7ab8a867 Merge pull request #261 from riscv/trigger_enum
Delay trigger enumeration until it's required.
2018-05-25 11:52:10 -07:00
Tim Newsome c3ffbc66e6 Merge pull request #257 from riscv/comment
Comment riscv_set_register, register_write_direct
2018-05-22 14:39:28 -07:00
Tim Newsome b629bbeade Delay trigger enumeration until it's required.
This improves startup time, which is important when connecting to
simulators. One problem is that triggers that are set when the debugger
connects are not cleared until enumeration happens. Execution may halt
due to a trigger set by a previous debug session, which could confuse
the user. If this happens, triggers will be instantly enumerated, so it
will only happen once per session.

Change-Id: I3396f713f16980a8b74745a1672fe8b8a2d4abae
2018-05-22 13:07:25 -07:00
Dan Robertson 0493ff81a1 Fix posible null deref in get_target_type
A null deref occurs if riscv_deinit_target is called and the
target has not been initialized.

Change-Id: Ic34057508ed6686eb48e9fe8220110c42ba2fc5e
2018-05-22 02:57:16 +00:00
Tim Newsome 0ad060d97a Review feedback.
Change-Id: If58c011fc8d89d329d65a6c624ffb631f111cef2
2018-05-17 18:08:08 -07:00
Tim Newsome 41c42bf2df Comment riscv_set_register, register_write_direct
Fixes #241

Change-Id: Ia199f15106a0bda465d3918d052ddd4d03655031
2018-05-17 18:01:00 -07:00
Tim Newsome bb86173f37 Merge pull request #251 from riscv/from_upstream
From upstream
2018-05-17 16:47:48 -07:00
Megan Wachs 802c3b4003 riscv: remove unexpected check during reset
I'm not sure what this check is adding, and it causes problems for implementations that take some time to report that they are halted out of reset (e.g. by executing Debug ROM).
2018-05-16 22:25:38 -07:00
Tim Newsome dabaf170ba blank_check_memory prototype has changed.
Just remove our nop implementation. The default behavior when this is
left NULL does the same thing.

Change-Id: I865976c694d24661941584cb0efc92fc26612316
2018-05-08 15:21:49 -07:00
Tim Newsome 2a103bae44 Don't error if hart select isn't implemented.
It's not implemented for 0.11 because we don't need it. Returning error
caused 0.11 targets to not be debuggable since change
848062d0d1.

Change-Id: I8b04a1fcf3c3e8bf8340cbf39aaf475d2a213519
2018-05-07 15:16:57 -07:00
Tim Newsome 909c9d4ab2 Conform to OpenOCD style
Change-Id: I3954a8ac254b460560fa1414c5921777e4005645
2018-05-03 17:58:44 -07:00
Tim Newsome 487501e761 Merge branch 'riscv' into optimize
Change-Id: I2693eb05dee72acd2df5d8594c51e9da08ea1cc6
2018-05-03 16:02:59 -07:00
Tim Newsome 67b4e2c522 counter*h registers only exist on RV32
Fixes #245.

Change-Id: If05ec9773dc9975931434f09c431eba122a6e8d0
2018-05-03 12:26:30 -07:00
Tim Newsome 292180fb44 Merge pull request #246 from darius-bluespec/sysbus-bugfix
Bug fixes for system bus access
2018-05-01 14:12:48 -07:00
Darius Rad 31494f68a4 Properly retry system bus access if busy error was detected. 2018-05-01 11:45:24 -04:00
Darius Rad cb282e81bc Fix polling for system bus busy. 2018-05-01 11:45:24 -04:00
Tim Newsome b62c014bdc Merge branch 'riscv' into notice_reset 2018-04-30 13:36:06 -07:00
Tim Newsome 9a69c1c096 Fix mingw32 build.
Change-Id: If7a57749ba8c49385a4020ce8d2d8dbb94242122
2018-04-20 16:28:24 -07:00
Tim Newsome 4593659edf Fix error messages for reset dmi timeouts.
Change-Id: I00869ba20db6f27415af8e53e7b3e67741bf894d
2018-04-20 15:10:56 -07:00
Tim Newsome ba2174249d Make encoding.h pass style guide.
There's a manual step in commenting this out, but this file changes very
rarely.

Change-Id: I332d6490940ecc81e18c3b112a7ba415331b9c86
2018-04-20 14:47:27 -07:00
Tim Newsome b5dae238a1 Fix comments in encoding.h.
This was updated in the source a long time ago:
https://github.com/riscv/riscv-opcodes/commit/25881d8a221393cfd996ec074d8003ef31bfc5a6

Change-Id: Ia158205d046522c6802a3a32b330759f5e65566f
2018-04-20 14:47:27 -07:00
Tim Newsome 005630d24d Use reset timeout to read dmstatus out of reset
Change-Id: I74cc6a1e006269270c5197994d21523d01206141
2018-04-18 14:31:00 -07:00
Tim Newsome 69a426038d Enforce OpenOCD style guide. (#239)
* Enforce OpenOCD style guide.

Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8

* Fail if `git diff` fails

Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9

* Maybe every line gets its own shell?

Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6

* Maybe this will error properly.

Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9

* Take different approach than merge-base

Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1

* Fix style issues.

Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
2018-04-18 13:11:08 -07:00
Tim Newsome 1fda89c3ce Only write hartsel if we're changing it.
DebugBreakpoint went from 2.94s to 2.74s.

Change-Id: Ia3ab857aea89fb83f0bcdd9a6bb69f256bde13dd
2018-04-09 15:13:24 -07:00
Tim Newsome 238b1e9f06 Cache registers while halted.
This saves us from re-reading s0 before doing just about anything
program buffer related.

Improves DebugBreakpoint from 3.01s to 2.89s. Feels like the improvement
should be larger than that. Maybe my metric isn't very good.

Change-Id: I85e1a1ddbf09006d76c451a32048be7b773dcfe9
2018-04-06 15:52:40 -07:00
Tim Newsome 5c0a9a9ee4 Just read abstractcs once when executing a command
DebugBreakpoint went from 3.41s to 3.05s!

Change-Id: Icfc4ad5fb663b3607bf2027fda744b43be662fc5
2018-04-05 17:59:07 -07:00
Tim Newsome 6030644a9d Track misa per-hart even in -rtos mode
This works around some side effects of the -rtos hack, namely that we
were unable to set hardware breakpoints on harts whose misa differed
from the first one. There may be other bugs like this one lurking
elsewhere. The only proper solution is for gdb to have a better user
interface when talking to a server that exposes multiple targets, but
that's a very big project.

This fixes #194.

Change-Id: I81aedddeaa922d220e936730e9c731545953ae21
2018-04-03 15:12:19 -07:00
Tim Newsome eeae8c4261 Add gdb_report_register_access_error command
This replaces the earlier mechanism which would propagate errors only
for targets that decided they wanted to. It was suggested by Matthias
Welwarsky from the OpenOCD team.

Change-Id: Ibe8e97644abb47aff26d74b8280377d42615a4d3
2018-04-02 13:37:53 -07:00
Tim Newsome 755c6a4caa Add wall clock timeout to dmi_op()
If the target is held in reset we'd keep adding more delays, and since
those grow exponentially they'd get so huge it would take forever to
exit out of the loop.

Change-Id: Ieaab8b124c101fd1b12f81f905a6de22192ac662
2018-03-30 15:24:16 -07:00
Tim Newsome 58a2994b00 Merge pull request #231 from riscv/auth
Fix auth error message.
2018-03-30 14:02:29 -07:00
Tim Newsome 3c7c7e26a4 Merge pull request #230 from riscv/deleg
Make m*deleg regs conditional on U/S/N
2018-03-30 14:02:13 -07:00
Tim Newsome 4ee7d5373d Fix auth error message.
Change-Id: I79b72325e9a6b85f8b67df8e9837a54cfce928f0
2018-03-30 13:21:00 -07:00
Tim Newsome 224e7b4f16 Once more... Less sloppy this time.
Change-Id: I4a24e777af3a0d8e072bc1bce0b314738393aa86
2018-03-27 11:42:32 -07:00
Tim Newsome 55e427b72b Don't rely on havereset when deasserting reset.
This removes the need for the supports_havereset config option as well.

Change-Id: Ic4391ce8c15d15e2ef662d170d483f336e8e8a5e
2018-03-27 11:31:39 -07:00
Tim Newsome 0c05aafbf8 Fix m*deleg logic.
Change-Id: Ieda035280334f8e7dc78c9fbc2bdbea7c565d2de
2018-03-26 16:00:34 -07:00
Tim Newsome b6dca68b2e Make m*deleg regs conditional on U/S/N
Change-Id: I544fc15625400d8ad64d4a65f0fc9d77f428ca84
2018-03-23 13:43:12 -07:00
Tim Newsome c534a37fc3 Make reset work again for multicore
Both regular multicore and RTOS hack methods.

Change-Id: I9a0998de0f33ef8a4d163f36ddf01c7675893b3d
2018-03-23 12:53:24 -07:00
Tim Newsome d7282d0bfe Add set_supports_havereset
This lets reset work on targets that don't implement havereset.

Change-Id: I09eb20970fac740eb6465541db6e739ae3e6b0d5
2018-03-22 12:44:15 -07:00
Tim Newsome e5591c2584 Halt the target again if it was reset while halted
Change-Id: I59707e7b2e1646c312d4eb8e96e9d7dfd1e128c2
2018-03-20 12:34:17 -07:00
Tim Newsome 52eabbd2a5 Add riscv set_prefer_sba
This allows a user to tell OpenOCD to prefer system bus access for
memory access, which can be useful for testing, or when there really is
a difference in behavior.

Change-Id: I8c2f15b89a2ccdae568c68ee743b75a74f9ad6bd
2018-03-19 14:09:56 -07:00
Tim Newsome d5b450c508 Fix build, broken by b7c5c5d228.
Change-Id: Iee55d799e14376ec5079d7db5fc6369e85368212
2018-03-19 12:56:05 -07:00
Tim Newsome 40e0c5b976 Format error messages.
Change-Id: I50c21319765e1ead279223466ed02a06ecf6a522
2018-03-19 12:46:10 -07:00
Tim Newsome b7c5c5d228 Merge pull request #225 from riscv/old_bus2
Support v0 System Bus Access
2018-03-19 12:11:28 -07:00
Tim Newsome 4d2d1f7324 Notice when a hart has reset.
Attempt to notify the user.
Deal correctly with a halted target that is suddenly running.

Change-Id: Ib0e0aa843d1da22df673713687ec884f6af14949
2018-03-16 15:04:14 -07:00
Tim Newsome fd2759a63d Clear havereset in examine() and deassert_reset().
Change-Id: I89f32a44ebd6f3df0d0e2f6b54b111daa6ab06f7
2018-03-16 15:03:31 -07:00
Tim Newsome 848062d0d1 Propagate errors in more places
Change-Id: I5a7594d4b44c524537827f403348d0c10814546f
2018-03-16 15:03:31 -07:00