Rename the _swd_native.cfg files as -self-hosted.cfg files as a better
representation of what we are using the configuration files to be.
Change-Id: I4eb469a219b83de6a9e7a8dfef5607306f59a7cd
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9206
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
As part of the cfg file cleanups, let us move the TI evms, launchpads
and other development platform configuration files to board/ti folder.
While at this, drop the "ti_" prefix as the folder structure gives us
the details anyways.
Change-Id: I929b88e0cf6527f3181820ad0b9b4744185eabaf
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9205
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Move the BeagleBoard.org Foundation boards to it's own folder. This
allows additional support such as BeagleV-Fire and other non TI SoC
vendor support to be subsequently added.
While doing this,
* Use "-" as separator for the file names as recommended
by coding standards.
* To maintain compatibility, add the non-trivial renames to
file_renaming.cfg
Change-Id: Ie916c9bf81fc3922bf19ed9ed2db841549d29ca9
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9204
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Move the ti targets to a TI folder. Since the folder is ti, we can
drop the "ti" prefix from the files themselves.
Done via the following script:
mkdir target/ti
FILES=`ls target/ti*.cfg target/omap*.cfg target/am335x.cfg
target/amdm37x.cfg target/icepick.cfg target/stellaris.cfg
target/davinci.cfg`
for cname in $FILES
do
bname=`basename $cname`
nname=`echo $bname|sed -e "s/^ti-//g"|sed -e "s/ti_//g"`
npath="target/ti/$nname"
echo "$cname => $npath"
fref=`git grep $cname .|cut -d ':' -f1|sort -u`
sed -i -e "s&$cname&$npath&g" $fref
git mv $cname $npath
done
Change-Id: I9f94dc6bb01f73721d4ff96be92cb51de2cbf0e2
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9203
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For stm32l4, stm32wbx, stm32wlx the target tcl scripts try to change the
MSI oscillator's speed to 24 MHz before boosting the interface
frequency, but don't clear the RCC_CR_MSIRANGE field correctly before.
This causes the register write access to fail and leaves the clock
frequency unchanged. For the stm32wlx, the script also neglects to set
the MSIRGSEL bit, such that the frequency setting is not actually
applied.
The issue appears to not cause a problem when using an ST-Link adapter.
When using an FT4232HP, communication to the target fails after the
reset-init event, possibly because this adapter actually supports the
higher interface frequency.
This commit fixes the register accesses to make sure the RCC_CR_MSIRANGE
is cleared to zero before OR-ing the new value. For the stm32wlx, also
set the MSIRGSEL bit. Just to be safe, also fix the write access to the
FLASH_ACR_LATENCY field to clear it before OR-ing, even though it should
be zero at reset anyways.
Change-Id: Ie8320fa6ee2086981c0b1f3c18f51e171709078d
Signed-off-by: Niklas Gürtler <profclonk@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9282
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
These changes bring over some lines from the independently-developed
gd32vf103.cfg that I contributed[1] to the riscv-openocd fork of
OpenOCD. They're all minor, so I'm squashing them into one review. The
changes are as follows:
- Add boundary scan TAP.
- Mention inconsistency of CPU ID between vendor SDK and real hardware.
- Specify that there's no MMU so we don't look for one at runtime.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Change-Id: Ie8033eff436d6dbdc3eab156769a8908ccb547f6
Reviewed-on: https://review.openocd.org/c/openocd/+/6959
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The esirisc_trace.c uses macro BIT_MASK(), same name as a macro
from helper/bits.h
Drop the macro definition and use GENMASK() instead.
Change-Id: I0cc6a58e5aff3f48fa9a79a99bd28124f334c4e2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9168
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Use command_print() in order to provide an error message to the caller.
While at it, fix the return values.
Change-Id: I0f8d3466ab2729d8cca6cf4c1cff51d67982c373
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9267
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
By reorganizing the free() of the service and its subfields, the
patch reported in 'fixes' exposes a new double free().
Issue detected by 'scan-build'.
Fix it.
Fixes: 5ff384be08 ("semihosting: fix memory leak and double free")
Change-Id: Ief4262e98c9ecdca39d4e2d77e7a0ea87cfa198c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9266
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
cJTAG OSCAN1, in lieu of 4-wire JTAG, is starting to be a configuration
option for some SiFive hardware. An FTDI-based adapter that can be
configured to drive the bidirectional pin TMSC is assumed for this
topology. Specifically, the Olimex ARM-USB-TINY-H with the ARM-JTAG-SWD
adapter, connected to a SiFive cJTAG-enabled target board is the only
known concrete topology, currently. But in theory, other FTDI based
devices that can drive a two-wire bidirectional signaling pattern could
be made to work in this scheme in the future.
These code changes are offered as a way to drive that topology. It's
translating IR/DR and JTAG traversal commands to the two-wire clocking
and signaling.
See:
- https://github.com/riscv-collab/riscv-openocd/pull/320
- https://github.com/riscv-collab/riscv-openocd/pull/736
Signed-off-by: Greg Savin <greg.savin@sifive.com>
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Change-Id: Ia1daa2c01227c4b0005be947b2bb0de81a800874
Reviewed-on: https://review.openocd.org/c/openocd/+/6981
Tested-by: jenkins
On Cortex-M7 only, several registers in System Control Space (SCS)
are not accessible when the CPU is under reset, generating a bus
error.
This causes OpenOCD to fail examining the CPU when the board reset
button is pressed or when the flag 'connect_assert_srst' is used
on 'reset_config' command.
Introduce a deferred identification of the cache and run it during
polling and at target halted (just in case of polling disabled).
Change-Id: Ia5c582ae95f825c5fb8c2dcfb320142f7ac04a9f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9232
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
In a SMP configuration 'resumed' event was emitted only for
the active core, in contradiction to 'halted' event, which
gets emitted for all cores from the SMP group:
> resume
target event 3 (resume-start) for core stm32mp15x.cpu0
target event 2 (resumed) for core stm32mp15x.cpu0
target event 4 (resume-end) for core stm32mp15x.cpu0
target event 7 (gdb-start) for core stm32mp15x.cpu0
> halt
target event 0 (gdb-halt) for core stm32mp15x.cpu1
target event 1 (halted) for core stm32mp15x.cpu1
target event 0 (gdb-halt) for core stm32mp15x.cpu0
target event 1 (halted) for core stm32mp15x.cpu0
target event 8 (gdb-end) for core stm32mp15x.cpu0
Emit 'resumed' event in cortex_a_restore_smp().
While on it replace adding the returned errors together
with the proper error handling.
Change-Id: I9debef0884519cde767707f78f163b136ecc7aa5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9244
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Add command to re-load option bytes.
Tested with STM32L072CZ and STM32L152RCT6.
Change-Id: I5653f2222a48af1fe0332d4bdc3552e481e375d0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8998
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Cherry-picked from [1].
To replicate the issue that this fixes:
1. Connect to a multi-hart RISC-V target configured as an SMP group.
2. Start a GDB instance against the running OpenOCD.
3. Observe that GDB might display "warning: multi-threaded target
stopped without sending a thread-id, using first non-exited thread."
4. Set a breakpoint in code that any non-hart-0 hart is expected to
reach (but hart 0 is not expected to reach).
5. Allow a non-hart-0 hart to reach the breakpoint.
6. Remove the breakpoint.
7. Do a few sequential `stepi` commands in GDB.
8. Observe that GDB displays "Switching to Thread 1" even though the
thread that was just single stepped was not Thread 1 in GDB. Also
observe that the register values in GDB correspond to the thread that
was single-stepped, not Thread 1. Basically GDB erroneously starts to
consider thread 1 to be current, when in fact the thread that was
single-stepped is still current.
The changes in this pull request are intended to avoid the erroneous
"Switching to Thread 1" described in (8) above.
What was happening was that, in a couple areas of code, non-hart-0 harts
weren't seen as belonging to an RTOS module, and this had the effect of
(1) bypassing `hwthread_update_threads()` being called after a halt; (2)
omitting a thread ID in a stop reply over GDB remote protocol connection
(requiring GDB to take an arbitrary guess of current thread id, a guess
that is wrong unless the current thread happens to be hart 0).
Link: https://github.com/riscv-collab/riscv-openocd/pull/675 [1]
Change-Id: I9872062dfa0e3f1ca531d282d52a1b04c527546a
Signed-off-by: Greg Savin <greg.savin@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9183
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Commit 0847a4d7fb ("jtag/commands: Use 'unsigned int' data type")
introduced bug when changing loop variable from `int` to `unsigned int`.
Instead of getting negative and terminating the loop, the value wraps
around to `INT_MAX` and the loop never finishes.
Change-Id: I055025a1f8eb4abe50955607b3e89530dfd92af4
Signed-off-by: NikLeberg <niklaus.leuenb@gmail.com>
Fixes: 0847a4d7fb ("jtag/commands: Use 'unsigned int' data type")
Reviewed-on: https://review.openocd.org/c/openocd/+/9078
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Gdb uses length 3 to set breakpoint on a 4 byte Thumb-2
instruction. Without this patch a breakpoint on down aligned word
address was set. If the requested address was not word aligned,
the breakpoint triggered at previous instruction and was not
recognised properly by gdb.
Set breakpoint on whole word if aligns with requested address,
otherwise use length 2 and set byte mask.
Change-Id: I12d1c57b7154e64abdf23dd7cd31714f9d8ec6f0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9211
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Some targets have no means to find out which watchpoint triggered
the debug halt. Resolve properly the trivial and most used case
when only one watchpoint is set.
Change-Id: I683933ec43e6ca0fed84a08a2aa222ed8a6e277f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9210
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Resolve two problems that occurred when working with semihosting service
through multiple connection cycles (connect-disconnect-reconnect):
1) Double free:
When the same service handles multiple connections sequentially,
the same memory gets freed repeatedly, because function
'semihosting_service_connection_closed_handler()' incorrectly frees
service->priv->name on every connection closure.
2) Memory leak:
Function 'free_services()' misses service->priv->name cleanup for
semihosting redirection. Memory remains allocated after service
destruction.
The solution introduces a new 'dtor()' field in the service structure
that is called exactly once during free_service() execution.
To reproduce the issue, you can do the following:
1. openocd -f target.cfg -c init -c 'arm semihosting enable' -c
'arm semihosting_redirect tcp 4445'
# in another terminal
2. nc localhost 4445
3. Ctr+C
4. nc localhost 4445
5. Ctr+C
Change-Id: I0dc8021cc3e21c5af619c71a1821a1afe9bffe78
Signed-off-by: Kulyatskaya Alexandra <a.kulyatskaya@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9196
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
on ARMv6M variants (mainly Cortex-M0 and Cortex-M0+) and
on ARMv8M baseline (e.g.Cortex-M23). The devices do not have
BASEPRI and FAULTMASK functionally implemented and the corresponding
register bits are just read as zero, write ignored.
ARMv6-M Architecture Reference Manual:
Table D3-2 Programmers’ model feature comparison
Reduced exception priority management: PRIMASK
special-purpose register. No support for changing the
priority of configurable exceptions when they are active.
Armv8-M Architecture Reference Manual:
B3.32 Special-purpose mask registers, PRIMASK, BASEPRI, FAULTMASK,
for configurable priority boosting
A PE without the Main Extension implements PRIMASK, but does not
implement FAULTMASK and BASEPRI.
Change-Id: I332cc79718852c0109148817a214a2657960370b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9174
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Some link if not anymore accessible.
Replace them with current one and add a backup in case one gets
not accessible anymore.
Change-Id: Iffca714555e94e5322a5daac1ea756e36bbd3a8f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9188
Tested-by: jenkins
Commit 93f16eed4d ("command: fix OpenOCD commands return value
for next jimtcl") aligns the return of OpenOCD Tcl commands to the
standard Tcl error codes.
This has the side effect to hide the internal OpenOCD error codes
(e.g. ERROR_FAIL = -4) from the Tcl environment. These codes are
for internal use, can change during OpenOCD development and should
not be exposed to the user.
Nevertheless, some ACI test has been instrumented to check such
values and there is a requirement to make them available, possibly
without breaking the Tcl language rules.
Tcl allows procedures to return, through the 'return' command [1]:
- the result text;
- a return code like 'ok' or 'error';
- an optional 'errorcode';
- ...
The optional 'errorcode' can be exploited to propagate the OpenOCD
error code to the Tcl script for ACI test purpose.
It would be equivalent of considering the OpenOCD commands as Tcl
procedures that either returns as:
return -code ok 'command output text'
or return an error as:
return -code error -errorcode {OpenOCD -4} 'error text'
where '-4' is the OpenOCD value for ERROR_FAIL.
Tcl stores the errorcode in the global variable 'errorCode' that
can be easily accessed within a Tcl script [2].
The variable 'errorCode' is by default set to 'NONE' and has to be
set to a Tcl list. The first element of the list identifies the
general class of errors and determines the format of the rest of
the list. This allows the required flexibility to propagate the
OpenOCD error codes in a format unique that does not impact other
Tcl functionality.
Propagates the OpenOCD error code in the Tcl global variable
'errorCode' as a Tcl list formatted as {OpenOCD %s}.
Modify the test script to check for OpenOCD error code.
Link: https://www.tcl-lang.org/man/tcl8.6/TclCmd/return.htm [1]
Link: https://www.tcl-lang.org/man/tcl8.6/TclCmd/tclvars.htm [2]
Change-Id: Ia5007e04b3c061a0f7a74387b51ab2a57c658088
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9186
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
We want the output of the 'usage' command to become the output of
the current command that has triggered the syntax error.
Don't use command_run_linef(), as it will first print the message,
then pass it to the current command that will use it again.
Replace command_run_linef() with Jim_Eval..().
Change-Id: Icefa87746156e6e8758026c0fdc5e02b440b3aaa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9185
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
The commands 'help' and 'usage' still rely on LOG_USER_N() and
LOG_USER() for the output.
Convert them to command_print().
Change-Id: I6e77dd761b61344ff797f661456896388bba89aa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9184
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Tested-by: jenkins
Commit 4afa32ece1 ("aarch64: unify armv7-a and armv8
debug entry decoding")
probably unintentionally removed DSCR_ENTRY_VECT_CATCH from
reported debug entry reasons. Note the discrepancy between
'case DSCR_ENTRY_BKPT_INSTR:' and its comment.
Hitting vector catch was reported as DBG_REASON_UNDEFINED.
DBG_REASON_UNDEFINED disturbed hwthread/gdb cooperation and
gdb reported the wrong thread as stopped by SIGTRAP.
Revert to the original functionality and report vector
catch as a breakpoint.
Change-Id: I12e938182cff8f633decba340000cfbb7b112ae3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9209
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
gdb uses this mark when creating a dummy frame for
manual call of a function by gdb command.
With the original setting all registers as caller_save = false
call command in gdb always clobbers r0, r1 and pc
and some other registers depending on the called function.
Set 'save-restore' for all registers but banked ones.
Change-Id: I16c49e4bf8001e38d18ce8861ca65988b08ccc88
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9208
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Commit b5d2b1224f ("target/cortex_a: add hypervisor mode")
added sp_hyp, spsr_hyp registers with gdb_index 51 and 52
but did not moved FP regs enum base starting from 51.
Move FP registers indices to make room for added registers.
Change-Id: I4338777545918fdf62016e06764308dacea61e98
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9235
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Switch to LOG_TARGET_DEBUG() and LOG_TARGET_ERROR()
to make analyzing logs of multicore system easier.
Not changed completely in the whole file, the changes were focused
to halt and resume.
Change-Id: I055ad682d3098d5c301a111605d57e504f877b4c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9207
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Change 7732: jtag/drivers/bcm2835gpio: Support all 54 GPIO pins [1]
reduces the time needed for GPIO handling.
Adjust the speed offsets to the new and faster bcm2835gpio code.
Measured with Sigrok/PulseView, sampled at 800 MHz.
Configured as SWD with the fast path in the driver - other
modes are expected to be slower.
Adjusted to keep all half periods of SWCLK in the sampled poll
sequence longer or equal than the half period of the nominal
adapter speed.
Link: [1] https://review.openocd.org/c/openocd/+/7732
Change-Id: Ia9e932dfd7547c8011c1d20d9e90bc0294050e8a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9234
Tested-by: jenkins
Reviewed-by: Vincent Fazio <vfazio@gmail.com>
Previously, only the first 32 GPIO were supported on the BCM2835.
Performance was cited as being the primary justification for not
supporting all 54 pins, notably:
1. There is overhead for calculating the memory offset for the pin
2. GPIO values cannot be written in bulk if pins span memory offsets
Now, all 54 GPIO pins are supported by the driver.
Since pins may use different offsets, multiple pins cannot be toggled
with one memory store. Multiple stores now need to occur when one
sufficed before.
To offset some of the performance overhead for the additional stores,
memory addresses, masks, and shift bits are calculated once and cached
into struct. Calculating these once reduces the number of instructions
a function needs to run in order to manipulate a given GPIO.
The following functions have been updated to leverage the new struct
as they represent some of the hottest paths:
bcm2835_swdio_drive
bcm2835_swdio_read
bcm2835gpio_swd_write_fast
bcm2835gpio_read
bcm2835gpio_write
For `bcm2835gpio_swd_write_fast`, performance should be roughly the same
as the number of memory stores hasn't changed.
For `bcm2835_write`, there is a slight performance degradation since
TMS/TDI/TCK are set separately which incurs an additional memory store.
Instruction counts across the above functions are reduced by ~10-40%.
Macros to access registers have been reworked into inline functions to
support access to all pins and to avoid checkpatch headaches.
The `initial_gpio_state.output_level` member has been retyped to bool to
better align with the expected values.
Support for adjusting pads for the expanded pin range has been left out
as support for manipulating these settings should be moved out of this
driver and into its own utility.
Change-Id: I18853d1a2c86776658630326c71a6bf236fcc6da
Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7732
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Restarting the program buffer memory write pipeline when the write of
the last element resulted in the busy response triggers an extra memory
wrtite, that is cought by an assertion:
```
src/target/riscv/riscv-013.c:5048: write_memory_progbuf_inner: Assertion
`next_addr_on_target - args.address <= (target_addr_t)args.size *
args.count' failed.
```
Change-Id: I0f27145cad24686cf539aebfea7f6578b7cd78ab
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9233
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This is a cherry-pick of:
Link: efce094b40
Fake step is a hack introduced to make things work with real RTOSs that
have a concept of a current thread. The hwthread rtos always has access
to all threads, so doesn't need it.
This fixes a bug when running my MulticoreRegTest against HiFive
Unleashed where OpenOCD would return the registers of the wrong thread
after gdb stepped a hart.
Change-Id: I64f538a133fb078c05a0c6b8121388b0b9d7f1b8
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9177
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
For all the targets that support SMP, the sub-commands 'smp' and
'smp_gdb' are under the arch name:
- aarch64 smp
- cortex_a smp
- cortex_m smp
- esp32 smp
- mips_m4k smp
Keep consistency among OpenOCD commands, and move under the arch
name 'riscv' the SMP subcommands.
Change-Id: Iede7841c2df8161ff2c6fea3be561d1f26ad6cd0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9165
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
The buffer 'args' is allocated and freed in the caller function
parse_reg_ranges().
There is no reason to free it, only in some special case, in the
called function parse_reg_ranges_impl().
Scan build reports:
src/target/riscv/riscv.c:4537:2: warning: Attempt to free
released memory [unix.Malloc]
Drop the free() in the called function.
Change-Id: I2e308670c502f8e140603b4e5c16fc568088e1a8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9164
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The array 'wps_to_enable' is never freed.
Scan build reports:
src/target/riscv/riscv.c:4271:6: warning: Potential leak
of memory pointed to by 'wps_to_enable' [unix.Malloc]
Add the needed free().
While there, check if the allocation is successful.
Change-Id: I00e7ade37a43a97dcc245113ad93c48784fce609
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9163
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Now that the whole code is aligned with the coding style, enforce
the check through checkpatch.
Change-Id: Ie74ed98c5dfa61978d5551b60eb90acf746a3cc5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9057
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1274
From: Sriram Shanmuga <sriramharshalee@gmail.com>
RISC-V Debug Specification v1.0 [3.14.22. System Bus Access Control and
Status (`sbcs`, at 0x38)] states in `sbasize` field description:
> Width of system bus addresses in bits. (0 indicates there is no bus
access support.)
Before the patch, the error message did not include the information
about `sbcs.sbasize` being zero wich made it quite undescriptive:
```
[riscv.cpu] Turning off memory sampling because it failed.
```
Fixes#1270
Change-Id: I5402dd57dc9a81f65ee4c67d24e11c366006427c
Signed-off-by: Sriram Shanmuga <sriramharshalee@gmail.com>
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9142
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
If it fails, then pass that failure on. If it's simply not implemented,
then we can fall through and try target_get_gdb_reg_list_noread().
This difference matters when the target representing the current
hwthread is unavailable, but the target that is linked to the gdb
connection is available. In that case we want the operation to return an
error to gdb, instead of reading the register from the target that is
available.
Change-Id: I9c84ca556f818c5580e25ab349a34a226fcf0f43
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9138
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
'smp' and 'smp_gdb' command do not have 'riscv' prefix.
Document 'riscv use_bscan_tunnel' and 'riscv set_bscan_tunnel_ir'
as {Config Command}
Change-Id: I7b57613c9fedcccd6d6b1438d7fc2d28ea34ba65
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9133
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
