Commit Graph

3837 Commits

Author SHA1 Message Date
Antonio Borneo
8c41070415 target: riscv: fix double free() in parse_reg_ranges()
The buffer 'args' is allocated and freed in the caller function
parse_reg_ranges().
There is no reason to free it, only in some special case, in the
called function parse_reg_ranges_impl().
Scan build reports:
	src/target/riscv/riscv.c:4537:2: warning: Attempt to free
	released memory [unix.Malloc]

Drop the free() in the called function.

Change-Id: I2e308670c502f8e140603b4e5c16fc568088e1a8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9164
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:34:40 +00:00
Antonio Borneo
be083909b7 target: riscv: fix memory leak in riscv_openocd_step_impl()
The array 'wps_to_enable' is never freed.
Scan build reports:
	src/target/riscv/riscv.c:4271:6: warning: Potential leak
	of memory pointed to by 'wps_to_enable' [unix.Malloc]

Add the needed free().
While there, check if the allocation is successful.

Change-Id: I00e7ade37a43a97dcc245113ad93c48784fce609
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9163
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-11-12 20:34:21 +00:00
Tomas Vanek
18734bcf95 target/riscv: fix get mode filed for vsatp and hgatp
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1258
developed by Mark Zhuang <mark.zhuang@spacemit.com>

Add the necessary get_filed and add a comment to indicate
this section is for VU/VS mode

Change-Id: I898bba6250258c5076a98eb95411fcabccc52b96
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9144
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
2025-11-12 20:33:15 +00:00
Tomas Vanek
ffdbdf6b03 target/riscv: fix address translation in hypervisor mode
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1258
developed by zhefan.lv <zhefan.lv@spacemit.com>

address translation don't need to care hstatus.HU

Change-Id: I40a15ec17347dffaa6e663a637150dfb393471a0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9143
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2025-11-12 20:32:57 +00:00
Sriram Shanmuga
f5ce311103 target/riscv: improve error messaging in case sbasize is zero
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1274

From: Sriram Shanmuga <sriramharshalee@gmail.com>

RISC-V Debug Specification v1.0 [3.14.22. System Bus Access Control and
Status (`sbcs`, at 0x38)] states in `sbasize` field description:
> Width of system bus addresses in bits. (0 indicates there is no bus
access support.)

Before the patch, the error message did not include the information
about `sbcs.sbasize` being zero wich made it quite undescriptive:
```
[riscv.cpu] Turning off memory sampling because it failed.

```

Fixes #1270

Change-Id: I5402dd57dc9a81f65ee4c67d24e11c366006427c
Signed-off-by: Sriram Shanmuga <sriramharshalee@gmail.com>
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9142
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:32:33 +00:00
Tomas Vanek
3483756cba target/riscv: check nextdm address in abits range
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1257
developed by Mark Zhuang <mark.zhuang@spacemit.com>

When abits not correctly configured, we hope to detect it
as soon as possible.

Change-Id: I0b7b170c39761fb531dda0747f88ace3f39ae03b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9141
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
2025-11-12 20:32:10 +00:00
Tomas Vanek
ab8fb1d981 target/riscv: fix checking of number of parameters
in command 'riscv resume_order' to prevent segfault
on issuing the command without a parameter.

Change-Id: I5d7f4f92c2fa8e9effaba2c000d111e491b7b64f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9132
Tested-by: jenkins
2025-11-12 20:30:12 +00:00
Tomas Vanek
a0eac82708 target, flash: utility for riscv repeat_read command
Imported non-riscv part from
https://github.com/riscv-collab/riscv-openocd/pull/510
developed by Tim Newsome <tim@sifive.com>

Introduce target_handle_md_output() parameter include_address.
All callers set it true but riscv repeat_read command.

Change-Id: I67b5aad15a33ad149d4047998b22407cb60098fd
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9127
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2025-11-12 20:29:03 +00:00
Tomas Vanek
f354d259ff target/riscv: return ERROR_TARGET_NOT_HALTED
instead of ERROR_FAIL where appropriate.

Change-Id: I1881c0c6c437355007c3844556489162666023dc
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9171
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2025-11-12 20:27:27 +00:00
Tim Newsome
6127077613 target/breakpoints: better wording for error reason
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/767

Extracted small part of
target/riscv: Don't resume unavailable harts.

Change-Id: Id6617230cfdadf93ba402e60fb704bdfe7af5c1e
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8921
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:19:28 +00:00
Antonio Borneo
da96d3d41b target: riscv-011: don't change 'debug_level' during target polling
In the riscv fork, [1] has disable the debug log during target
polling, with message:
	Improve low-level logging.

	Now logging is consistent and more readable.
	I did remove most logging during riscv_poll() since it clutters
	up the log/screen and is not generally helpful.

This is questionable, because if the user enables the debug log,
the messages should all be logged.

Drop the code that overwrites the 'debug_level'.

Link: https://github.com/riscv-collab/riscv-openocd/commit/54c65a9a4b71 [1]
Change-Id: Ia86b998cf654760f36c2f217d44bcb9ffd9c3a94
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9072
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:18:36 +00:00
Antonio Borneo
768b4084eb target: riscv: don't test 'debug_level' directly
Use the macro 'LOG_LEVEL_IS()' to test 'debug_level'.

Change-Id: Ic931fd2eff0fa97a7a315b4b276f85dfc5fc8d5f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9071
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-11-12 20:17:21 +00:00
Antonio Borneo
bd303d6a3d target: riscv: align switch and case statements
The coding style requires the 'case' to be at the same indentation
level of its 'switch' statement.

Align the code accordingly.

While there, put at newline the command after the 'case'.

No changes are reported by
	git log -p -w --ignore-blank-lines --patience
apart from the newline after 'case'.

Change-Id: Id856e24100de6fb0442afe8bc51545b0138ef02d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9069
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:16:51 +00:00
Bernhard Rosenkränzer
56141bb349 target: riscv: Drop new typedefs added by the updated riscv-debug-spec files
The advantage of this patch is that it brings the new code closer to
OpenOCD coding style - the disadvantage is that it involves modifying
autogenerated files, making it harder to drop in new versions when
riscv-debug-spec changes.

Change-Id: I4c317e11ab1652333b0bb44168f953ef452d3ef5
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8896
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-11-12 20:16:13 +00:00
Bernhard Rosenkränzer
5754aebc49 target: riscv: Sync with the RISC-V fork
Regenerate autogenerated debug_defines.{c,h} files from current
riscv-debug-spec, sync remaining RISC-V target files with the
RISC-V fork.

This is based on the work of (in alphabetic order):

Aleksey Lotosh <lotosh@gmail.com>
Alexander Rumyantsev <cetygamer@gmail.com>
Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Bernhard Rosenkränzer <bero@baylibre.com>
bluew <bluewww@users.noreply.github.com>
Carsten Gosvig <40368726+cgsfv@users.noreply.github.com>
cgsfv <cgsfv@users.noreply.github.com>
Craig Blackmore <craig.blackmore@embecosm.com>
Dan Robertson <danlrobertson89@gmail.com>
Darius Rad <darius@bluespec.com>
dave-estes-syzexion <53795406+dave-estes-syzexion@users.noreply.github.com>
Dmitry Ryzhov <dmitry.ryzhov@cloudbear.ru>
Dolu1990 <charles.papon.90@gmail.com>
Emmanuel Blot <emmanuel.blot@free.fr>
Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>
Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Farid Khaydari <f.khaydari@syntacore.com>
Gleb Gagarin <gleb@sifive.com>
Greg Savin <43152568+SiFiveGregS@users.noreply.github.com>
Hang Xu <xuhang@eswincomputing.com>
Hsiangkai <Hsiangkai@gmail.com>
Jan Matyas <jan.matyas@codasip.com>
jhjung81 <48940114+jhjung81@users.noreply.github.com>
Jiuyang Liu <liu@jiuyang.me>
Kaspar Schleiser <kaspar@schleiser.de>
Khem Raj <raj.khem@gmail.com>
Kirill Radkin <kirill.radkin@syntacore.com>
liangzhen <zhen.liang@spacemit.com>
Liviu Ionescu <ilg@livius.net>
Marc Schink <openocd-dev@marcschink.de>
Megan Wachs <megan@sifive.com>
Nils Wistoff <git@wistoff.net>
Palmer Dabbelt <palmer@dabbelt.com>
panciyan <panciyan@eswincomputing.com>
Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Paul George <command.paul@gmail.com>
Pavel S. Smirnov <Paul.Smirnov.aka.sps@gmail.com>
Philipp Wagner <mail@philipp-wagner.com>
Ryan Macdonald <rmac@sifive.com>
Samuel Obuch <samuel.obuch17@gmail.com>
Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tim Newsome <tim@casualhacker.net>
Tobias Kaiser <mail@tb-kaiser.de>
Tom Hebb <tommyhebb@gmail.com>
Tommy Murphy <tommy_murphy@hotmail.com>
wxjstz <wxjstz@126.com>
wzgpeter <wzgpeter@outlook.com>
Xiang W <wxjstz@126.com>
zhusonghe <zhusonghe@eswincomputing.com>

Checkpatch-ignore MULTISTATEMENT_MACRO_USE_DO_WHILE is added to allow a
macro in riscv-013.c that can't use do/while because it expands to a
"case ...:" statement.

Checkpatch-ignore TRAILING_SEMICOLON is added to allow a construct in
riscv-013.c where a macro expands to either code (where it needs the
semicolon) or a member of an enum (where it needs a comma).

Checkpatch-ignore LONG_LINE_COMMENT and NEW_TYPEDEFS lines are added for
the sake of the autogenerated files from riscv-debug-spec.
All non-autogenerated files have been updated for checkpatch compliance.

Checkpatch-ignore: LONG_LINE_COMMENT
Checkpatch-ignore: NEW_TYPEDEFS
Checkpatch-ignore: MULTISTATEMENT_MACRO_USE_DO_WHILE
Checkpatch-ignore: TRAILING_SEMICOLON
Change-Id: Ie594915a4d6e6f9d9dad6016b176ab76409a099a
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8893
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:14:47 +00:00
Antonio Borneo
ab22b0bf8f target: cortex-m: don't query cache on hla targets
The cache handling code is written and optimized for dap queuing.
On hla targets it causes a segmentation fault due to uninitialized
AP pointer still set to NULL.

While it's possible to modify the code to cope with hla targets,
this would lower the OpenOCD performance on modern adapters.

Make cache handling not available on hla targets.

Reported-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Ief4499caedcee477b9517a7ad4597d06b5cb061e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 04da6e2c62 ("target: cortex-m: add support for armv8m caches")
Reviewed-on: https://review.openocd.org/c/openocd/+/9202
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-11-08 16:00:22 +00:00
Lucien Dufour
22afaae7fa Use C99 style for loop var
Use ARRAY_SIZE() to ensure ranges are correct.
Also, the C99 style is hopefully more readable.

Change-Id: I3d6bfbdc8e723791ba14d5a32e311c61bc2dfd77
Signed-off-by: Lucien Dufour <lucien.buchmann@dufour.aero>
Reviewed-on: https://review.openocd.org/c/openocd/+/9097
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
2025-11-02 13:50:21 +00:00
kryvosheiaivan
1ee0499cd8 armv8m: Add support for msplim/psplim for targets with no secext
When armv8m does not have security extension, it still has
msplim/psplim regs implemented, which is described in Cortex-M33
Devices Generic User Guide.
Document ID: 100235_0100_06_en, or at the link:
https://developer.arm.com/documentation/100235/latest/
Tested on cyw20829 along with gdb v14.2.1

Change-Id: I4f060e4df742c6773e79ce0481697361202d544c
Signed-off-by: kryvosheiaivan <Ivan.Kryvosheia@infineon.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8887
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-11-02 13:46:35 +00:00
Antonio Borneo
88b9bd396d target: cortex-m: fix support for armv8m caches
Scan-build is unable to correctly follow the deferred loading of
queued read, finalized by the atomic write, thus it incorrectly
claims that the arrays d_u_ccsidr[] and i_ccsidr[] could carry
not initialized values:

	armv7m_cache.c:154:31: warning: 1st function call argument
	is an uninitialized value [core.CallAndMessage]
	   cache->arch[cl].d_u_size = decode_ccsidr(d_u_ccsidr[cl]);

	armv7m_cache.c:172:29: warning: 1st function call argument
	is an uninitialized value [core.CallAndMessage]
	   cache->arch[cl].i_size = decode_ccsidr(i_ccsidr[cl]);

Initialize the arrays to zero to hide these false positive.

Change-Id: I6d1e88093cb8807848643139647a571c1b566aa8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 04da6e2c62 ("target: cortex-m: add support for armv8m caches")
Reviewed-on: https://review.openocd.org/c/openocd/+/9167
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-10-18 08:59:44 +00:00
Antonio Borneo
557a2082b1 openocd: don't test 'debug_level' directly
Use the macro 'LOG_LEVEL_IS()' to test 'debug_level'.

While there, use the macro 'LOG_LVL_*' in place of the numeric
value.

Skip all riscv code, as it is going to be updated soon from the
external fork.

Change-Id: Icad7e879e040d3b9cf1cc004c433f28725017493
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9070
Tested-by: jenkins
2025-10-18 08:37:13 +00:00
Antonio Borneo
8b43a967e5 target: cortex_m: add comment for breakpoint of length 3
Add a comment in the breakpoint code to clarify the check for the
odd breakpoint length of 3 bytes, introduced by [1].

[1]: commit 0a5e03c12a ("cortex_m.c: Use two byte breakpoint for
     32bit Thumb-2 request").

Change-Id: I024863d10078b5d9062c876aa59ccf70a81bf641
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9139
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-10-11 15:57:06 +00:00
Antonio Borneo
04da6e2c62 target: cortex-m: add support for armv8m caches
Cores like Cortex-M7, Cortex-M55 and Cortex-M85 can have either
D-Cache and/or I-Cache.
Using SW breakpoints in RAM requires handling these caches.

Detect the presence of cache at examine.
Detect cache state (enable/disable) at debug entry.
Take care of caches synchronization through the PoC (usually the
SRAM) while setting and removing SW breakpoints.
Add command 'cache_info' to check cache presence and size.

Change-Id: Ice637c215fe3042c8fff57edefbab1b86515ef4b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9077
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-10-11 15:56:41 +00:00
Marc Schink
2abf8daa80 target/cortex_m: Remove echo of 'reset_config' command
Do not echo the selected reset config. This is one of many changes to
make the behavior of Tcl commands more consistent.

This also avoids stray and confusing messages in the output of OpenOCD.
For example, the "reset_config" line here:

  Open On-Chip Debugger 0.12.0+dev-00802-gb7f0145fc-dirty
  Licensed under GNU GPL v2
  For bug reports, read
  	http://openocd.org/doc/doxygen/bugs.html
  cortex_m reset_config sysresetreq
  Info : Listening on port 6666 for tcl connections
  Info : Listening on port 4444 for telnet connections

While at it, fix some coding style and command handling issues.

Change-Id: I3b3d8687af1d23a2dc1764f29b52dc607b80cb59
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8638
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-10-11 15:51:37 +00:00
Samuel Obuch
e5888bda38 target/breakpoints: drop duplicate breakpoint/watchpoint "clear_target" functions
We need to cleanup watchpoints on all targets in SMP group when GDB
connects. Otherwise, the targets will not be consistent.
Once thats fixed, both *_clear_target functions clearly duplicate
the corresponding *_remove_all functions.

Change-Id: I8e85dbc66fd3e596990d631ed2aed22959a8ca60
Signed-off-by: Samuel Obuch <samuel.obuch@espressif.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9086
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-09-30 07:22:37 +00:00
Antonio Borneo
27ab12dd82 target: extend registers match on 'get_reg' and 'set_reg'
Some target, like aarch64, has more than one bank of registers.

Let the commands 'get_reg' and 'set_reg' to search the register
name in all banks, as is already done in command 'reg'.

Change-Id: Iae350a52f993790c5546925a2f7f81fbdb3f49b8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: e8e62c5aca ("target/tcl: Add get_reg function")
Fixes: da73280101 ("target/tcl: Add set_reg function")
Reviewed-on: https://review.openocd.org/c/openocd/+/9122
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
2025-09-27 14:53:26 +00:00
Marc Schink
9279a489d4 target/stm8: Remove useless parentheses
Parentheses are not necessary here, remove them.

Change-Id: I793639fbef38688045104d351fb4e5320f1eba2a
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9058
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-09-06 11:41:51 +00:00
Antonio Borneo
ddef9cf73b target: align switch and case statements
The coding style requires the 'case' to be at the same indentation
level of its 'switch' statement.

Align the code accordingly.

While there:
- add space around the operators;
- drop useless empty line.

Skip all riscv code, as it is going to be updated soon from the
external fork.

No changes are reported by
	git log -p -w --ignore-blank-lines --patience

Change-Id: I2691dfdd2b6734143e14160b46183623e9773539
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9051
Tested-by: jenkins
2025-09-06 11:41:33 +00:00
Antonio Borneo
e9561c4af5 target: prepare for aligning switch and case statements
To prepare for aligning switch and case statements, fix in advance
some checkpatch error due to existing code:
- remove useless parenthesis;
- remove useless 'break';
- join spit lines;
- add space around operators;
- remove 'else' after exit() and return.

Change-Id: I8a87a0ea104205d087dcb8cbf4c67ff13a47742f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9050
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
2025-09-06 08:33:52 +00:00
Antonio Borneo
6b7cc918f0 target: cortex_a: add break in switch/case
The code falls-through in the default case, making it not easy to
read.

Add the explicit break to improve the readability.

Change-Id: I4784b883e0e82258de17018dfdfb59b4042ac743
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9049
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-09-06 08:33:38 +00:00
Richard Allen
1950befd76 target/espressif: add profiling function for ESP32, ESP32-S2
Use the TRAX interface DEBUGPC if available.
Otherwise use default stop-and-go profiling.

ESP32: FT2232H+Linux: 97ksample/second @ 20mbps JTAG

Change-Id: I1dda43df2727b542b08e338f7f4ba63530844a4f
Signed-off-by: Richard Allen <rsaxvc@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8910
Reviewed-by: Samuel Obuch <samuel.obuch@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-08-17 13:32:59 +00:00
Antonio Borneo
8b4eb936db target: allow events to be modified inside an event handler
The code in an event handler can use the command '$target_name
configure' to add a new event or to remove or modify an existing
event.
Such operation impacts the list of event of the target and also
modify the event itself, causing OpenOCD to access memory already
deallocated or not anymore valid.

Use the safe version of list_for_each_entry() to iterate on the
list of events.
Make a local copy of the current event, to avoid issues if it gets
deallocated.
Use Jim_IncrRefCount() to guarantee that the body of the event
handler don't gets deallocated when the event is removed.

Change-Id: I936e35adddc030ba7cec6e2fc0c7d3b1b5c4a863
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9063
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
2025-08-17 13:32:19 +00:00
Antonio Borneo
003cb92cd5 openocd: drop empty string suffix from format strings
Format strings are often split to allow using the conversion
specifiers macros from <inttypes.h>.
When the format string ends with one of such macros, there is no
need to add an empty string "" after the macro.

In current code we have 203 cases of empty string present, against
1159 cases of string ending with the macro.

Uniform the style across OpenOCD by removing the empty string.

Don't modify the files 'angie.c' and 'max32xxx.c' as they are
already changed by other independent commits.

Change-Id: I23f1120101ce1da67c6578635fc6507a58c803e9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9065
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-08-09 15:04:46 +00:00
Antonio Borneo
9fe3780432 openocd: drop iteration downsampling for keep_alive()
The function keep_alive() is optimized and return immediately if
has nothing to do.
There is no need to overly-complicate the code with extra counters
or time computation plus the relative checks to reduce the number
of calls to keep_alive().

Drop such extra code.

Change-Id: I4574a3f154b5779f44105936c74af8fca1d2c49c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9064
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Lucien Buchmann <lucien.buchmann@dufour.aero>
2025-08-09 15:04:34 +00:00
Samuel Obuch
d3c25a45f6 target/xtensa: fix unaligned memory read on retry
When we read unaligned memory there is an offset in the albuff buffer,
that we account for when copying back to original buffer. But in case
the first access failed, the retry call already removed the offset,
so doing it a second time shifts the returned memory.

Change-Id: Ie255c367ca6a001bfe7038a76cf8a6443e398c51
Signed-off-by: Samuel Obuch <samuel.obuch@espressif.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8987
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-08-09 15:00:50 +00:00
Marc Schink
c8e6746e9f rtt: Consider target endianness
Consider target endianness when reading control block and channel
information. Current implementation fails on big-endian devices.

Tested on TMS570 (big-endian) and on nRF52 (little-endian).

Note that in its current implementation RTT does not work properly on
TMS570 due to its missing support for background memory access.

Change-Id: Iab58804c42c85a932a750201a69ded35cebedd5d
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8993
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-08-02 12:59:33 +00:00
Marc Schink
1272796cc5 target/armv8: Use 'bool' data type for cache validity flag
The variable is already used as boolean value but has the wrong data
type.

Change-Id: Ia54cfbcdad00dc15e1181c05fb97fcbaa435bb21
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9059
Tested-by: jenkins
Reviewed-by: Richard Allen <rsaxvc@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-08-02 12:57:05 +00:00
Marc Schink
b4d05b6e72 target/arvm7a: Use 'bool' data type where appropriate
The variables are already used as boolean value but have the wrong
data type.

Change-Id: I0f169cac83f6c4094e8d1acb2cb8f1017a96a5d8
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9008
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-08-02 12:56:53 +00:00
Marc Schink
c2b8f994bf target: Make use of str_enabled_disabled()
The data type changes introduced in [1,2] lead to implicit casts from a
boolean to an integer value in the string selection between "enabled" and
"disabled".

Use str_enabled_disabled() to get rid of this implicit cast.

[1] https://review.openocd.org/c/openocd/+/8988
[2] https://review.openocd.org/c/openocd/+/8992

Change-Id: Ia98abdd43b42f394f5bf0aa845017dfbb0e087fd
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9007
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-08-02 12:56:32 +00:00
Marc Schink
bd32290864 target: Use 'bool' data type for {i,d_u}_cache_enabled
The variables are already used as boolean value but have the wrong
data type.

Change-Id: Ia4c63d04fdd61bfd48e353fde9984b0e6cefbd8b
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8992
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-08-02 12:56:14 +00:00
Marc Schink
218ea2658a target/cortex_a: Use 'bool' data type in cortex_a_mmu_modify()
The variables are already used as boolean value but have the wrong
data type.

Change-Id: Ia1660751063993fcf46c86246e93a75089629ab5
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8991
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-08-02 12:56:01 +00:00
Marc Schink
d20878b776 target/cortex_a: Use 'bool' data type for cortex_a_*_memaccess()
Use 'bool' because it is the appropriate data type.

Change-Id: I543b153fe5f6af4d20988b95eb17f2357e706a76
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8990
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-08-02 12:55:43 +00:00
Marc Schink
325e6d38b5 target: Use 'bool' data type in mmu()
The variable is already used in some parts of the code as boolean value
but have the wrong data type.

Change-Id: I50ccbf84c6f33a3034de989789c6b17312458ea8
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8989
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-08-02 12:55:31 +00:00
Marc Schink
a66e6fb43f target: Use 'bool' data type for 'mmu_enabled'
The variables are already used in some parts of the code as boolean
value but have the wrong data type.

Change-Id: I2c4955a6ed463fabf63a1dbd79145cb63bc7a99c
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8988
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-08-02 12:55:14 +00:00
Tomas Vanek
09a54c3a89 target/arm_adi: add URLs of latest ARM ADI spec
While on it warn about screwed SWD diagrams in ADI spec
and add reference to a SWD timing diagram.

Change-Id: I628d707ebf8ce7c22ba19bdcfd06028d4eaa60f8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8690
Tested-by: jenkins
2025-07-02 12:20:36 +00:00
Tomas Vanek
f547e55076 target/cortex_m: introduce security manipulation routines
Running target algorithms on ARMv8M may require core in secure
mode with SAU and MPU off (as set after reset).

cortex_m_set_secure() forces this mode with optional save of
the previous state.

cortex_m_security_restore() restores previously saved state.

Change-Id: Ia71826db47ee7b0557eaffd55244ce13eacbcb4b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8959
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-06-29 07:41:04 +00:00
Marc Schink
c6f1863352 target/armv4: Use command_print() instead of LOG_ERROR()
Use command_print() in order to provide an error message to the caller.

Change-Id: I9f1a2ef07a102e1d6e755f3680bed0f7183b5c9c
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8968
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-06-29 07:35:35 +00:00
Marc Schink
56c24b9eb2 target/armv4: Use LOG_TARGET_xxx()
Use LOG_TARGET_xxx() for log messages as it is used for other targets.

While at it, rework the log messages. For example by removing spaces or
punctuation marks at the end of the message.

Change-Id: I295001876d40527ec8f35c2aec8d562a29e57b26
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8967
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-06-29 07:35:23 +00:00
Marc Schink
7fa8a5c257 target/armv7a: Use LOG_TARGET_xxx()
Use LOG_TARGET_xxx() to indicate which target the message belongs to.

Change-Id: Ic40c61a779c1a1ebdc96ebc56b27541fff5e6205
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8966
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-06-29 07:35:12 +00:00
Marc Schink
d008a02a74 target/armv7a: Hide multiprocessing support message
Print a debug message about missing multiprocessing support rather than
an error message.

Change-Id: Ia1581f7284747d8a92096d6f5515f891c8069f71
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8965
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-06-29 07:35:01 +00:00
Marc Schink
4d56d580ce target/arm_dpm: Use LOG_TARGET_xxx()
Use LOG_TARGET_xxx() to indicate which target the message belongs to.

While at it, rework the log messages. For example, using correct format
specifiers.

Change-Id: I05031e0ae25fe9e7bc38dfb781b6623a967fd533
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8964
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-06-29 07:34:48 +00:00