The openocd-0.12.0 release

Signed-off-by: Paul Fertser <fercerpav@gmail.com>

NEWS

@@ -111,7 +111,7 @@ Build and Release:
 	* Drop repository repo.or.cz for submodules
 	* Move gerrit to https://review.openocd.org/
 	* Require autoconf 2.69 or newer
-	* Update jep106 to revision JEP106BE
+	* Update jep106 to revision JEP106BF.01
 	* Update jimtcl to version 0.81
 	* Update libjaylink to version 0.3.1
 	* New configure flag '--enable-jimtcl-maintainer' for jimtcl build
@@ -121,7 +121,7 @@ This release also contains a number of other important functional and
 cosmetic bugfixes. For more details about what has changed since the
 last release, see the git repository history:
 
-http://sourceforge.net/p/openocd/code/ci/v0.12.0-rc2/log/?path=
+http://sourceforge.net/p/openocd/code/ci/v0.12.0/log/?path=
 
 
 For older NEWS, see the NEWS files associated with each release

configure.ac

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 AC_PREREQ([2.69])
-AC_INIT([openocd], [0.12.0-rc2],
+AC_INIT([openocd], [0.12.0],
   [OpenOCD Mailing List <openocd-devel@lists.sourceforge.net>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 AC_CONFIG_AUX_DIR([build-aux])
@@ -574,7 +574,7 @@ AS_IF([test "x$enable_buspirate" != "xno"], [
 ])
 
 AS_IF([test "x$use_internal_jimtcl" = "xyes"], [
-  AS_IF([test -f "$srcdir/jimtcl/configure.ac"], [
+  AS_IF([test -f "$srcdir/jimtcl/configure"], [
     AS_IF([test "x$use_internal_jimtcl_maintainer" = "xyes"], [
       jimtcl_config_options="--disable-install-jim --with-ext=json --maintainer"
     ], [

doc/openocd.texi

@@ -8478,12 +8478,20 @@ that particular type of PLD.
 
 @deffn {FPGA Driver} {virtex2} [no_jstart]
 Virtex-II is a family of FPGAs sold by Xilinx.
+This driver can also be used to load Series3, Series6, Series7 and Zynq 7000 devices.
 It supports the IEEE 1532 standard for In-System Configuration (ISC).
 
 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
 loading the bitstream. While required for Series2, Series3, and Series6, it
 breaks bitstream loading on Series7.
 
+@example
+openocd -f board/digilent_zedboard.cfg -c "init" \
+	-c "pld load 0 zedboard_bitstream.bit"
+@end example
+
+
+
 @deffn {Command} {virtex2 read_stat} num
 Reads and displays the Virtex-II status register (STAT)
 for FPGA @var{num}.
@@ -8515,7 +8523,7 @@ command. All output is relayed through the GDB session.
 
 @item @b{Machine Interface}
 The Tcl interface's intent is to be a machine interface. The default Tcl
-port is 5555.
+port is 6666.
 @end itemize
 
 

src/flash/nor/at91samd.c

@@ -12,6 +12,7 @@
 #include "imp.h"
 #include "helper/binarybuffer.h"
 
+#include <helper/time_support.h>
 #include <jtag/jtag.h>
 #include <target/cortex_m.h>
 
@@ -31,7 +32,7 @@
 #define SAMD_NVMCTRL_CTRLA		0x00	/* NVM control A register */
 #define SAMD_NVMCTRL_CTRLB		0x04	/* NVM control B register */
 #define SAMD_NVMCTRL_PARAM		0x08	/* NVM parameters register */
-#define SAMD_NVMCTRL_INTFLAG	0x18	/* NVM Interrupt Flag Status & Clear */
+#define SAMD_NVMCTRL_INTFLAG	0x14	/* NVM Interrupt Flag Status & Clear */
 #define SAMD_NVMCTRL_STATUS		0x18	/* NVM status register */
 #define SAMD_NVMCTRL_ADDR		0x1C	/* NVM address register */
 #define SAMD_NVMCTRL_LOCK		0x20	/* NVM Lock section register */
@@ -55,6 +56,9 @@
 /* NVMCTRL bits */
 #define SAMD_NVM_CTRLB_MANW 0x80
 
+/* NVMCTRL_INTFLAG bits */
+#define SAMD_NVM_INTFLAG_READY 0x01
+
 /* Known identifiers */
 #define SAMD_PROCESSOR_M0	0x01
 #define SAMD_FAMILY_D		0x00
@@ -497,7 +501,27 @@ static int samd_probe(struct flash_bank *bank)
 static int samd_check_error(struct target *target)
 {
 	int ret, ret2;
+	uint8_t intflag;
 	uint16_t status;
+	int timeout_ms = 1000;
+	int64_t ts_start = timeval_ms();
+
+	do {
+		ret = target_read_u8(target,
+			SAMD_NVMCTRL + SAMD_NVMCTRL_INTFLAG, &intflag);
+		if (ret != ERROR_OK) {
+			LOG_ERROR("Can't read NVM intflag");
+			return ret;
+		}
+		if (intflag & SAMD_NVM_INTFLAG_READY)
+			break;
+		keep_alive();
+	} while (timeval_ms() - ts_start < timeout_ms);
+
+	if (!(intflag & SAMD_NVM_INTFLAG_READY)) {
+		LOG_ERROR("SAMD: NVM programming timed out");
+		return ERROR_FLASH_OPERATION_FAILED;
+	}
 
 	ret = target_read_u16(target,
 			SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);

src/flash/nor/lpc2900.c

@@ -1132,9 +1132,9 @@ static int lpc2900_write(struct flash_bank *bank, const uint8_t *buffer,
 	 * reduced size if that fails. */
 	struct working_area *warea;
 	uint32_t buffer_size = lpc2900_info->max_ram_block - 1 * KiB;
-	while ((retval = target_alloc_working_area_try(target,
+	while (target_alloc_working_area_try(target,
 				 buffer_size + target_code_size,
-				 &warea)) != ERROR_OK) {
+				 &warea) != ERROR_OK) {
 		/* Try a smaller buffer now, and stop if it's too small. */
 		buffer_size -= 1 * KiB;
 		if (buffer_size < 2 * KiB) {

src/flash/nor/stm32f1x.c

@@ -473,7 +473,7 @@ static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buff
 
 	/* memory buffer */
 	buffer_size = target_get_working_area_avail(target);
-	buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256));
+	buffer_size = MIN(hwords_count * 2 + 8, MAX(buffer_size, 256));
 	/* Normally we allocate all available working area.
 	 * MIN shrinks buffer_size if the size of the written block is smaller.
 	 * MAX prevents using async algo if the available working area is smaller

src/flash/nor/stm32lx.c

@@ -132,7 +132,7 @@ static const struct stm32lx_rev stm32_417_revs[] = {
 	{ 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" }, { 0x1038, "X" }
 };
 static const struct stm32lx_rev stm32_425_revs[] = {
-	{ 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Y" },
+	{ 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Y" }, { 0x2018, "1, X" },
 };
 static const struct stm32lx_rev stm32_427_revs[] = {
 	{ 0x1000, "A" }, { 0x1018, "Y" }, { 0x1038, "X" }, { 0x10f8, "V" },

src/flash/nor/stmqspi.c

@@ -616,8 +616,6 @@ COMMAND_HANDLER(stmqspi_handle_set)
 
 	LOG_DEBUG("%s", __func__);
 
-	dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
-
 	/* chip_erase_cmd, sectorsize and erase_cmd are optional */
 	if ((CMD_ARGC < 7) || (CMD_ARGC > 10))
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -628,8 +626,9 @@ COMMAND_HANDLER(stmqspi_handle_set)
 
 	target = bank->target;
 	stmqspi_info = bank->driver_priv;
+	dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
 
-	/* invalidate all old info */
+	/* invalidate all flash device info */
 	if (stmqspi_info->probed)
 		free(bank->sectors);
 	bank->size = 0;
@@ -721,10 +720,8 @@ COMMAND_HANDLER(stmqspi_handle_set)
 
 	uint32_t dcr;
 	retval = target_read_u32(target, io_base + SPI_DCR, &dcr);
-
 	if (retval != ERROR_OK)
 		return retval;
-
 	fsize = (dcr >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
 
 	LOG_DEBUG("FSIZE = 0x%04x", fsize);
@@ -1799,7 +1796,6 @@ static int find_sfdp_dummy(struct flash_bank *bank, int len)
 		}
 	}
 
-	retval = ERROR_FAIL;
 	LOG_DEBUG("no start of SFDP header even after %u dummy bytes", count);
 
 err:
@@ -2081,16 +2077,17 @@ static int stmqspi_probe(struct flash_bank *bank)
 	bool octal_dtr;
 	int retval;
 
-	if (stmqspi_info->probed) {
-		bank->size = 0;
-		bank->num_sectors = 0;
+	/* invalidate all flash device info */
+	if (stmqspi_info->probed)
 		free(bank->sectors);
-		bank->sectors = NULL;
-		memset(&stmqspi_info->dev, 0, sizeof(stmqspi_info->dev));
-		stmqspi_info->sfdp_dummy1 = 0;
-		stmqspi_info->sfdp_dummy2 = 0;
-		stmqspi_info->probed = false;
-	}
+	bank->size = 0;
+	bank->num_sectors = 0;
+	bank->sectors = NULL;
+	stmqspi_info->sfdp_dummy1 = 0;
+	stmqspi_info->sfdp_dummy2 = 0;
+	stmqspi_info->probed = false;
+	memset(&stmqspi_info->dev, 0, sizeof(stmqspi_info->dev));
+	stmqspi_info->dev.name = "unknown";
 
 	/* Abort any previous operation */
 	retval = stmqspi_abort(bank);
@@ -2105,8 +2102,8 @@ static int stmqspi_probe(struct flash_bank *bank)
 	/* check whether QSPI_ABR is writeable and readback returns the value written */
 	retval = target_write_u32(target, io_base + QSPI_ABR, magic);
 	if (retval == ERROR_OK) {
-		retval = target_read_u32(target, io_base + QSPI_ABR, &data);
-		retval = target_write_u32(target, io_base + QSPI_ABR, 0);
+		(void)target_read_u32(target, io_base + QSPI_ABR, &data);
+		(void)target_write_u32(target, io_base + QSPI_ABR, 0);
 	}
 
 	if (data == magic) {

src/helper/jep106.inc

@@ -8,7 +8,7 @@
  * identification code list, please visit the JEDEC website at www.jedec.org .
  */
 
-/* This file is aligned to revision JEP106BE January 2022. */
+/* This file is aligned to revision JEP106BF.01 October 2022. */
 
 [0][0x01 - 1] = "AMD",
 [0][0x02 - 1] = "AMI",
@@ -149,7 +149,7 @@
 [1][0x0b - 1] = "Bestlink Systems",
 [1][0x0c - 1] = "Graychip",
 [1][0x0d - 1] = "GENNUM",
-[1][0x0e - 1] = "VideoLogic",
+[1][0x0e - 1] = "Imagination Technologies Limited",
 [1][0x0f - 1] = "Robert Bosch",
 [1][0x10 - 1] = "Chip Express",
 [1][0x11 - 1] = "DATARAM",
@@ -1501,7 +1501,7 @@
 [11][0x67 - 1] = "Guangzhou Shuvrwine Technology Co",
 [11][0x68 - 1] = "Shenzhen Hangshun Chip Technology",
 [11][0x69 - 1] = "Chengboliwei Electronic Business",
-[11][0x6a - 1] = "Kowin Memory Technology Co Ltd",
+[11][0x6a - 1] = "Kowin Technology HK Limited",
 [11][0x6b - 1] = "Euronet Technology Inc",
 [11][0x6c - 1] = "SCY",
 [11][0x6d - 1] = "Shenzhen Xinhongyusheng Electrical",
@@ -1705,4 +1705,85 @@
 [13][0x37 - 1] = "ORICO Technologies Co. Ltd.",
 [13][0x38 - 1] = "Space Exploration Technologies Corp",
 [13][0x39 - 1] = "AONDEVICES Inc",
+[13][0x3a - 1] = "Shenzhen Netforward Micro Electronic",
+[13][0x3b - 1] = "Syntacore Ltd",
+[13][0x3c - 1] = "Shenzhen Secmem Microelectronics Co",
+[13][0x3d - 1] = "ONiO As",
+[13][0x3e - 1] = "Shenzhen Peladn Technology Co Ltd",
+[13][0x3f - 1] = "O-Cubes Shanghai Microelectronics",
+[13][0x40 - 1] = "ASTC",
+[13][0x41 - 1] = "UMIS",
+[13][0x42 - 1] = "Paradromics",
+[13][0x43 - 1] = "Sinh Micro Co Ltd",
+[13][0x44 - 1] = "Metorage Semiconductor Technology Co",
+[13][0x45 - 1] = "Aeva Inc",
+[13][0x46 - 1] = "HongKong Hyunion Electronics Co Ltd",
+[13][0x47 - 1] = "China Flash Co Ltd",
+[13][0x48 - 1] = "Sunplus Technology Co Ltd",
+[13][0x49 - 1] = "Idaho Scientific",
+[13][0x4a - 1] = "Suzhou SF Micro Electronics Co Ltd",
+[13][0x4b - 1] = "IMEX Cap AG",
+[13][0x4c - 1] = "Fitipower Integrated Technology Co Ltd",
+[13][0x4d - 1] = "ShenzhenWooacme Technology Co Ltd",
+[13][0x4e - 1] = "KeepData Original Chips",
+[13][0x4f - 1] = "Rivos Inc",
+[13][0x50 - 1] = "Big Innovation Company Limited",
+[13][0x51 - 1] = "Wuhan YuXin Semiconductor Co Ltd",
+[13][0x52 - 1] = "United Memory Technology (Jiangsu)",
+[13][0x53 - 1] = "PQShield Ltd",
+[13][0x54 - 1] = "ArchiTek Corporation",
+[13][0x55 - 1] = "ShenZhen AZW Technology Co Ltd",
+[13][0x56 - 1] = "Hengchi Zhixin (Dongguan) Technology",
+[13][0x57 - 1] = "Eggtronic Engineering Spa",
+[13][0x58 - 1] = "Fusontai Technology",
+[13][0x59 - 1] = "PULP Platform",
+[13][0x5a - 1] = "Koitek Electronic Technology (Shenzhen) Co",
+[13][0x5b - 1] = "Shenzhen Jiteng Network Technology Co",
+[13][0x5c - 1] = "Aviva Links Inc",
+[13][0x5d - 1] = "Trilinear Technologies Inc",
+[13][0x5e - 1] = "Shenzhen Developer Microelectronics Co",
+[13][0x5f - 1] = "Guangdong OPPO Mobile Telecommunication",
+[13][0x60 - 1] = "Akeana",
+[13][0x61 - 1] = "Lyczar",
+[13][0x62 - 1] = "Shenzhen Qiji Technology Co Ltd",
+[13][0x63 - 1] = "Shenzhen Shangzhaoyuan Technology",
+[13][0x64 - 1] = "Han Stor",
+[13][0x65 - 1] = "China Micro Semicon Co., Ltd.",
+[13][0x66 - 1] = "Shenzhen Zhuqin Technology Co Ltd",
+[13][0x67 - 1] = "Shanghai Ningyuan Electronic Technology",
+[13][0x68 - 1] = "Auradine",
+[13][0x69 - 1] = "Suzhou Yishuo Electronics Co Ltd",
+[13][0x6a - 1] = "Faurecia Clarion Electronics",
+[13][0x6b - 1] = "SiMa Technologies",
+[13][0x6c - 1] = "CFD Sales Inc",
+[13][0x6d - 1] = "Suzhou Comay Information Co Ltd",
+[13][0x6e - 1] = "Yentek",
+[13][0x6f - 1] = "Qorvo Inc",
+[13][0x70 - 1] = "Shenzhen Youzhi Computer Technology",
+[13][0x71 - 1] = "Sychw Technology (Shenzhen) Co Ltd",
+[13][0x72 - 1] = "MK Founder Technology Co Ltd",
+[13][0x73 - 1] = "Siliconwaves Technologies Co Ltd",
+[13][0x74 - 1] = "Hongkong Hyunion Electronics Co Ltd",
+[13][0x75 - 1] = "Shenzhen Xinxinzhitao Electronics Business",
+[13][0x76 - 1] = "Shenzhen HenQi Electronic Commerce Co",
+[13][0x77 - 1] = "Shenzhen Jingyi Technology Co Ltd",
+[13][0x78 - 1] = "Xiaohua Semiconductor Co. Ltd.",
+[13][0x79 - 1] = "Shenzhen Dalu Semiconductor Technology",
+[13][0x7a - 1] = "Shenzhen Ninespeed Electronics Co Ltd",
+[13][0x7b - 1] = "ICYC Semiconductor Co Ltd",
+[13][0x7c - 1] = "Shenzhen Jaguar Microsystems Co Ltd",
+[13][0x7d - 1] = "Beijing EC-Founder Co Ltd",
+[13][0x7e - 1] = "Shenzhen Taike Industrial Automation Co",
+[14][0x01 - 1] = "Kalray SA",
+[14][0x02 - 1] = "Shanghai Iluvatar CoreX Semiconductor Co",
+[14][0x03 - 1] = "Fungible Inc",
+[14][0x04 - 1] = "Song Industria E Comercio de Eletronicos",
+[14][0x05 - 1] = "DreamBig Semiconductor Inc",
+[14][0x06 - 1] = "ChampTek Electronics Corp",
+[14][0x07 - 1] = "Fusontai Technology",
+[14][0x08 - 1] = "Endress Hauser AG",
+[14][0x09 - 1] = "altec ComputerSysteme GmbH",
+[14][0x0a - 1] = "UltraRISC Technology (Shanghai) Co Ltd",
+[14][0x0b - 1] = "Shenzhen Jing Da Kang Technology Co Ltd",
+[14][0x0c - 1] = "Hangzhou Hongjun Microelectronics Co Ltd",
 /* EOF */

src/helper/types.h

@@ -151,7 +151,7 @@ static inline uint16_t be_to_h_u16(const uint8_t *buf)
 	return (uint16_t)((uint16_t)buf[1] | (uint16_t)buf[0] << 8);
 }
 
-static inline void h_u64_to_le(uint8_t *buf, int64_t val)
+static inline void h_u64_to_le(uint8_t *buf, uint64_t val)
 {
 	buf[7] = (uint8_t) (val >> 56);
 	buf[6] = (uint8_t) (val >> 48);
@@ -163,7 +163,7 @@ static inline void h_u64_to_le(uint8_t *buf, int64_t val)
 	buf[0] = (uint8_t) (val >> 0);
 }
 
-static inline void h_u64_to_be(uint8_t *buf, int64_t val)
+static inline void h_u64_to_be(uint8_t *buf, uint64_t val)
 {
 	buf[0] = (uint8_t) (val >> 56);
 	buf[1] = (uint8_t) (val >> 48);
@@ -175,7 +175,7 @@ static inline void h_u64_to_be(uint8_t *buf, int64_t val)
 	buf[7] = (uint8_t) (val >> 0);
 }
 
-static inline void h_u32_to_le(uint8_t *buf, int val)
+static inline void h_u32_to_le(uint8_t *buf, uint32_t val)
 {
 	buf[3] = (uint8_t) (val >> 24);
 	buf[2] = (uint8_t) (val >> 16);
@@ -183,7 +183,7 @@ static inline void h_u32_to_le(uint8_t *buf, int val)
 	buf[0] = (uint8_t) (val >> 0);
 }
 
-static inline void h_u32_to_be(uint8_t *buf, int val)
+static inline void h_u32_to_be(uint8_t *buf, uint32_t val)
 {
 	buf[0] = (uint8_t) (val >> 24);
 	buf[1] = (uint8_t) (val >> 16);
@@ -191,27 +191,27 @@ static inline void h_u32_to_be(uint8_t *buf, int val)
 	buf[3] = (uint8_t) (val >> 0);
 }
 
-static inline void h_u24_to_le(uint8_t *buf, int val)
+static inline void h_u24_to_le(uint8_t *buf, unsigned int val)
 {
 	buf[2] = (uint8_t) (val >> 16);
 	buf[1] = (uint8_t) (val >> 8);
 	buf[0] = (uint8_t) (val >> 0);
 }
 
-static inline void h_u24_to_be(uint8_t *buf, int val)
+static inline void h_u24_to_be(uint8_t *buf, unsigned int val)
 {
 	buf[0] = (uint8_t) (val >> 16);
 	buf[1] = (uint8_t) (val >> 8);
 	buf[2] = (uint8_t) (val >> 0);
 }
 
-static inline void h_u16_to_le(uint8_t *buf, int val)
+static inline void h_u16_to_le(uint8_t *buf, uint16_t val)
 {
 	buf[1] = (uint8_t) (val >> 8);
 	buf[0] = (uint8_t) (val >> 0);
 }
 
-static inline void h_u16_to_be(uint8_t *buf, int val)
+static inline void h_u16_to_be(uint8_t *buf, uint16_t val)
 {
 	buf[0] = (uint8_t) (val >> 8);
 	buf[1] = (uint8_t) (val >> 0);

src/jtag/drivers/arm-jtag-ew.c

@@ -776,17 +776,12 @@ static int armjtagew_usb_read(struct armjtagew *armjtagew, int exp_in_length)
 
 static void armjtagew_debug_buffer(uint8_t *buffer, int length)
 {
-	char line[81];
-	char s[4];
-	int i;
-	int j;
+	char line[8 + 3 * BYTES_PER_LINE + 1];
 
-	for (i = 0; i < length; i += BYTES_PER_LINE) {
-		snprintf(line, 5, "%04x", i);
-		for (j = i; j < i + BYTES_PER_LINE && j < length; j++) {
-			snprintf(s, 4, " %02x", buffer[j]);
-			strcat(line, s);
-		}
+	for (int i = 0; i < length; i += BYTES_PER_LINE) {
+		int n = snprintf(line, 9, "%04x", i);
+		for (int j = i; j < i + BYTES_PER_LINE && j < length; j++)
+			n += snprintf(line + n, 4, " %02x", buffer[j]);
 		LOG_DEBUG("%s", line);
 
 		/* Prevent GDB timeout (writing to log might take some time) */

src/jtag/drivers/cmsis_dap.c

@@ -660,7 +660,7 @@ static int cmsis_dap_cmd_dap_swo_baudrate(
 	command[0] = CMD_DAP_SWO_BAUDRATE;
 	h_u32_to_le(&command[1], in_baudrate);
 
-	int retval = cmsis_dap_xfer(cmsis_dap_handle, 4);
+	int retval = cmsis_dap_xfer(cmsis_dap_handle, 5);
 	uint32_t rvbr = le_to_h_u32(&cmsis_dap_handle->response[1]);
 	if (retval != ERROR_OK || rvbr == 0) {
 		LOG_ERROR("CMSIS-DAP: command CMD_SWO_Baudrate(%u) -> %u failed.", in_baudrate, rvbr);

src/jtag/drivers/cmsis_dap_usb_bulk.c

@@ -262,8 +262,10 @@ static int cmsis_dap_usb_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p
 					/* If the interface is reliably identified
 					 * then we need not insist on setting USB class, subclass and protocol
 					 * exactly as the specification requires.
+					 * Just filter out the well known classes, mainly CDC and MSC.
 					 * At least KitProg3 uses class 0 contrary to the specification */
-					if (intf_identified_reliably) {
+					if (intf_identified_reliably &&
+							(intf_desc->bInterfaceClass == 0 || intf_desc->bInterfaceClass > 0x12)) {
 						LOG_WARNING("Using CMSIS-DAPv2 interface %d with wrong class %" PRId8
 								  " subclass %" PRId8 " or protocol %" PRId8,
 								  interface_num,

src/jtag/drivers/esp_usb_jtag.c

@@ -16,8 +16,6 @@
 #include "bitq.h"
 #include "libusb_helper.h"
 
-#define __packed __attribute__((packed))
-
 /*
 Holy Crap, it's protocol documentation, and it's even vendor-provided!
 
@@ -110,7 +108,7 @@ descriptor.
 struct jtag_proto_caps_hdr {
 	uint8_t proto_ver;	/* Protocol version. Expects JTAG_PROTO_CAPS_VER for now. */
 	uint8_t length;	/* of this plus any following descriptors */
-} __packed;
+} __attribute__((packed));
 
 /* start of the descriptor headers */
 #define JTAG_BUILTIN_DESCR_START_OFF            0	/* Devices with builtin usb jtag */
@@ -133,7 +131,7 @@ of caps header to assume this. If no such caps exist, assume a minimum (in) buff
 struct jtag_gen_hdr {
 	uint8_t type;
 	uint8_t length;
-} __packed;
+} __attribute__((packed));
 
 struct jtag_proto_caps_speed_apb {
 	uint8_t type;					/* Type, always JTAG_PROTO_CAPS_SPEED_APB_TYPE */
@@ -141,7 +139,7 @@ struct jtag_proto_caps_speed_apb {
 	uint8_t apb_speed_10khz[2];		/* ABP bus speed, in 10KHz increments. Base speed is half this. */
 	uint8_t div_min[2];				/* minimum divisor (to base speed), inclusive */
 	uint8_t div_max[2];				/* maximum divisor (to base speed), inclusive */
-} __packed;
+} __attribute__((packed));
 
 #define JTAG_PROTO_CAPS_DATA_LEN                255
 #define JTAG_PROTO_CAPS_SPEED_APB_TYPE          1

src/jtag/drivers/opendous.c

@@ -796,17 +796,12 @@ int opendous_usb_read(struct opendous_jtag *opendous_jtag)
 
 void opendous_debug_buffer(uint8_t *buffer, int length)
 {
-	char line[81];
-	char s[4];
-	int i;
-	int j;
+	char line[8 + 3 * BYTES_PER_LINE + 1];
 
-	for (i = 0; i < length; i += BYTES_PER_LINE) {
-		snprintf(line, 5, "%04x", i);
-		for (j = i; j < i + BYTES_PER_LINE && j < length; j++) {
-			snprintf(s, 4, " %02x", buffer[j]);
-			strcat(line, s);
-		}
+	for (int i = 0; i < length; i += BYTES_PER_LINE) {
+		int n = snprintf(line, 9, "%04x", i);
+		for (int j = i; j < i + BYTES_PER_LINE && j < length; j++)
+			n += snprintf(line + n, 4, " %02x", buffer[j]);
 		LOG_DEBUG("%s", line);
 	}
 }

src/jtag/drivers/vdebug.c

@@ -1246,7 +1246,7 @@ static const struct command_registration vdebug_command_handlers[] = {
 	{
 		.name = "mem_path",
 		.handler = &vdebug_set_mem,
-		.mode = COMMAND_ANY,
+		.mode = COMMAND_CONFIG,
 		.help = "set the design memory for the code load",
 		.usage = "<path> <base_address> <size>",
 	},

src/jtag/drivers/xds110.c

@@ -1354,11 +1354,13 @@ static void xds110_swd_queue_cmd(uint8_t cmd, uint32_t *value)
 static void xds110_swd_read_reg(uint8_t cmd, uint32_t *value,
 	uint32_t ap_delay_clk)
 {
+	assert(cmd & SWD_CMD_RNW);
 	xds110_swd_queue_cmd(cmd, value);
 }
 static void xds110_swd_write_reg(uint8_t cmd, uint32_t value,
 	uint32_t ap_delay_clk)
 {
+	assert(!(cmd & SWD_CMD_RNW));
 	xds110_swd_queue_cmd(cmd, &value);
 }
 

src/rtos/ThreadX.c

@@ -320,6 +320,12 @@ static int threadx_update_threads(struct rtos *rtos)
 		rtos->thread_details->thread_name_str = malloc(sizeof(tmp_str));
 		strcpy(rtos->thread_details->thread_name_str, tmp_str);
 
+		/* If we just invented thread 1 to represent the current execution, we
+		 * need to make sure the RTOS object also claims it's the current thread
+		 * so that threadx_get_thread_reg_list() doesn't attempt to read a
+		 * thread control block at 0x00000001. */
+		rtos->current_thread = 1;
+
 		if (thread_list_size == 0) {
 			rtos->thread_count = 1;
 			return ERROR_OK;
@@ -364,16 +370,21 @@ static int threadx_update_threads(struct rtos *rtos)
 		}
 
 		/* Read the thread name */
-		retval =
-			target_read_buffer(rtos->target,
-				name_ptr,
-				THREADX_THREAD_NAME_STR_SIZE,
-				(uint8_t *)&tmp_str);
-		if (retval != ERROR_OK) {
-			LOG_ERROR("Error reading thread name from ThreadX target");
-			return retval;
+		tmp_str[0] = '\x00';
+
+		/* Check if thread has a valid name */
+		if (name_ptr != 0) {
+			retval =
+				target_read_buffer(rtos->target,
+					name_ptr,
+					THREADX_THREAD_NAME_STR_SIZE,
+					(uint8_t *)&tmp_str);
+			if (retval != ERROR_OK) {
+				LOG_ERROR("Error reading thread name from ThreadX target");
+				return retval;
+			}
+			tmp_str[THREADX_THREAD_NAME_STR_SIZE - 1] = '\x00';
 		}
-		tmp_str[THREADX_THREAD_NAME_STR_SIZE-1] = '\x00';
 
 		if (tmp_str[0] == '\x00')
 			strcpy(tmp_str, "No Name");

src/rtos/hwthread.c

@@ -78,9 +78,11 @@ static int hwthread_fill_thread(struct rtos *rtos, struct target *curr, int thre
 static int hwthread_update_threads(struct rtos *rtos)
 {
 	int threads_found = 0;
+	int thread_list_size = 0;
 	struct target_list *head;
 	struct target *target;
 	int64_t current_thread = 0;
+	int64_t current_threadid = rtos->current_threadid; /* thread selected by GDB */
 	enum target_debug_reason current_reason = DBG_REASON_UNDEFINED;
 
 	if (!rtos)
@@ -99,13 +101,22 @@ static int hwthread_update_threads(struct rtos *rtos)
 			if (!target_was_examined(curr))
 				continue;
 
-			++threads_found;
+			++thread_list_size;
 		}
 	} else
-		threads_found = 1;
+		thread_list_size = 1;
+
+	/* restore the threadid which is currently selected by GDB
+	 * because rtos_free_threadlist() wipes out it
+	 * (GDB thread id is 1-based indexing) */
+	if (current_threadid <= thread_list_size)
+		rtos->current_threadid = current_threadid;
+	else
+		LOG_WARNING("SMP node change, disconnect GDB from core/thread %" PRId64,
+			    current_threadid);
 
 	/* create space for new thread details */
-	rtos->thread_details = malloc(sizeof(struct thread_detail) * threads_found);
+	rtos->thread_details = malloc(sizeof(struct thread_detail) * thread_list_size);
 
 	if (target->smp) {
 		/* loop over all threads */
@@ -170,10 +181,13 @@ static int hwthread_update_threads(struct rtos *rtos)
 			default:
 				break;
 			}
+
+			threads_found++;
 		}
 	} else {
 		hwthread_fill_thread(rtos, target, threads_found);
 		current_thread = threadid_from_target(target);
+		threads_found++;
 	}
 
 	rtos->thread_count = threads_found;
@@ -251,10 +265,19 @@ static int hwthread_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
 	for (int i = 0; i < reg_list_size; i++) {
 		if (!reg_list[i] || reg_list[i]->exist == false || reg_list[i]->hidden)
 			continue;
-		(*rtos_reg_list)[j].number = (*reg_list)[i].number;
-		(*rtos_reg_list)[j].size = (*reg_list)[i].size;
-		memcpy((*rtos_reg_list)[j].value, (*reg_list)[i].value,
-				((*reg_list)[i].size + 7) / 8);
+		if (!reg_list[i]->valid) {
+			retval = reg_list[i]->type->get(reg_list[i]);
+			if (retval != ERROR_OK) {
+				LOG_ERROR("Couldn't get register %s.", reg_list[i]->name);
+				free(reg_list);
+				free(*rtos_reg_list);
+				return retval;
+			}
+		}
+		(*rtos_reg_list)[j].number = reg_list[i]->number;
+		(*rtos_reg_list)[j].size = reg_list[i]->size;
+		memcpy((*rtos_reg_list)[j].value, reg_list[i]->value,
+				DIV_ROUND_UP(reg_list[i]->size, 8));
 		j++;
 	}
 	free(reg_list);

src/target/aarch64.c

@@ -2546,23 +2546,20 @@ static int aarch64_examine_first(struct target *target)
 	if (!pc)
 		return ERROR_FAIL;
 
-	if (armv8->debug_ap) {
-		dap_put_ap(armv8->debug_ap);
-		armv8->debug_ap = NULL;
-	}
-
-	if (pc->adiv5_config.ap_num == DP_APSEL_INVALID) {
-		/* Search for the APB-AB */
-		retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv8->debug_ap);
-		if (retval != ERROR_OK) {
-			LOG_ERROR("Could not find APB-AP for debug access");
-			return retval;
-		}
-	} else {
-		armv8->debug_ap = dap_get_ap(swjdp, pc->adiv5_config.ap_num);
-		if (!armv8->debug_ap) {
-			LOG_ERROR("Cannot get AP");
-			return ERROR_FAIL;
+	if (!armv8->debug_ap) {
+		if (pc->adiv5_config.ap_num == DP_APSEL_INVALID) {
+			/* Search for the APB-AB */
+			retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv8->debug_ap);
+			if (retval != ERROR_OK) {
+				LOG_ERROR("Could not find APB-AP for debug access");
+				return retval;
+			}
+		} else {
+			armv8->debug_ap = dap_get_ap(swjdp, pc->adiv5_config.ap_num);
+			if (!armv8->debug_ap) {
+				LOG_ERROR("Cannot get AP");
+				return ERROR_FAIL;
+			}
 		}
 	}
 

src/target/armv7m.c

@@ -116,27 +116,27 @@ static const struct {
 	{ ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
 	{ ARMV7M_CONTROL, "control", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
 
-	/* ARMv8-M specific registers */
-	{ ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-	{ ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-	{ ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-	{ ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-	{ ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-	{ ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-	{ ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-	{ ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
+	/* ARMv8-M security extension (TrustZone) specific registers */
+	{ ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
 
 	{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, "pmsk_bpri_fltmsk_ctrl_s", 32, REG_TYPE_INT, NULL, NULL },
-	{ ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-	{ ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-	{ ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-	{ ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+	{ ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
 
 	{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, "pmsk_bpri_fltmsk_ctrl_ns", 32, REG_TYPE_INT, NULL, NULL },
-	{ ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-	{ ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-	{ ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-	{ ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+	{ ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+	{ ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
 
 	/* FPU registers */
 	{ ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
@@ -529,6 +529,9 @@ int armv7m_start_algorithm(struct target *target,
 	/* Store all non-debug execution registers to armv7m_algorithm_info context */
 	for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
 		struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
+		if (!reg->exist)
+			continue;
+
 		if (!reg->valid)
 			armv7m_get_core_reg(reg);
 
@@ -688,16 +691,19 @@ int armv7m_wait_algorithm(struct target *target,
 	}
 
 	for (int i = armv7m->arm.core_cache->num_regs - 1; i >= 0; i--) {
+		struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
+		if (!reg->exist)
+			continue;
+
 		uint32_t regvalue;
-		regvalue = buf_get_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32);
+		regvalue = buf_get_u32(reg->value, 0, 32);
 		if (regvalue != armv7m_algorithm_info->context[i]) {
 			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
-					armv7m->arm.core_cache->reg_list[i].name,
-				armv7m_algorithm_info->context[i]);
-			buf_set_u32(armv7m->arm.core_cache->reg_list[i].value,
+					  reg->name, armv7m_algorithm_info->context[i]);
+			buf_set_u32(reg->value,
 				0, 32, armv7m_algorithm_info->context[i]);
-			armv7m->arm.core_cache->reg_list[i].valid = true;
-			armv7m->arm.core_cache->reg_list[i].dirty = true;
+			reg->valid = true;
+			reg->dirty = true;
 		}
 	}
 

src/target/cortex_a.c

@@ -2246,7 +2246,7 @@ static int cortex_a_write_cpu_memory(struct target *target,
 	/* Switch to non-blocking mode if not already in that mode. */
 	retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 
 	/* Mark R0 as dirty. */
 	arm_reg_current(arm, 0)->dirty = true;
@@ -2254,16 +2254,16 @@ static int cortex_a_write_cpu_memory(struct target *target,
 	/* Read DFAR and DFSR, as they will be modified in the event of a fault. */
 	retval = cortex_a_read_dfar_dfsr(target, &orig_dfar, &orig_dfsr, &dscr);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 
 	/* Get the memory address into R0. */
 	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
 			armv7a->debug_base + CPUDBG_DTRRX, address);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 	retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 
 	if (size == 4 && (address % 4) == 0) {
 		/* We are doing a word-aligned transfer, so use fast mode. */
@@ -2288,7 +2288,6 @@ static int cortex_a_write_cpu_memory(struct target *target,
 		retval = cortex_a_write_cpu_memory_slow(target, size, count, buffer, &dscr);
 	}
 
-out:
 	final_retval = retval;
 
 	/* Switch to non-blocking mode if not already in that mode. */
@@ -2564,7 +2563,7 @@ static int cortex_a_read_cpu_memory(struct target *target,
 	/* Switch to non-blocking mode if not already in that mode. */
 	retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 
 	/* Mark R0 as dirty. */
 	arm_reg_current(arm, 0)->dirty = true;
@@ -2572,16 +2571,16 @@ static int cortex_a_read_cpu_memory(struct target *target,
 	/* Read DFAR and DFSR, as they will be modified in the event of a fault. */
 	retval = cortex_a_read_dfar_dfsr(target, &orig_dfar, &orig_dfsr, &dscr);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 
 	/* Get the memory address into R0. */
 	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
 			armv7a->debug_base + CPUDBG_DTRRX, address);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 	retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
 	if (retval != ERROR_OK)
-		goto out;
+		return retval;
 
 	if (size == 4 && (address % 4) == 0) {
 		/* We are doing a word-aligned transfer, so use fast mode. */
@@ -2607,7 +2606,6 @@ static int cortex_a_read_cpu_memory(struct target *target,
 		retval = cortex_a_read_cpu_memory_slow(target, size, count, buffer, &dscr);
 	}
 
-out:
 	final_retval = retval;
 
 	/* Switch to non-blocking mode if not already in that mode. */
@@ -2874,23 +2872,20 @@ static int cortex_a_examine_first(struct target *target)
 	int retval = ERROR_OK;
 	uint32_t didr, cpuid, dbg_osreg, dbg_idpfr1;
 
-	if (armv7a->debug_ap) {
-		dap_put_ap(armv7a->debug_ap);
-		armv7a->debug_ap = NULL;
-	}
-
-	if (pc->ap_num == DP_APSEL_INVALID) {
-		/* Search for the APB-AP - it is needed for access to debug registers */
-		retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
-		if (retval != ERROR_OK) {
-			LOG_ERROR("Could not find APB-AP for debug access");
-			return retval;
-		}
-	} else {
-		armv7a->debug_ap = dap_get_ap(swjdp, pc->ap_num);
-		if (!armv7a->debug_ap) {
-			LOG_ERROR("Cannot get AP");
-			return ERROR_FAIL;
+	if (!armv7a->debug_ap) {
+		if (pc->ap_num == DP_APSEL_INVALID) {
+			/* Search for the APB-AP - it is needed for access to debug registers */
+			retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
+			if (retval != ERROR_OK) {
+				LOG_ERROR("Could not find APB-AP for debug access");
+				return retval;
+			}
+		} else {
+			armv7a->debug_ap = dap_get_ap(swjdp, pc->ap_num);
+			if (!armv7a->debug_ap) {
+				LOG_ERROR("Cannot get AP");
+				return ERROR_FAIL;
+			}
 		}
 	}
 

src/target/cortex_m.c

@@ -879,16 +879,6 @@ static int cortex_m_poll(struct target *target)
 	struct cortex_m_common *cortex_m = target_to_cm(target);
 	struct armv7m_common *armv7m = &cortex_m->armv7m;
 
-	/* Check if debug_ap is available to prevent segmentation fault.
-	 * If the re-examination after an error does not find a MEM-AP
-	 * (e.g. the target stopped communicating), debug_ap pointer
-	 * can suddenly become NULL.
-	 */
-	if (!armv7m->debug_ap) {
-		target->state = TARGET_UNKNOWN;
-		return ERROR_TARGET_NOT_EXAMINED;
-	}
-
 	/* Read from Debug Halting Control and Status Register */
 	retval = cortex_m_read_dhcsr_atomic_sticky(target);
 	if (retval != ERROR_OK) {
@@ -2280,6 +2270,22 @@ static void cortex_m_dwt_free(struct target *target)
 	cm->dwt_cache = NULL;
 }
 
+static bool cortex_m_has_tz(struct target *target)
+{
+	struct armv7m_common *armv7m = target_to_armv7m(target);
+	uint32_t dauthstatus;
+
+	if (armv7m->arm.arch != ARM_ARCH_V8M)
+		return false;
+
+	int retval = target_read_u32(target, DAUTHSTATUS, &dauthstatus);
+	if (retval != ERROR_OK) {
+		LOG_WARNING("Error reading DAUTHSTATUS register");
+		return false;
+	}
+	return (dauthstatus & DAUTHSTATUS_SID_MASK) != 0;
+}
+
 #define MVFR0 0xe000ef40
 #define MVFR1 0xe000ef44
 
@@ -2311,23 +2317,20 @@ int cortex_m_examine(struct target *target)
 	/* hla_target shares the examine handler but does not support
 	 * all its calls */
 	if (!armv7m->is_hla_target) {
-		if (armv7m->debug_ap) {
-			dap_put_ap(armv7m->debug_ap);
-			armv7m->debug_ap = NULL;
-		}
-
-		if (cortex_m->apsel == DP_APSEL_INVALID) {
-			/* Search for the MEM-AP */
-			retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
-			if (retval != ERROR_OK) {
-				LOG_TARGET_ERROR(target, "Could not find MEM-AP to control the core");
-				return retval;
-			}
-		} else {
-			armv7m->debug_ap = dap_get_ap(swjdp, cortex_m->apsel);
-			if (!armv7m->debug_ap) {
-				LOG_ERROR("Cannot get AP");
-				return ERROR_FAIL;
+		if (!armv7m->debug_ap) {
+			if (cortex_m->apsel == DP_APSEL_INVALID) {
+				/* Search for the MEM-AP */
+				retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
+				if (retval != ERROR_OK) {
+					LOG_TARGET_ERROR(target, "Could not find MEM-AP to control the core");
+					return retval;
+				}
+			} else {
+				armv7m->debug_ap = dap_get_ap(swjdp, cortex_m->apsel);
+				if (!armv7m->debug_ap) {
+					LOG_ERROR("Cannot get AP");
+					return ERROR_FAIL;
+				}
 			}
 		}
 
@@ -2411,7 +2414,7 @@ int cortex_m_examine(struct target *target)
 			for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
 				armv7m->arm.core_cache->reg_list[idx].exist = false;
 
-		if (armv7m->arm.arch != ARM_ARCH_V8M)
+		if (!cortex_m_has_tz(target))
 			for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
 				armv7m->arm.core_cache->reg_list[idx].exist = false;
 

src/target/cortex_m.h

@@ -68,6 +68,9 @@ struct cortex_m_part_info {
 #define DCB_DEMCR	0xE000EDFC
 #define DCB_DSCSR	0xE000EE08
 
+#define DAUTHSTATUS	0xE000EFB8
+#define DAUTHSTATUS_SID_MASK	0x00000030
+
 #define DCRSR_WNR	BIT(16)
 
 #define DWT_CTRL	0xE0001000

src/target/dsp5680xx.c

@@ -2200,8 +2200,8 @@ int dsp5680xx_f_lock(struct target *target)
 	struct jtag_tap *tap_chp;
 
 	struct jtag_tap *tap_cpu;
-	uint16_t lock_word[] = { HFM_LOCK_FLASH };
-	retval = dsp5680xx_f_wr(target, (uint8_t *) (lock_word), HFM_LOCK_ADDR_L, 2, 1);
+	uint16_t lock_word = HFM_LOCK_FLASH;
+	retval = dsp5680xx_f_wr(target, (uint8_t *)&lock_word, HFM_LOCK_ADDR_L, 2, 1);
 	err_check_propagate(retval);
 
 	jtag_add_reset(0, 1);

src/target/esirisc_jtag.c

@@ -130,7 +130,9 @@ static int esirisc_jtag_recv(struct esirisc_jtag *jtag_info,
 	int num_in_bytes = DIV_ROUND_UP(num_in_bits, 8);
 
 	struct scan_field fields[3];
-	uint8_t r[num_in_bytes * 2];
+	/* prevent zero-size variable length array */
+	int r_size = num_in_bytes ? num_in_bytes * 2 : 1;
+	uint8_t r[r_size];
 
 	esirisc_jtag_set_instr(jtag_info, INSTR_DEBUG);
 

src/target/mem_ap.c

@@ -136,15 +136,12 @@ static int mem_ap_examine(struct target *target)
 	struct mem_ap *mem_ap = target->arch_info;
 
 	if (!target_was_examined(target)) {
-		if (mem_ap->ap) {
-			dap_put_ap(mem_ap->ap);
-			mem_ap->ap = NULL;
-		}
-
-		mem_ap->ap = dap_get_ap(mem_ap->dap, mem_ap->ap_num);
 		if (!mem_ap->ap) {
-			LOG_ERROR("Cannot get AP");
-			return ERROR_FAIL;
+			mem_ap->ap = dap_get_ap(mem_ap->dap, mem_ap->ap_num);
+			if (!mem_ap->ap) {
+				LOG_ERROR("Cannot get AP");
+				return ERROR_FAIL;
+			}
 		}
 		target_set_examined(target);
 		target->state = TARGET_UNKNOWN;

src/target/mips_m4k.c

@@ -900,7 +900,7 @@ static int mips_m4k_set_watchpoint(struct target *target,
 			LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
 	}
 
-	watchpoint->number = wp_num;
+	watchpoint_set(watchpoint, wp_num);
 	comparator_list[wp_num].used = 1;
 	comparator_list[wp_num].bp_value = watchpoint->address;
 

src/target/openrisc/or1k_du_adv.c

@@ -934,7 +934,7 @@ static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info,
 	void *t = NULL;
 	struct target *target = jtag_info->target;
 	if ((target->endianness == TARGET_BIG_ENDIAN) && (size != 1)) {
-		t = malloc(count * size * sizeof(uint8_t));
+		t = calloc(count * size, sizeof(uint8_t));
 		if (!t) {
 			LOG_ERROR("Out of memory");
 			return ERROR_FAIL;
@@ -947,6 +947,9 @@ static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info,
 		case 2:
 			buf_bswap16(t, buffer, size * count);
 			break;
+		default:
+			free(t);
+			return ERROR_TARGET_FAILURE;
 		}
 		buffer = t;
 	}

src/target/rtt.c

@@ -241,43 +241,37 @@ int target_rtt_find_control_block(struct target *target,
 		target_addr_t *address, size_t size, const char *id, bool *found,
 		void *user_data)
 {
+	target_addr_t address_end = *address + size;
 	uint8_t buf[1024];
 
 	*found = false;
 
-	size_t j = 0;
-	size_t cb_offset = 0;
+	size_t id_matched_length = 0;
 	const size_t id_length = strlen(id);
 
 	LOG_INFO("rtt: Searching for control block '%s'", id);
 
-	for (target_addr_t addr = 0; addr < size; addr = addr + sizeof(buf)) {
+	for (target_addr_t addr = *address; addr < address_end; addr += sizeof(buf)) {
 		int ret;
 
-		const size_t buf_size = MIN(sizeof(buf), size - addr);
-		ret = target_read_buffer(target, *address + addr, buf_size, buf);
+		const size_t buf_size = MIN(sizeof(buf), address_end - addr);
+		ret = target_read_buffer(target, addr, buf_size, buf);
 
 		if (ret != ERROR_OK)
 			return ret;
 
-		size_t start = 0;
-		size_t i = 0;
-
-		while (i < buf_size) {
-			if (buf[i] != id[j]) {
-				start++;
-				cb_offset++;
-				i = start;
-				j = 0;
-
-				continue;
+		for (size_t buf_off = 0; buf_off < buf_size; buf_off++) {
+			if (id_matched_length > 0 &&
+			    buf[buf_off] != id[id_matched_length]) {
+				/* Start from beginning */
+				id_matched_length = 0;
 			}
 
-			i++;
-			j++;
+			if (buf[buf_off] == id[id_matched_length])
+				id_matched_length++;
 
-			if (j == id_length) {
-				*address = *address + cb_offset;
+			if (id_matched_length == id_length) {
+				*address = addr + buf_off + 1 - id_length;
 				*found = true;
 				return ERROR_OK;
 			}

src/target/target.c

@@ -4251,11 +4251,19 @@ static void write_gmon(uint32_t *samples, uint32_t sample_num, const char *filen
 
 		/* max should be (largest sample + 1)
 		 * Refer to binutils/gprof/hist.c (find_histogram_for_pc) */
-		max++;
+		if (max < UINT32_MAX)
+			max++;
+
+		/* gprof requires (max - min) >= 2 */
+		while ((max - min) < 2) {
+			if (max < UINT32_MAX)
+				max++;
+			else
+				min--;
+		}
 	}
 
-	int address_space = max - min;
-	assert(address_space >= 2);
+	uint32_t address_space = max - min;
 
 	/* FIXME: What is the reasonable number of buckets?
 	 * The profiling result will be more accurate if there are enough buckets. */
@@ -4331,6 +4339,19 @@ COMMAND_HANDLER(handle_profile_command)
 
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], offset);
 
+	uint32_t start_address = 0;
+	uint32_t end_address = 0;
+	bool with_range = false;
+	if (CMD_ARGC == 4) {
+		with_range = true;
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], start_address);
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], end_address);
+		if (start_address > end_address || (end_address - start_address) < 2) {
+			command_print(CMD, "Error: end - start < 2");
+			return ERROR_COMMAND_ARGUMENT_INVALID;
+		}
+	}
+
 	uint32_t *samples = malloc(sizeof(uint32_t) * MAX_PROFILE_SAMPLE_NUM);
 	if (!samples) {
 		LOG_ERROR("No memory to store samples.");
@@ -4383,15 +4404,6 @@ COMMAND_HANDLER(handle_profile_command)
 		return retval;
 	}
 
-	uint32_t start_address = 0;
-	uint32_t end_address = 0;
-	bool with_range = false;
-	if (CMD_ARGC == 4) {
-		with_range = true;
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], start_address);
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], end_address);
-	}
-
 	write_gmon(samples, num_of_samples, CMD_ARGV[1],
 		   with_range, start_address, end_address, target, duration_ms);
 	command_print(CMD, "Wrote %s", CMD_ARGV[1]);
@@ -6433,16 +6445,52 @@ static int jim_target_names(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 	return JIM_OK;
 }
 
+static struct target_list *
+__attribute__((warn_unused_result))
+create_target_list_node(Jim_Obj *const name) {
+	int len;
+	const char *targetname = Jim_GetString(name, &len);
+	struct target *target = get_target(targetname);
+	LOG_DEBUG("%s ", targetname);
+	if (!target)
+		return NULL;
+
+	struct target_list *new = malloc(sizeof(struct target_list));
+	if (!new) {
+		LOG_ERROR("Out of memory");
+		return new;
+	}
+
+	new->target = target;
+	return new;
+}
+
+static int get_target_with_common_rtos_type(struct list_head *lh, struct target **result)
+{
+	struct target *target = NULL;
+	struct target_list *curr;
+	foreach_smp_target(curr, lh) {
+		struct rtos *curr_rtos = curr->target->rtos;
+		if (curr_rtos) {
+			if (target && target->rtos && target->rtos->type != curr_rtos->type) {
+				LOG_ERROR("Different rtos types in members of one smp target!");
+				return JIM_ERR;
+			}
+			target = curr->target;
+		}
+	}
+	*result = target;
+	return JIM_OK;
+}
+
 static int jim_target_smp(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 {
-	int i;
-	const char *targetname;
-	int retval, len;
 	static int smp_group = 1;
-	struct target *target = NULL;
-	struct target_list *head, *new;
 
-	retval = 0;
+	if (argc == 1) {
+		LOG_DEBUG("Empty SMP target");
+		return JIM_OK;
+	}
 	LOG_DEBUG("%d", argc);
 	/* argv[1] = target to associate in smp
 	 * argv[2] = target to associate in smp
@@ -6456,27 +6504,24 @@ static int jim_target_smp(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 	}
 	INIT_LIST_HEAD(lh);
 
-	for (i = 1; i < argc; i++) {
-
-		targetname = Jim_GetString(argv[i], &len);
-		target = get_target(targetname);
-		LOG_DEBUG("%s ", targetname);
-		if (target) {
-			new = malloc(sizeof(struct target_list));
-			new->target = target;
+	for (int i = 1; i < argc; i++) {
+		struct target_list *new = create_target_list_node(argv[i]);
+		if (new)
 			list_add_tail(&new->lh, lh);
-		}
 	}
 	/*  now parse the list of cpu and put the target in smp mode*/
-	foreach_smp_target(head, lh) {
-		target = head->target;
+	struct target_list *curr;
+	foreach_smp_target(curr, lh) {
+		struct target *target = curr->target;
 		target->smp = smp_group;
 		target->smp_targets = lh;
 	}
 	smp_group++;
 
-	if (target && target->rtos)
-		retval = rtos_smp_init(target);
+	struct target *rtos_target;
+	int retval = get_target_with_common_rtos_type(lh, &rtos_target);
+	if (retval == JIM_OK && rtos_target)
+		retval = rtos_smp_init(rtos_target);
 
 	return retval;
 }

tcl/cpld/xilinx-xcu.cfg

@@ -9,7 +9,7 @@ if { [info exists CHIPNAME] } {
 	set _CHIPNAME xcu
 }
 
-# The cvarious chips in the Ultrascale family have different IR length.
+# The various chips in the Ultrascale family have different IR length.
 # Set $CHIP before including this file to determine the device.
 array set _XCU_DATA {
 	XCKU025 {0x03824093 6}

tcl/interface/raspberrypi2-native.cfg

@@ -15,9 +15,9 @@ adapter driver bcm2835gpio
 bcm2835gpio peripheral_base 0x3F000000
 
 # Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
-# These depend on system clock, calibrated for stock 700MHz
+# These depend on system clock, calibrated for scaling_max_freq 900MHz
 # bcm2835gpio speed SPEED_COEFF SPEED_OFFSET
-bcm2835gpio speed_coeffs 146203 36
+bcm2835gpio speed_coeffs 225000 36
 
 # Each of the JTAG lines need a gpio number set: tck tms tdi tdo
 # Header pin numbers: 23 22 19 21

tcl/target/max32620.cfg

@@ -16,8 +16,10 @@ if {[using_jtag]} {
     swd newdap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
 }
 
+dap create max32620.dap -chain-position max32620.cpu
+
 # target configuration
-target create max32620.cpu cortex_m -chain-position max32620.cpu
+target create max32620.cpu cortex_m -dap max32620.dap
 max32620.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
 
 # Config Command: flash bank name driver base size chip_width bus_width target [driver_options]

tcl/target/max32625.cfg

@@ -16,8 +16,10 @@ if {[using_jtag]} {
     swd newdap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
 }
 
+dap create max32625.dap -chain-position max32625.cpu
+
 # target configuration
-target create max32625.cpu cortex_m -chain-position max32625.cpu
+target create max32625.cpu cortex_m -dap max32625.dap
 max32625.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
 
 # Config Command: flash bank name driver base size chip_width bus_width target [driver_options]

tcl/target/max3263x.cfg

@@ -16,8 +16,10 @@ if {[using_jtag]} {
     swd newdap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
 }
 
+dap create max3263x.dap -chain-position max3263x.cpu
+
 # target configuration
-target create max3263x.cpu cortex_m -chain-position max3263x.cpu
+target create max3263x.cpu cortex_m -dap max3263x.dap
 max3263x.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
 
 # Config Command: flash bank name driver base size chip_width bus_width target [driver_options]