forked from auracaster/openocd
3c69eee9ef
This new cmd adds the ability to choose the Cortex-M3 reset method used. It defaults to using SRST for reset if available otherwise it falls back to using NVIC VECTRESET. This is known to work on all cores. Move any luminary specific reset handling to the stellaris cfg file. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
87 lines
2.7 KiB
INI
87 lines
2.7 KiB
INI
# TI/Luminary Stellaris LM3S chip family
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME lm3s
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}
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# CPU TAP ID 0x1ba00477 for early Sandstorm parts
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# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
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# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
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# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
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# ... we'll ignore the JTAG version field, rather than list every
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# chip revision that turns up.
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x0ba00477
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}
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if { [info exists WORKAREASIZE ] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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# default to 8K working area
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set _WORKAREASIZE 0x2000
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
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-expected-id $_CPUTAPID -ignore-version
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
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# 8K working area at base of ram, not backed up
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#
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# NOTE: you may need or want to reconfigure the work area;
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# some parts have just 6K, and you may want to use other
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# addresses (at end of mem not beginning) or back it up.
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
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# JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
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# LM3S parts don't support RTCK
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#
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# NOTE: this may be increased by a reset-init handler, after it
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# configures and enables the PLL. Or you might need to decrease
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# this, if you're using a slower clock.
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adapter_khz 500
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# mrw: "memory read word", returns value of $reg
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proc mrw {reg} {
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set value ""
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mem2array value 32 $reg 1
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return $value(0)
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}
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$_TARGETNAME configure -event reset-start {
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adapter_khz 500
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#
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# When nRST is asserted on most Stellaris devices, it clears some of
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# the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
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# and OpenOCD depends on those TRMs. So we won't use SRST on those
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# chips. (Only power-on reset should affect debug state, beyond a
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# few specified bits; not the chip's nRST input, wired to SRST.)
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#
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# REVISIT current errata specs don't seem to cover this issue.
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# Do we have more details than this email?
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# https://lists.berlios.de/pipermail
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# /openocd-development/2008-August/003065.html
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#
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set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
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if {$device_class == 0 || $device_class == 1 || $device_class == 3} {
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# Sandstorm, Fury and DustDevil are able to use NVIC SYSRESETREQ
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cortex_m3 reset_config systesetreq
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} else {
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# Tempest and newer default to using NVIC VECTRESET
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# this does mean a reset-init event handler is required to reset
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# any peripherals
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cortex_m3 reset_config vectreset
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}
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}
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# flash configuration ... autodetects sizes, autoprobed
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flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
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