forked from auracaster/openocd
Andreas Fritiofson
d3445cd146
Instead of updating these regularly we can just accept any IDCODE for the boundary scan TAP. The only downside might be that it's not immediately obvious if you source a config for the wrong type of STM32. Change-Id: I96d4d81699a491b3a46de3f0d3fd078ffddad4e4 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3385 Tested-by: jenkins
103 lines
2.6 KiB
INI
103 lines
2.6 KiB
INI
# script for stm32l4x family
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#
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# stm32l4 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32l4x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# Smallest current target has 64kB ram, use 32kB by default to avoid surprises
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x8000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0351
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# Section 44.6.3 - corresponds to Cortex-M4 r0p1
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set _CPUTAPID 0x4ba00477
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} {
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set _CPUTAPID 0x2ba01477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
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# Common knowledges tells JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
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# the safe side.
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#
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# Note that there is a pretty wide band where things are
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# more or less stable, see http://openocd.zylin.com/#/c/3366/
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adapter_khz 500
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adapter_nsrst_delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event reset-init {
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# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
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# Use MSI 24 MHz clock, compliant even with VOS == 2.
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# 3 WS compliant with VOS == 2 and 24 MHz.
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mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency)
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mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL| MSI Range 10
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# Boost JTAG frequency
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adapter_khz 4000
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}
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$_TARGETNAME configure -event reset-start {
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# Reset clock is MSI (4 MHz)
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adapter_khz 500
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}
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$_TARGETNAME configure -event examine-end {
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0xE0042004 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0042008 0x00001800 0
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0xE0042004 0x00000020 0
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}
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