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tcl/target: Move TI targets to ti folder

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Move the ti targets to a TI folder. Since the folder is ti, we can
drop the "ti" prefix from the files themselves.

Done via the following script:

 mkdir target/ti
 FILES=`ls target/ti*.cfg target/omap*.cfg target/am335x.cfg
           target/amdm37x.cfg target/icepick.cfg target/stellaris.cfg
		   target/davinci.cfg`
 for cname in $FILES
 do
   bname=`basename $cname`
   nname=`echo $bname|sed -e "s/^ti-//g"|sed -e "s/ti_//g"`
   npath="target/ti/$nname"
   echo "$cname => $npath"
   fref=`git grep $cname .|cut -d ':' -f1|sort -u`
   sed -i -e "s&$cname&$npath&g" $fref
   git mv $cname $npath
 done

Change-Id: I9f94dc6bb01f73721d4ff96be92cb51de2cbf0e2
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9203
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Nishanth Menon
2025-11-03 11:02:57 -06:00
committed by Antonio Borneo
parent 5479c58d23
commit 2f8ddc0835
105 changed files with 101 additions and 101 deletions
Download Patch File Download Diff File Expand all files Collapse all files

114
tcl/target/ti/am335x.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
source [find target/ti/icepick.cfg]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME am335x
}
# set the taps to be enabled by default. this can be overridden
# by setting DEFAULT_TAPS in a separate configuration file
# or directly on the command line.
if { [info exists DEFAULT_TAPS] } {
set _DEFAULT_TAPS "$DEFAULT_TAPS"
} else {
set _DEFAULT_TAPS "$_CHIPNAME.tap"
}
#
# Main DAP
#
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4b6b902f
}
jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0"
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
#
# M3 DAP
#
if { [info exists M3_DAP_TAPID] } {
set _M3_DAP_TAPID $M3_DAP_TAPID
} else {
set _M3_DAP_TAPID 0x4b6b902f
}
jtag newtap $_CHIPNAME m3_tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m3_tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0"
dap create $_CHIPNAME.m3_dap -chain-position $_CHIPNAME.m3_tap
#
# ICEpick-D (JTAG route controller)
#
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b94402f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
jtag configure $_CHIPNAME.jrc -event setup {
global _DEFAULT_TAPS
enable_default_taps $_DEFAULT_TAPS
}
# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
#
# helper function that enables all taps passed as argument
#
proc enable_default_taps { taps } {
foreach tap $taps {
jtag tapenable $tap
}
}
#
# Cortex-M3 target
#
set _TARGETNAME_2 $_CHIPNAME.m3
target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.m3_dap
#
# Cortex-A8 target
#
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80001000
# SRAM: 64K at 0x4030.0000; use the first 16K
$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
# when putting the target into 'reset halt', we need to disable the watchdog as
# it would otherwise trigger while we're in JTAG
# FIXME: unify with target/ti/am437x.cfg
source [find mem_helper.tcl]
set WDT1_BASE_ADDR 0x44e35000
set WDT1_W_PEND_WSPR [expr {$WDT1_BASE_ADDR + 0x0034}]
set WDT1_WSPR [expr {$WDT1_BASE_ADDR + 0x0048}]
proc disable_watchdog { } {
global WDT1_WSPR
global WDT1_W_PEND_WSPR
global _TARGETNAME
set curstate [$_TARGETNAME curstate]
if { [string compare $curstate halted] == 0 } {
set WDT_DISABLE_SEQ1 0xaaaa
set WDT_DISABLE_SEQ2 0x5555
mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1
# Empty body to make sure this executes as fast as possible.
# We don't want any delays here otherwise romcode might start
# executing and end up changing state of certain IPs.
while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
}
}
$_TARGETNAME configure -event reset-end { disable_watchdog }

1003
tcl/target/ti/am437x.cfg Normal file
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213
tcl/target/ti/amdm37x.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (C) 2010-2011 by Karl Kurbjun
# Copyright (C) 2009-2011 by Øyvind Harboe
# Copyright (C) 2009 by David Brownell
# Copyright (C) 2009 by Magnus Lundin
#
# TI AM/DM37x Technical Reference Manual (Version R)
# http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf
#
# This script is based on the AM3517 initialization. It should be considered
# preliminary since it needs more complete testing and only the basic
# operations work.
#
###############################################################################
# User modifiable parameters
###############################################################################
# This script uses the variable CHIPTYPE to determine whether this is an AM35x
# or DM37x target. If CHIPTYPE is not set it will error out.
if { [info exists CHIPTYPE] } {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME $CHIPTYPE
}
switch $CHIPTYPE {
dm37x {
# Primary TAP: ICEPick-C (JTAG route controller) and boundary scan
set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f"
}
am35x {
# Primary TAP: ICEPick-C (JTAG route controller) and boundary scan
set _JRC_TAPID "-expected-id 0x0b7ae02f -expected-id 0x0b86802f"
}
default {
error "ERROR: CHIPTYPE was set, but it was not set to a valid value. Acceptable values are \"dm37x\" or \"am35x\"."
}
}
} else {
error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration."
}
# Run the adapter at the fastest acceptable speed with the slowest possible
# core clock.
adapter speed 10
###############################################################################
# JTAG setup
# The OpenOCD commands are described in the TAP Declaration section
# http://openocd.org/doc/html/TAP-Declaration.html
###############################################################################
# The AM/DM37x has an ICEPick module in it like many of TI's other devices. More
# can be read about this module in sprugn4r in chapter 27: "Debug and
# Emulation". The module is used to route the JTAG chain to the various
# subsystems in the chip.
source [find target/ti/icepick.cfg]
# The TAP order should be described from the TDO connection in OpenOCD to the
# TDI pin. The OpenOCD FAQ describes this in more detail:
# http://openocd.org/doc/html/FAQ.html
# From SPRUGN4R CH27 the available secondary TAPs are in this order from TDO:
#
# Device | TAP number
# ---------|------------
# DAP | 3
# Sequencer| 2 Note: The sequencer is an ARM968
# DSP | 1
# D2D | 0
#
# Right now the only secondary tap enabled is the DAP so the rest are left
# undescribed.
######
# Start of Chain Description
# The Secondary TAPs all have enable functions defined for use with the ICEPick
# Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but
# the TAP numbers for ICEPick do not change.
#
# TODO: A disable function should also be added.
######
# Secondary TAP: DAP is closest to the TDO output
# The TAP enable event also needs to be described
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -disable
jtag configure $_CHIPNAME.cpu -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
# These taps are only present in the DM37x series.
if { $CHIPTYPE == "dm37x" } {
# Secondary TAP: Sequencer (ARM968) it is not in the chain by default
# The ICEPick can be used to enable it in the chain.
jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
jtag configure $_CHIPNAME.arm2 -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 2"
# Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable)
# The ICEPick can be used to enable it in the chain.
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
jtag configure $_CHIPNAME.dsp -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
}
# Secondary TAP: D2D it is not in the chain by default (-disable)
# The ICEPick can be used to enable it in the chain.
# This IRLEN is probably incorrect - not sure where the documentation is.
jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
jtag configure $_CHIPNAME.d2d -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
# Primary TAP: ICEPick - it is closest to TDI so last in the chain
eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID"
######
# End of Chain Description
######
######
# Start JTAG TAP events
######
# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
# Enable the DAP TAP
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
######
# End JTAG TAP events
######
###############################################################################
# Target Setup:
# This section is described in the OpenOCD documentation under CPU Configuration
# http://openocd.org/doc/html/CPU-Configuration.html
###############################################################################
# Create the CPU target to be used with GDB: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
# 16K to be used as a scratchpad for OpenOCD.
$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
######
# Start Target Reset Event Setup:
######
# Set the JTAG clock down to 10 kHz to be sure that it will work with the
# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
# *after* PLL and clock tree setup.
$_TARGETNAME configure -event "reset-start" { adapter speed 10 }
# Describe the reset assert process for openocd - this is asserted with the
# ICEPick
$_TARGETNAME configure -event "reset-assert" {
global _CHIPNAME
# assert warm system reset through ICEPick
icepick_c_wreset $_CHIPNAME.jrc
}
# After the reset is asserted we need to re-initialize debugging and speed up
# the JTAG clock.
$_TARGETNAME configure -event reset-assert-post {
global _TARGETNAME
amdm37x_dbginit $_TARGETNAME
adapter speed 1000
}
$_TARGETNAME configure -event gdb-attach {
global _TARGETNAME
amdm37x_dbginit $_TARGETNAME
echo "Halting target"
halt
}
######
# End Target Reset Event Setup:
######
###############################################################################
# Target Functions
# Add any functions needed for the target here
###############################################################################
# Run this to enable invasive debugging. This is run automatically in the
# reset sequence.
proc amdm37x_dbginit {target} {
# General Cortex-A8 debug initialisation
cortex_a dbginit
# Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
# access to the signal appears to be implementation specific. TI does not
# describe this register much except a quick line that states DBGEM (sic) is
# at this address and this bit.
$target mww phys 0x5401d030 0x00002000
}

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tcl/target/ti/ar7.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments AR7 SOC - used in many adsl modems.
# http://www.linux-mips.org/wiki/AR7
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME ti-ar7
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x0000100f
}
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_CHIPNAME.cpu
# use onboard 4k sram as working area
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000

59
tcl/target/ti/calypso.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
#
# TI Calypso (lite) G2 C035 Digital Base Band chip
#
# ARM7TDMIE + DSP subchip (S28C128)
#
# 512K SRAM Calypso
# 256K SRAM Calypso lite
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME calypso
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x3100e02f
}
# Work-area is a space in RAM used for flash programming
# By default use 64kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x10000
}
adapter speed 1000
reset_config trst_and_srst
jtag newtap $_CHIPNAME dsp -expected-id 0x00000000 -irlen 8
jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
# target
set _TARGETNAME $_CHIPNAME.arm
target create $_TARGETNAME arm7tdmi -endian little -chain-position $_TARGETNAME
# workarea
$_TARGETNAME configure -work-area-phys 0x00800000 -work-area-size $_WORKAREASIZE -work-area-backup 1
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable
$_TARGETNAME configure -event examine-start {
irscan calypso.arm 0x0b -endstate DRPAUSE
drscan calypso.arm 2 2 -endstate RUN/IDLE
}

13
tcl/target/ti/cc13x0.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments CC13x0 - ARM Cortex-M3
#
# http://www.ti.com
#
set CHIPNAME cc13x0
set JRC_TAPID 0x0B9BE02F
set WORKAREASIZE 0x4000
source [find target/ti/cc26x0.cfg]

13
tcl/target/ti/cc13x2.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments CC13x2 - ARM Cortex-M4
#
# http://www.ti.com
#
set CHIPNAME cc13x2
set JRC_TAPID 0x0BB4102F
set WORKAREASIZE 0x7000
source [find target/ti/cc26x0.cfg]

47
tcl/target/ti/cc2538.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# Config for Texas Instruments low power RF SoC CC2538
# http://www.ti.com/lit/pdf/swru319
adapter speed 100
source [find target/ti/icepick.cfg]
source [find target/ti/cjtag.cfg]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cc2538
}
#
# Main DAP
#
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x8B96402F
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
#
# ICEpick-C (JTAG route controller)
#
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x8B96402F
}
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
# A start sequence is needed to change from cJTAG (Compact JTAG) to
# 4-pin JTAG before talking via JTAG commands
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
#
# Cortex-M3 target
#
set _TARGETNAME $_CHIPNAME.cpu
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap

57
tcl/target/ti/cc26x0.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments CC26x0 - ARM Cortex-M3
#
# http://www.ti.com
#
source [find target/ti/icepick.cfg]
source [find target/ti/cjtag.cfg]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cc26x0
}
#
# Main DAP
#
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4BA00477
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
#
# ICEpick-C (JTAG route controller)
#
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0B99A02F
}
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
# A start sequence is needed to change from 2-pin cJTAG to 4-pin JTAG
jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
set _TARGETNAME $_CHIPNAME.cpu
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x4000
}
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
cortex_m reset_config vectreset

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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments CC26x2 - ARM Cortex-M4
#
# http://www.ti.com
#
set CHIPNAME cc26x2
set JRC_TAPID 0x0BB4102F
set WORKAREASIZE 0x7000
source [find target/ti/cc26x0.cfg]

13
tcl/target/ti/cc26x2x7.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments CC26x2 - ARM Cortex-M4
#
# http://www.ti.com
#
set CHIPNAME cc26x2x7
set JRC_TAPID 0x1BB7702F
set WORKAREASIZE 0x7000
source [find target/ti/cc26x0.cfg]

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tcl/target/ti/cc3220sf.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments CC3220SF - ARM Cortex-M4
#
# http://www.ti.com/CC3220SF
#
source [find target/swj-dp.tcl]
source [find target/ti/icepick.cfg]
source [find target/ti/cc32xx.cfg]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
#
# On CC32xx family of devices, sysreqreset is disabled, and vectreset is
# blocked by the boot loader (stops in a while(1) statement). srst reset can
# leave the target in a state that prevents debug. The following uses the
# soft_reset_halt command to reset and halt the target. Then the PC and stack
# are initialized from internal flash. This allows for a more reliable reset,
# but with two caveats: it only works for the SF variant that has internal
# flash, and it only resets the CPU and not any peripherals.
#
proc ocd_process_reset_inner { MODE } {
soft_reset_halt
# Initialize MSP, PSP, and PC from vector table at flash 0x01000800
set boot [read_memory 0x01000800 32 2]
reg msp [lindex $boot 0]
reg psp [lindex $boot 0]
reg pc [lindex $boot 1]
if { 0 == [string compare $MODE run ] } {
resume
}
cc32xx.cpu invoke-event reset-end
}

63
tcl/target/ti/cc32xx.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments CC32xx - ARM Cortex-M4
#
# http://www.ti.com/product/CC3200
# http://www.ti.com/product/CC3220
#
source [find target/swj-dp.tcl]
source [find target/ti/icepick.cfg]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cc32xx
}
#
# Main DAP
#
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
if {[using_jtag]} {
set _DAP_TAPID 0x4BA00477
} else {
set _DAP_TAPID 0x2BA01477
}
}
if {[using_jtag]} {
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
} else {
swj_newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID
}
#
# ICEpick-C (JTAG route controller)
#
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0B97C02F
}
if {[using_jtag]} {
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
}
set _TARGETNAME $_CHIPNAME.cpu
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x2000
}
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

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tcl/target/ti/cjtag.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# A start sequence to change from cJTAG to 4-pin JTAG
# This is needed for CC2538 and CC26xx to be able to communicate through JTAG
# Read section 6.3 in http://www.ti.com/lit/pdf/swru319 for more information.
proc ti_cjtag_to_4pin_jtag {jrc} {
# Bypass
runtest 20
irscan $jrc 0x3f -endstate RUN/IDLE
# Two zero bit scans and a one bit drshift
pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRUPDATE RUN/IDLE
pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
# A two bit drhift and a 9 bit drshift
pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRUPDATE RUN/IDLE
pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRPAUSE
pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
# Bypass
irscan $jrc 0x3f -endstate RUN/IDLE
# Set ICEPick IDCODE in data register
irscan $jrc 0x04 -endstate RUN/IDLE
}

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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Utility code for DaVinci-family chips
#
# davinci_pinmux: assigns PINMUX$reg <== $value
proc davinci_pinmux {soc reg value} {
mww [expr {[dict get $soc sysbase] + 4 * $reg}] $value
}
source [find mem_helper.tcl]
#
# pll_setup: initialize PLL
# - pll_addr ... physical addr of controller
# - mult ... pll multiplier
# - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
#
# For PLLs that don't have a given register (e.g. plldiv8), or where a
# given divider is non-programmable, caller provides *NO* config mapping.
#
# PLL version 0x02: tested on dm355
# REVISIT: On dm6446/dm357 the PLLRST polarity is different.
proc pll_v02_setup {pll_addr mult config} {
set pll_ctrl_addr [expr {$pll_addr + 0x100}]
set pll_ctrl [mrw $pll_ctrl_addr]
# 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
# NOTE: this assumes we should clear that bit
set pll_ctrl [expr {$pll_ctrl & ~0x0100}]
mww $pll_ctrl_addr $pll_ctrl
# 2 - clear PLLENSRC (bit 5)
set pll_ctrl [expr {$pll_ctrl & ~0x0020}]
mww $pll_ctrl_addr $pll_ctrl
# 3 - clear PLLEN (bit 0) ... enter bypass mode
set pll_ctrl [expr {$pll_ctrl & ~0x0001}]
mww $pll_ctrl_addr $pll_ctrl
# 4 - wait at least 4 refclk cycles
sleep 1
# 5 - set PLLRST (bit 3)
set pll_ctrl [expr {$pll_ctrl | 0x0008}]
mww $pll_ctrl_addr $pll_ctrl
# 6 - set PLLDIS (bit 4)
set pll_ctrl [expr {$pll_ctrl | 0x0010}]
mww $pll_ctrl_addr $pll_ctrl
# 7 - clear PLLPWRDN (bit 1)
set pll_ctrl [expr {$pll_ctrl & ~0x0002}]
mww $pll_ctrl_addr $pll_ctrl
# 8 - clear PLLDIS (bit 4)
set pll_ctrl [expr {$pll_ctrl & ~0x0010}]
mww $pll_ctrl_addr $pll_ctrl
# 9 - optional: write prediv, postdiv, and pllm
# NOTE: for dm355 PLL1, postdiv is controlled via MISC register
mww [expr {$pll_addr + 0x0110}] [expr {($mult - 1) & 0xff}]
if { [dict exists $config prediv] } {
set div [dict get $config prediv]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0114}] $div
}
if { [dict exists $config postdiv] } {
set div [dict get $config postdiv]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0128}] $div
}
# 10 - optional: set plldiv1, plldiv2, ...
# NOTE: this assumes some registers have their just-reset values:
# - PLLSTAT.GOSTAT is clear when we enter
# - ALNCTL has everything set
set go 0
if { [dict exists $config div1] } {
set div [dict get $config div1]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0118}] $div
set go 1
}
if { [dict exists $config div2] } {
set div [dict get $config div2]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x011c}] $div
set go 1
}
if { [dict exists $config div3] } {
set div [dict get $config div3]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0120}] $div
set go 1
}
if { [dict exists $config div4] } {
set div [dict get $config div4]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0160}] $div
set go 1
}
if { [dict exists $config div5] } {
set div [dict get $config div5]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0164}] $div
set go 1
}
if {$go != 0} {
# write pllcmd.GO; poll pllstat.GO
mww [expr {$pll_addr + 0x0138}] 0x01
set pllstat [expr {$pll_addr + 0x013c}]
while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
}
mww [expr {$pll_addr + 0x0138}] 0x00
# 11 - wait at least 5 usec for reset to finish
# (assume covered by overheads including JTAG messaging)
# 12 - clear PLLRST (bit 3)
set pll_ctrl [expr {$pll_ctrl & ~0x0008}]
mww $pll_ctrl_addr $pll_ctrl
# 13 - wait at least 8000 refclk cycles for PLL to lock
# if we assume 24 MHz (slowest osc), that's 1/3 msec
sleep 3
# 14 - set PLLEN (bit 0) ... leave bypass mode
set pll_ctrl [expr {$pll_ctrl | 0x0001}]
mww $pll_ctrl_addr $pll_ctrl
}
# PLL version 0x03: tested on dm365
proc pll_v03_setup {pll_addr mult config} {
set pll_ctrl_addr [expr {$pll_addr + 0x100}]
set pll_secctrl_addr [expr {$pll_addr + 0x108}]
set pll_ctrl [mrw $pll_ctrl_addr]
# 1 - power up the PLL
set pll_ctrl [expr {$pll_ctrl & ~0x0002}]
mww $pll_ctrl_addr $pll_ctrl
# 2 - clear PLLENSRC (bit 5)
set pll_ctrl [expr {$pll_ctrl & ~0x0020}]
mww $pll_ctrl_addr $pll_ctrl
# 2 - clear PLLEN (bit 0) ... enter bypass mode
set pll_ctrl [expr {$pll_ctrl & ~0x0001}]
mww $pll_ctrl_addr $pll_ctrl
# 3 - wait at least 4 refclk cycles
sleep 1
# 4 - set PLLRST (bit 3)
set pll_ctrl [expr {$pll_ctrl | 0x0008}]
mww $pll_ctrl_addr $pll_ctrl
# 5 - wait at least 5 usec
sleep 1
# 6 - clear PLLRST (bit 3)
set pll_ctrl [expr {$pll_ctrl & ~0x0008}]
mww $pll_ctrl_addr $pll_ctrl
# 9 - optional: write prediv, postdiv, and pllm
mww [expr {$pll_addr + 0x0110}] [expr {($mult / 2) & 0x1ff}]
if { [dict exists $config prediv] } {
set div [dict get $config prediv]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0114}] $div
}
if { [dict exists $config postdiv] } {
set div [dict get $config postdiv]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0128}] $div
}
# 10 - write start sequence to PLLSECCTL
mww $pll_secctrl_addr 0x00470000
mww $pll_secctrl_addr 0x00460000
mww $pll_secctrl_addr 0x00400000
mww $pll_secctrl_addr 0x00410000
# 11 - optional: set plldiv1, plldiv2, ...
# NOTE: this assumes some registers have their just-reset values:
# - PLLSTAT.GOSTAT is clear when we enter
set aln 0
if { [dict exists $config div1] } {
set div [dict get $config div1]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0118}] $div
set aln [expr {$aln | 0x1}]
} else {
mww [expr {$pll_addr + 0x0118}] 0
}
if { [dict exists $config div2] } {
set div [dict get $config div2]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x011c}] $div
set aln [expr {$aln | 0x2}]
} else {
mww [expr {$pll_addr + 0x011c}] 0
}
if { [dict exists $config div3] } {
set div [dict get $config div3]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0120}] $div
set aln [expr {$aln | 0x4}]
} else {
mww [expr {$pll_addr + 0x0120}] 0
}
if { [dict exists $config oscdiv] } {
set div [dict get $config oscdiv]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0124}] $div
} else {
mww [expr {$pll_addr + 0x0124}] 0
}
if { [dict exists $config div4] } {
set div [dict get $config div4]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0160}] $div
set aln [expr {$aln | 0x8}]
} else {
mww [expr {$pll_addr + 0x0160}] 0
}
if { [dict exists $config div5] } {
set div [dict get $config div5]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0164}] $div
set aln [expr {$aln | 0x10}]
} else {
mww [expr {$pll_addr + 0x0164}] 0
}
if { [dict exists $config div6] } {
set div [dict get $config div6]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0168}] $div
set aln [expr {$aln | 0x20}]
} else {
mww [expr {$pll_addr + 0x0168}] 0
}
if { [dict exists $config div7] } {
set div [dict get $config div7]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x016c}] $div
set aln [expr {$aln | 0x40}]
} else {
mww [expr {$pll_addr + 0x016c}] 0
}
if { [dict exists $config div8] } {
set div [dict get $config div8]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0170}] $div
set aln [expr {$aln | 0x80}]
} else {
mww [expr {$pll_addr + 0x0170}] 0
}
if { [dict exists $config div9] } {
set div [dict get $config div9]
set div [expr {0x8000 | ($div - 1)}]
mww [expr {$pll_addr + 0x0174}] $div
set aln [expr {$aln | 0x100}]
} else {
mww [expr {$pll_addr + 0x0174}] 0
}
if {$aln != 0} {
# clear pllcmd.GO
mww [expr {$pll_addr + 0x0138}] 0x00
# write alignment flags
mww [expr {$pll_addr + 0x0140}] $aln
# write pllcmd.GO; poll pllstat.GO
mww [expr {$pll_addr + 0x0138}] 0x01
set pllstat [expr {$pll_addr + 0x013c}]
while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
}
mww [expr {$pll_addr + 0x0138}] 0x00
set addr [dict get $config ctladdr]
while {[expr {[mrw $addr] & 0x0e000000}] != 0x0e000000} { sleep 1 }
# 12 - set PLLEN (bit 0) ... leave bypass mode
set pll_ctrl [expr {$pll_ctrl | 0x0001}]
mww $pll_ctrl_addr $pll_ctrl
}
# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
# modules can be enabled.
# prepare a non-DSP module to be enabled; finish with psc_go
proc psc_enable {module} {
set psc_addr 0x01c41000
# write MDCTL
mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x03 0x1f
}
# prepare a non-DSP module to be reset; finish with psc_go
proc psc_reset {module} {
set psc_addr 0x01c41000
# write MDCTL
mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x01 0x1f
}
# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
proc psc_go {} {
set psc_addr 0x01c41000
set ptstat_addr [expr {$psc_addr + 0x0128}]
# just in case PTSTAT.go isn't clear
while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
# write PTCMD.go ... ignoring any DSP power domain
mww [expr {$psc_addr + 0x0120}] 1
# wait for PTSTAT.go to clear (again ignoring DSP power domain)
while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
}
#
# A reset using only SRST is a "Warm Reset", resetting everything in the
# chip except ARM emulation (and everything _outside_ the chip that hooks
# up to SRST). But many boards don't expose SRST via their JTAG connectors
# (it's not present on TI-14 headers).
#
# From the chip-only perspective, a "Max Reset" is a "Warm" reset ... except
# without any board-wide side effects, since it's triggered using JTAG using
# either (a) ARM watchdog timer, or (b) ICEpick.
#
proc davinci_wdog_reset {} {
set timer2_phys 0x01c21c00
# NOTE -- on entry
# - JTAG communication with the ARM *must* be working OK; this
# may imply using adaptive clocking or disabling WFI-in-idle
# - current target must be the DaVinci ARM
# - that ARM core must be halted
# - timer2 clock is still enabled (PSC 29 on most chips)
#
# Part I -- run regardless of being halted via JTAG
#
# NOTE: for now, we assume there's no DSP that could control the
# watchdog; or, equivalently, SUSPSRC.TMR2SRC says the watchdog
# suspend signal is controlled via ARM emulation suspend.
#
# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
mww phys [expr {$timer2_phys + 0x28}] 0x00004000
#
# Part II -- in case watchdog hasn't been set up
#
# TCR: disable, force internal clock source
mww phys [expr {$timer2_phys + 0x20}] 0
# TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
mww phys [expr {$timer2_phys + 0x24}] 0
mww phys [expr {$timer2_phys + 0x24}] 0x110b
# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
# so watchdog triggers ASAP
mww phys [expr {$timer2_phys + 0x10}] 0
mww phys [expr {$timer2_phys + 0x14}] 0
mww phys [expr {$timer2_phys + 0x18}] 0
mww phys [expr {$timer2_phys + 0x1c}] 0
# WDTCR: put into pre-active state, then active
mww phys [expr {$timer2_phys + 0x28}] 0xa5c64000
mww phys [expr {$timer2_phys + 0x28}] 0xda7e4000
#
# Part III -- it's ready to rumble
#
# WDTCR: write invalid WDKEY to trigger reset
mww phys [expr {$timer2_phys + 0x28}] 0x00004000
}

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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments DaVinci family: TMS320DM355
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME dm355
}
# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
# after JTAG reset until ICEpick is used to route them in.
set EMU01 "-disable"
# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
# needing any ICEpick interaction.
#set EMU01 "-enable"
source [find target/ti/icepick.cfg]
#
# Also note: when running without RTCK before the PLLs are set up, you
# may need to slow the JTAG clock down quite a lot (under 2 MHz).
#
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID] } {
set _ETB_TAPID $ETB_TAPID
} else {
set _ETB_TAPID 0x2b900f0f
}
jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
if { [info exists CPU_TAPID] } {
set _CPU_TAPID $CPU_TAPID
} else {
set _CPU_TAPID 0x07926001
}
jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
# Primary TAP: ICEpick (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b73b02f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
jtag configure $_CHIPNAME.jrc -event setup \
"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
################
# various symbol definitions, to avoid hard-wiring addresses
# and enable some sharing of DaVinci-family utility code
global dm355
set dm355 [ dict create ]
# Physical addresses for controllers and memory
# (Some of these are valid for many DaVinci family chips)
dict set dm355 sram0 0x00010000
dict set dm355 sram1 0x00014000
dict set dm355 sysbase 0x01c40000
dict set dm355 pllc1 0x01c40800
dict set dm355 pllc2 0x01c40c00
dict set dm355 psc 0x01c41000
dict set dm355 gpio 0x01c67000
dict set dm355 a_emif 0x01e10000
dict set dm355 a_emif_cs0 0x02000000
dict set dm355 a_emif_cs1 0x04000000
dict set dm355 ddr_emif 0x20000000
dict set dm355 ddr 0x80000000
dict set dm355 uart0 0x01c20000
dict set dm355 uart1 0x01c20400
dict set dm355 uart2 0x01e06000
source [find target/ti/davinci.cfg]
################
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
# and the ETB memory (4K) are other options, while trace is unused.
set _TARGETNAME $_CHIPNAME.arm
target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
# and that the work area is used only with a kernel mmu context ...
$_TARGETNAME configure \
-work-area-virt [expr {0xfffe0000 + 0x4000}] \
-work-area-phys [dict get $dm355 sram1] \
-work-area-size 0x4000 \
-work-area-backup 0
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
adapter speed 1500
$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
# trace setup
etm config $_TARGETNAME 16 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb

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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments DaVinci family: TMS320DM365
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME dm365
}
# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
# after JTAG reset until ICEpick is used to route them in.
set EMU01 "-disable"
# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
# needing any ICEpick interaction.
#set EMU01 "-enable"
source [find target/ti/icepick.cfg]
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID] } {
set _ETB_TAPID $ETB_TAPID
} else {
set _ETB_TAPID 0x2b900f0f
}
jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
if { [info exists CPU_TAPID] } {
set _CPU_TAPID $CPU_TAPID
} else {
set _CPU_TAPID 0x0792602f
}
jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
# Primary TAP: ICEpick (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b83e02f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
jtag configure $_CHIPNAME.jrc -event setup \
"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
################
# various symbol definitions, to avoid hard-wiring addresses
# and enable some sharing of DaVinci-family utility code
global dm365
set dm365 [ dict create ]
# Physical addresses for controllers and memory
# (Some of these are valid for many DaVinci family chips)
dict set dm365 sram0 0x00010000
dict set dm365 sram1 0x00014000
dict set dm365 sysbase 0x01c40000
dict set dm365 pllc1 0x01c40800
dict set dm365 pllc2 0x01c40c00
dict set dm365 psc 0x01c41000
dict set dm365 gpio 0x01c67000
dict set dm365 a_emif 0x01d10000
dict set dm365 a_emif_cs0 0x02000000
dict set dm365 a_emif_cs1 0x04000000
dict set dm365 ddr_emif 0x20000000
dict set dm365 ddr 0x80000000
source [find target/ti/davinci.cfg]
################
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
# and the ETB memory (4K) are other options, while trace is unused.
set _TARGETNAME $_CHIPNAME.arm
target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
# and that the work area is used only with a kernel mmu context ...
$_TARGETNAME configure \
-work-area-virt [expr {0xfffe0000 + 0x4000}] \
-work-area-phys [dict get $dm365 sram1] \
-work-area-size 0x4000 \
-work-area-backup 0
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
adapter speed 1500
$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
# trace setup
etm config $_TARGETNAME 16 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb

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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments DaVinci family: TMS320DM6446
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME dm6446
}
# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
# after JTAG reset until ICEpick is used to route them in.
set EMU01 "-disable"
# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
# needing any ICEpick interaction.
#set EMU01 "-enable"
source [find target/ti/icepick.cfg]
# Subsidiary TAP: unknown ... must enable via ICEpick
jtag newtap $_CHIPNAME unknown -irlen 8 -disable
jtag configure $_CHIPNAME.unknown -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
jtag configure $_CHIPNAME.dsp -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 2"
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID] } {
set _ETB_TAPID $ETB_TAPID
} else {
set _ETB_TAPID 0x2b900f0f
}
jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
if { [info exists CPU_TAPID] } {
set _CPU_TAPID $CPU_TAPID
} else {
set _CPU_TAPID 0x07926001
}
jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b70002f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
jtag configure $_CHIPNAME.jrc -event setup \
"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
################
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
# and the ETB memory (4K) are other options, while trace is unused.
# Little-endian; use the OpenOCD default.
set _TARGETNAME $_CHIPNAME.arm
target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
adapter speed 1500
$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
# trace setup
etm config $_TARGETNAME 16 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb

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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (C) 2011 by Karl Kurbjun
# Copyright (C) 2009 by David Brownell
#
# Utilities for TI ICEpick-C/D used in most TI SoCs
# Details about the ICEPick are available in the TRM for each SoC
# and http://processors.wiki.ti.com/index.php/ICEPICK
# create "constants"
proc CONST { key } {
array set constant {
# define ICEPick instructions
IR_BYPASS 0x00
IR_ROUTER 0x02
IR_CONNECT 0x07
IF_BYPASS 0x3F
}
return $constant($key)
}
# Instruction to connect to the icepick module
proc icepick_c_connect {jrc} {
# Send CONNECT instruction in IR state
irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE
# Send write and connect key
drscan $jrc 8 0x89 -endstate DRPAUSE
}
# Instruction to disconnect to the icepick module
proc icepick_c_disconnect {jrc} {
# Send CONNECT instruction in IR state
irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE
# Send write and connect key
drscan $jrc 8 0x86 -endstate DRPAUSE
}
#
# icepick_c_router:
# this function is for sending router commands
# arguments are:
# jrc: TAP name for the ICEpick
# rw: read/write (0 for read, 1 for write)
# block: icepick or DAP
# register: which register to read/write
# payload: value to read/write
# this function is for sending router commands
#
proc icepick_c_router {jrc rw block register payload} {
set new_dr_value \
[expr { ( ($rw & 0x1) << 31) | ( ($block & 0x7) << 28) | \
( ($register & 0xF) << 24) | ( $payload & 0xFFFFFF ) } ]
# echo "\tNew router value:\t0x[format %x $new_dr_value]"
# select router
irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE
# ROUTER instructions are 32 bits wide
set old_dr_value 0x[drscan $jrc 32 $new_dr_value -endstate DRPAUSE]
# echo "\tOld router value:\t0x[format %x $old_dr_value]"
}
# Configure the icepick control register
proc icepick_c_setup {jrc} {
# send a router write, block is 0, register is 1, value is 0x2100
icepick_c_router $jrc 1 0x0 0x1 0x001000
}
# jrc == TAP name for the ICEpick
# port == a port number, 0..15 for debug tap, 16..31 for test tap
proc icepick_c_tapenable {jrc port} {
if { ($port >= 0) && ($port < 16) } {
# Debug tap"
set tap $port
set block 0x2
} elseif { $port < 32 } {
# Test tap
set tap [expr {$port - 16}]
set block 0x1
} else {
echo "ERROR: Invalid ICEPick C port number: $port"
return
}
# First CONNECT to the ICEPick
# echo "Connecting to ICEPick"
icepick_c_connect $jrc
# echo "Configuring the ICEpick"
icepick_c_setup $jrc
# NOTE: it's important not to enter RUN/IDLE state until
# done sending these instructions and data to the ICEpick.
# And never to enter RESET, which will disable the TAPs.
# first enable power and clock for TAP
icepick_c_router $jrc 1 $block $tap 0x110048
# TRM states that the register should be read back here, skipped for now
# enable debug "default" mode
icepick_c_router $jrc 1 $block $tap 0x112048
# TRM states that debug enable and debug mode should be read back and
# confirmed - skipped for now
# Finally select the tap
icepick_c_router $jrc 1 $block $tap 0x112148
# Enter the bypass state
irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE
runtest 10
}
# jrc == TAP name for the ICEpick
# coreid== core id number 0..15 (not same as port number!)
proc icepick_d_set_core_control {jrc coreid value } {
icepick_c_router $jrc 1 0x6 $coreid $value
}
# jrc == TAP name for the ICEpick
# port == a port number, 0..15
# Follow the sequence described in
# http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf
proc icepick_d_tapenable {jrc port coreid { value 0x2008 } } {
# First CONNECT to the ICEPick
icepick_c_connect $jrc
icepick_c_setup $jrc
# Select the port
icepick_c_router $jrc 1 0x2 $port 0x2108
# Set icepick core control for $coreid
icepick_d_set_core_control $jrc $coreid $value
# Enter the bypass state
irscan $jrc [CONST IF_BYPASS] -endstate RUN/IDLE
runtest 10
}
# This function uses the ICEPick to send a warm system reset
proc icepick_c_wreset {jrc} {
# send a router write, block is 0, register is 1, value is 0x2100
icepick_c_router $jrc 1 0x0 0x1 0x002101
}

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# SPDX-License-Identifier: GPL-2.0-or-later
# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
#
# Texas Instruments K3 devices:
# * AM243: https://www.ti.com/lit/pdf/spruim2
# Has 4 R5 Cores, M4F and an M3
# * AM261: https://www.ti.com/lit/pdf/sprujb6
# Has 2 R5 Cores and an M4F
# * AM263: https://www.ti.com/lit/pdf/spruj17
# Has 4 R5 Cores and an M3
# * AM263P: https://www.ti.com/lit/pdf/spruj55
# Has 4 R5 Cores and an M4F
# * AM273: https://www.ti.com/lit/pdf/spruiu0
# Has 2 R5 Cores and an M3
# * AM625: https://www.ti.com/lit/pdf/spruiv7a
# Has 4 ARMV8 Cores and 1 R5 Core and an M4F
# * AM62A7: https://www.ti.com/lit/pdf/spruj16a
# Has 4 ARMV8 Cores and 2 R5 Cores
# * AM62P: https://www.ti.com/lit/pdf/spruj83
# Has 4 ARMV8 Cores and 2 R5 Cores
# * AM62L: https://www.ti.com/lit/pdf/sprujb4
# Has 2 ARMv8 Cores only
# * AM642: https://www.ti.com/lit/pdf/spruim2
# Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
# * AM654x: https://www.ti.com/lit/pdf/spruid7
# Has 4 ARMV8 Cores and 2 R5 Cores and an M3
# * J7200: https://www.ti.com/lit/pdf/spruiu1
# Has 2 ARMV8 Cores and 4 R5 Cores and an M3
# * J721E: https://www.ti.com/lit/pdf/spruil1
# Has 2 ARMV8 Cores and 6 R5 Cores and an M3
# * J721S2: https://www.ti.com/lit/pdf/spruj28
# Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
# * J722S: https://www.ti.com/lit/zip/sprujb3
# Has 4 ARMV8 Cores and 3 R5 Cores
# * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
# Has 8 ARMV8 Cores and 8 R5 Cores
#
source [find target/swj-dp.tcl]
if { [info exists SOC] } {
set _soc $SOC
} else {
set _soc am654
}
# set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
if { [info exists V8_SMP_DEBUG] } {
set _v8_smp_debug $V8_SMP_DEBUG
} else {
set _v8_smp_debug 0
}
# Common Definitions
# System Controller is the very first processor - all current SoCs have it.
set CM3_CTIBASE {0x3C016000}
# sysctrl power-ap unlock offsets
set _sysctrl_ap_unlock_offsets {0xf0 0x44}
set _sysctrl_ap_num 7
# All the ARMV8s are the next processors.
# CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
# And we add up the R5s
# (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
set _r5_ap_num 1
# Finally an General Purpose(GP) MCU
set CM4_CTIBASE {0x20001000}
# General Purpose MCU (M4) may be present on some very few SoCs
set _gp_mcu_cores 0
# General Purpose MCU power-ap unlock offsets
set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
# Generic mem-ap port number
set _mem_ap_num 2
# Generic AP_SEL PWR Register number
set _power_ap_num 3
# Generic SPREC RESET BANK and Field number
set _powerap_sprec_reset 0xf0
# Set configuration overrides for each SOC
switch $_soc {
am261 -
am263p -
am263 {
set _K3_DAP_TAPID 0x2bb7d02f
# Mem-ap port
set _mem_ap_num 6
# AM263 has 0 ARMV8 CPUs
set _armv8_cores 0
# AM263 has 2 cluster of 2 R5s cores.
set _r5_cores 4
set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000}
set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000}
set _r5_ap_num 5
set _power_ap_num 7
if { "$_soc" == "am263p" } {
set _K3_DAP_TAPID 0x1bb9502f
}
if { "$_soc" == "am261" } {
set _K3_DAP_TAPID 0x1bba602f
set _r5_cores 2
}
}
am273 {
set _K3_DAP_TAPID 0x1bb6a02f
# Mem-ap port
set _mem_ap_num 6
# system controller is on AP0
set _sysctrl_ap_num 0
# AM273 has 0 ARMV8 CPUs
set _armv8_cores 0
# AM273 has 1 cluster of 2 R5s cores.
set _r5_cores 2
set R5_NAMES {main0_r5.0 main0_r5.1}
set R5_DBGBASE {0x90030000 0x90032000}
set R5_CTIBASE {0x90038000 0x90039000}
set _r5_ap_num 5
}
am654 {
set _K3_DAP_TAPID 0x0bb5a02f
# AM654 has 2 clusters of 2 A53 cores each.
set _armv8_cpu_name a53
set _armv8_cores 4
# AM654 has 1 cluster of 2 R5s cores.
set _r5_cores 2
set R5_NAMES {mcu_r5.0 mcu_r5.1}
# Sysctrl power-ap unlock offsets
set _sysctrl_ap_unlock_offsets {0xf0 0x50}
}
am243 -
am642 {
set _K3_DAP_TAPID 0x0bb3802f
# AM642 has 1 clusters of 2 A53 cores each.
set _armv8_cpu_name a53
set _armv8_cores 2
set ARMV8_DBGBASE {0x90010000 0x90110000}
set ARMV8_CTIBASE {0x90020000 0x90120000}
# AM642 has 2 cluster of 2 R5s cores.
set _r5_cores 4
set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
# M4 processor
set _gp_mcu_cores 1
# Overrides for am243
if { "$_soc" == "am243" } {
# Uses the same JTAG ID
set _armv8_cores 0
}
# Setup DMEM access descriptions
# DAPBUS (Debugger) description
set _dmem_base_address 0x740002000
set _dmem_ap_address_offset 0x100
set _dmem_max_aps 10
# Emulated AP description
set _dmem_emu_base_address 0x760000000
set _dmem_emu_base_address_map_to 0x1d500000
set _dmem_emu_ap_list 1
}
am625 {
set _K3_DAP_TAPID 0x0bb7e02f
# AM625 has 1 clusters of 4 A53 cores.
set _armv8_cpu_name a53
set _armv8_cores 4
set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
# AM625 has 1 cluster of 1 R5s core.
set _r5_cores 1
set R5_NAMES {main0_r5.0}
set R5_DBGBASE {0x9d410000}
set R5_CTIBASE {0x9d418000}
# sysctrl CTI base
set CM3_CTIBASE {0x20001000}
# Sysctrl power-ap unlock offsets
set _sysctrl_ap_unlock_offsets {0xf0 0x78}
# M4 processor
set _gp_mcu_cores 1
set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
# Setup DMEM access descriptions
# DAPBUS (Debugger) description
set _dmem_base_address 0x740002000
set _dmem_ap_address_offset 0x100
set _dmem_max_aps 10
# Emulated AP description
set _dmem_emu_base_address 0x760000000
set _dmem_emu_base_address_map_to 0x1d500000
set _dmem_emu_ap_list 1
}
j722s -
am62p -
am62a7 {
set _K3_DAP_TAPID 0x0bb8d02f
# AM62a7/AM62P has 1 cluster of 4 A53 cores.
set _armv8_cpu_name a53
set _armv8_cores 4
set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
# AM62a7/AM62P has 2 cluster of 1 R5 core.
set _r5_cores 2
set R5_NAMES {main0_r5.0 mcu0_r5.0}
set R5_DBGBASE {0x9d410000 0x9d810000}
set R5_CTIBASE {0x9d418000 0x9d818000}
# sysctrl CTI base
set CM3_CTIBASE {0x20001000}
# Sysctrl power-ap unlock offsets
set _sysctrl_ap_unlock_offsets {0xf0 0x78}
# Setup DMEM access descriptions
# DAPBUS (Debugger) description
set _dmem_base_address 0x740002000
set _dmem_ap_address_offset 0x100
set _dmem_max_aps 10
# Emulated AP description
set _dmem_emu_base_address 0x760000000
set _dmem_emu_base_address_map_to 0x1d500000
set _dmem_emu_ap_list 1
# Overrides for am62p
if { "$_soc" == "am62p" } {
set _K3_DAP_TAPID 0x0bb9d02f
set R5_NAMES {wkup0_r5.0 mcu0_r5.0}
}
# Overrides for j722s
if { "$_soc" == "j722s" } {
set _K3_DAP_TAPID 0x0bba002f
set _r5_cores 3
set R5_NAMES {wkup0_r5.0 main0_r5.0 mcu0_r5.0}
set R5_DBGBASE {0x9d410000 0x9d510000 0x9d810000}
set R5_CTIBASE {0x9d418000 0x9d518000 0x9d818000}
}
}
am62l {
set _K3_DAP_TAPID 0x0bba702f
# AM62Lx has 1 cluster of 2 A53 cores.
set _armv8_cpu_name a53
set _armv8_cores 2
set ARMV8_DBGBASE {0x90010000 0x90110000}
set ARMV8_CTIBASE {0x90020000 0x90120000}
# Has no supporting microcontrollers
set _r5_cores 0
}
j721e {
set _K3_DAP_TAPID 0x0bb6402f
# J721E has 1 cluster of 2 A72 cores.
set _armv8_cpu_name a72
set _armv8_cores 2
# J721E has 3 clusters of 2 R5 cores each.
set _r5_cores 6
# Setup DMEM access descriptions
# DAPBUS (Debugger) description
set _dmem_base_address 0x4c40002000
set _dmem_ap_address_offset 0x100
set _dmem_max_aps 8
# Emulated AP description
set _dmem_emu_base_address 0x4c60000000
set _dmem_emu_base_address_map_to 0x1d600000
set _dmem_emu_ap_list 1
}
j7200 {
set _K3_DAP_TAPID 0x0bb6d02f
# J7200 has 1 cluster of 2 A72 cores.
set _armv8_cpu_name a72
set _armv8_cores 2
# J7200 has 2 clusters of 2 R5 cores each.
set _r5_cores 4
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
# M3 CTI base
set CM3_CTIBASE {0x20001000}
}
j721s2 {
set _K3_DAP_TAPID 0x0bb7502f
# J721s2 has 1 cluster of 2 A72 cores.
set _armv8_cpu_name a72
set _armv8_cores 2
# J721s2 has 3 clusters of 2 R5 cores each.
set _r5_cores 6
# sysctrl CTI base
set CM3_CTIBASE {0x20001000}
# Sysctrl power-ap unlock offsets
set _sysctrl_ap_unlock_offsets {0xf0 0x78}
# M4 processor
set _gp_mcu_cores 1
set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
}
j784s4 {
set _K3_DAP_TAPID 0x0bb8002f
# j784s4 has 2 cluster of 4 A72 cores each.
set _armv8_cpu_name a72
set _armv8_cores 8
set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000
0x90810000 0x90910000 0x90a10000 0x90b10000}
set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000
0x90820000 0x90920000 0x90a20000 0x90b20000}
# J784s4 has 4 clusters of 2 R5 cores each.
set _r5_cores 8
set R5_DBGBASE {0x9d010000 0x9d012000
0x9d410000 0x9d412000
0x9d510000 0x9d512000
0x9d610000 0x9d612000}
set R5_CTIBASE {0x9d018000 0x9d019000
0x9d418000 0x9d419000
0x9d518000 0x9d519000
0x9d618000 0x9d619000}
set R5_NAMES {mcu_r5.0 mcu_r5.1
main0_r5.0 main0_r5.1
main1_r5.0 main1_r5.1
main2_r5.0 main2_r5.1}
# Setup DMEM access descriptions
# DAPBUS (Debugger) description
set _dmem_base_address 0x4c40002000
set _dmem_ap_address_offset 0x100
set _dmem_max_aps 8
# Emulated AP description
set _dmem_emu_base_address 0x4c60000000
set _dmem_emu_base_address_map_to 0x1d600000
set _dmem_emu_ap_list 1
# sysctrl CTI base
set CM3_CTIBASE {0x20001000}
# Sysctrl power-ap unlock offsets
set _sysctrl_ap_unlock_offsets {0xf0 0x78}
}
default {
echo "'$_soc' is invalid!"
}
}
proc _get_rtos_type_for_cpu { target_name } {
if { [info exists ::RTOS($target_name)] } {
return $::RTOS($target_name)
}
return none
}
set _CHIPNAME $_soc
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
set _CTINAME $_CHIPNAME.cti
# sysctrl is always present
cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \
-ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0]
target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \
-ap-num $_sysctrl_ap_num -defer-examine \
-rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
$_TARGETNAME.sysctrl configure -event reset-assert { }
proc sysctrl_up {} {
# To access sysctrl, we need to enable the JTAG access for the same.
# Ensure Power-AP unlocked
$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
$::_TARGETNAME.sysctrl arp_examine
}
$_TARGETNAME.sysctrl configure -event gdb-attach {
sysctrl_up
# gdb-attach default rule
halt 1000
}
proc _cpu_no_smp_up {} {
set _current_target [target current]
set _current_type [$_current_target cget -type]
$_current_target arp_examine
$_current_target $_current_type dbginit
}
proc _armv8_smp_up {} {
for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
$::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
}
# Set Default target as core 0
targets $::_TARGETNAME.$::_armv8_cpu_name.0
}
set _v8_smp_targets ""
for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
-baseaddr [lindex $ARMV8_CTIBASE $_core]
target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]
set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
if { $_v8_smp_debug == 0 } {
$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
_cpu_no_smp_up
# gdb-attach default rule
halt 1000
}
} else {
$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
_armv8_smp_up
# gdb-attach default rule
halt 1000
}
}
}
if { $_armv8_cores > 0 } {
# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
set _armv8_up_cmd "$_armv8_cpu_name"_up
# Available if V8_SMP_DEBUG is set to non-zero value
set _armv8_smp_cmd "$_armv8_cpu_name"_smp
if { $_v8_smp_debug == 0 } {
proc $_armv8_up_cmd { args } {
foreach _core $args {
targets $_core
_cpu_no_smp_up
}
}
} else {
proc $_armv8_smp_cmd { args } {
_armv8_smp_up
}
# Declare SMP
target smp {*}$_v8_smp_targets
}
}
for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
set _r5_name [lindex $R5_NAMES $_core]
cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
-baseaddr [lindex $R5_CTIBASE $_core]
# inactive core examination will fail - wait till startup of additional core
target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
$_TARGETNAME.$_r5_name configure -event gdb-attach {
_cpu_no_smp_up
# gdb-attach default rule
halt 1000
}
}
proc r5_up { args } {
foreach _core $args {
targets $_core
_cpu_no_smp_up
}
}
if { $_gp_mcu_cores != 0 } {
cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
-rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
$_TARGETNAME.gp_mcu configure -event reset-assert { }
proc gp_mcu_up {} {
# To access GP MCU, we need to enable the JTAG access for the same.
# Ensure Power-AP unlocked
$::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
$::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
$::_TARGETNAME.gp_mcu arp_examine
}
$_TARGETNAME.gp_mcu configure -event gdb-attach {
gp_mcu_up
# gdb-attach default rule
halt 1000
}
}
# In case of DMEM access, configure the dmem adapter with offsets from above.
if { 0 == [string compare [adapter name] dmem ] } {
if { [info exists _dmem_base_address] } {
# DAPBUS (Debugger) description
dmem base_address $_dmem_base_address
dmem ap_address_offset $_dmem_ap_address_offset
dmem max_aps $_dmem_max_aps
# The following are the details of APs to be emulated for direct address access.
# Debug Config (Debugger) description
dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to
dmem emu_ap_list $_dmem_emu_ap_list
# We are going local bus, so speed is really dummy here.
adapter speed 2500
} else {
puts "ERROR: ${SOC} data is missing to support dmem access!"
}
} else {
# AXI AP access port for SoC address map
target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num
}
# Reset system using (Debug Reset) SPREC Register,SYSTEMRESET bit field via apreg
proc dbg_sys_reset {} {
$::_CHIPNAME.dap apreg $::_power_ap_num $::_powerap_sprec_reset 0x1
}
add_help_text dbg_sys_reset "Debugger initiated system reset attempt via Power-AP"

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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments MSP432 - ARM Cortex-M4F @ up to 48 MHz
#
# http://www.ti.com/MSP432
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME msp432
}
if { [info exists CPUTAPID] } {
set _DAP_TAPID $CPUTAPID
} else {
set _DAP_TAPID 0x4ba00477
}
if { [info exists DAP_SWD_ID] } {
set _DAP_SWD_ID $DAP_SWD_ID
} else {
set _DAP_SWD_ID 0x2ba01477
}
source [find target/swj-dp.tcl]
if { [using_jtag] } {
set _DAP_ID $_DAP_TAPID
} else {
set _DAP_ID $_DAP_SWD_ID
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x4000
}
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
cortex_m reset_config sysresetreq

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# SPDX-License-Identifier: GPL-2.0-or-later
# Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/
#
# Texas Instruments MSPM0L/G - ARM Cortex-M0 @ 32MHz
# https://www.ti.com/microcontrollers-mcus-processors/arm-based-microcontrollers/arm-cortex-m0-mcus/overview.html
#
source [find bitsbytes.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
# Meant to work with MSPM0L and MSPM0G class of devices.
set _CHIPNAME mspm0x
}
if { [info exists CPUTAPID] } {
set _DAP_TAPID $CPUTAPID
} else {
set _DAP_TAPID 0x4ba00477
}
if { [info exists DAP_SWD_ID] } {
set _DAP_SWD_ID $DAP_SWD_ID
} else {
set _DAP_SWD_ID 0x2ba01477
}
source [find target/swj-dp.tcl]
# MSPM0 only supports swd, so set it here and save a line for custom boards
transport select swd
set _DAP_ID $_DAP_SWD_ID
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
if { [info exists WORKAREABASE] } {
set _WORKAREABASE $WORKAREABASE
} else {
set _WORKAREABASE 0x20000000
}
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
# Smallest SRAM size is 1K SRAM.
set _WORKAREASIZE 0x400
}
#
# MSPM0 Debug SubSystem Mailbox (DSSM) Communication helpers
#
proc _mspm0_wait_for_dssm_response {command} {
# Wait for SECAP::RCR rx_valid to be set
set timeout 1000
while { [expr { [$::_CHIPNAME.dap apreg 2 0xc] & 0x1}] != 0x1 } {
sleep 1
set timeout [expr {$timeout - 1}]
if { $timeout == 0 } {
set rcr [$::_CHIPNAME.dap apreg 2 0xc]
return -code error [format "MSPM0 SECAP RCR=0x%08x timeout rx_valid" $rcr]
}
}
# Read SECAP::RXD to clear the RX_VALID bit
set rxd [$::_CHIPNAME.dap apreg 2 0x8]
# Read SECAP::RCR
set rcr [$::_CHIPNAME.dap apreg 2 0xc]
# Check if we got successful response. This is denoted as:
# 8 LSBits of $command should matchup with SECAP::RCR
# and
# SECAP::RXD should be 0x10003
if { ([expr { $command & 0xff}] == $rcr) && ($rxd == 0x10003) } {
return 0
}
# Provide some debug log for users to report back if CMD fails.
return -code error [format "MSPM0 SECAP CMD FAIL! RXD: 0x%08X RCR: 0x%08X" $rxd $rcr]
}
proc _mspm0_dssm_command {command} {
# SECAP::TCR = command
$::_CHIPNAME.dap apreg 2 0x4 $command
# SECAP::TDR = 0x0
$::_CHIPNAME.dap apreg 2 0x0 0x0
# Read SECAP::RCR and RXD to clear up any prev pending reads
set rxd [$::_CHIPNAME.dap apreg 2 0x8]
set rcr [$::_CHIPNAME.dap apreg 2 0xc]
# Make sure everything is synced
sleep 1000
# Trigger nRST
mspm0_board_reset
# Wait for ROM to do it's magic and respond back
set res [_mspm0_wait_for_dssm_response $command]
if { $res } {
return $res
}
# Paranoid.. make sure ROM does what it is meant to do
# RX valid should have been cleared after the operation is
# complete
sleep 1000
# Trigger nRST to get back to sane system
mspm0_board_reset
sleep 1000
return 0
}
# NOTE: Password authentication scheme is NOT supported atm.
# mspm0_factory_reset: Factory reset the board
proc mspm0_factory_reset {} {
set res [_mspm0_dssm_command 0x020a]
if { $res } {
echo "Factory Reset failed!"
} else {
echo "Factory reset success! Halting processor"
# We need to halt the processor else the WDT fires!
halt
}
return $res
}
add_help_text mspm0_factory_reset "Force Factory reset to recover 'bricked' board"
# NOTE: Password authentication scheme is NOT supported atm.
# mspm0_mass_erase: Mass erase flash
proc mspm0_mass_erase {} {
set res [_mspm0_dssm_command 0x020c]
if { $res } {
echo "Mass Erase failed!"
} else {
echo "Mass Erase success! Halting Processor"
# We need to halt the processor else the WDT fires!
halt
}
return $res
}
add_help_text mspm0_mass_erase "Mass erase flash"
# mspm0_start_bootloader: Ask explicitly for bootloader startup
proc mspm0_start_bootloader {} {
set res [_mspm0_dssm_command 0x0108]
if { $res } {
echo "Start BL failed!"
}
return $res
}
add_help_text mspm0_start_bootloader "Ask explicitly for bootloader startup"
# MSPM0 requires board level NRST reset to be toggled for
# Factory reset operations to function.
# However this cannot be the default configuration as this
# prevents reset init reset halt to function properly
# since the Debug Subsystem (debugss) logic or coresight
# seems impacted by nRST.
# This can be overridden in board file as required.
#
# mspm0_board_reset: Board level reset
proc mspm0_board_reset {} {
set user_reset_config [reset_config]
reset_config srst_only
set errno [catch {reset}]
eval reset_config $user_reset_config
if {$errno} {error}
}
add_help_text mspm0_board_reset "Request a board level reset"
# If the flash is empty or the device is already in low-power state, then
# debug access is not available. to handle this, explicitly control power ap
# to provide access. Refer to Technical Reference Manual for further info.
proc _mspm0_enable_low_power_mode { } {
# PWR_AP::DPREC <= FRCACT(3)=1, RST_CTL(14:16)=1, IHIB_SLP(20)=1
$::_CHIPNAME.dap apreg 4 0x00 0x104008
# PWR_AP::SPREC <= SYSRST=1
$::_CHIPNAME.dap apreg 4 0xF0 0x01
# PWR_AP::DPREC <= FRCACT(3)=1, IHIB_SLP(20)=1
$::_CHIPNAME.dap apreg 4 0x00 0x100008
}
$_TARGETNAME configure -event examine-start { _mspm0_enable_low_power_mode }
$_TARGETNAME configure -work-area-phys $_WORKAREABASE -work-area-size $_WORKAREASIZE -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME.main mspm0 0 0 0 0 $_TARGETNAME
flash bank $_FLASHNAME.nonmain mspm0 0x41c00000 0 0 0 $_TARGETNAME
flash bank $_FLASHNAME.data mspm0 0x41d00000 0 0 0 $_TARGETNAME
cortex_m reset_config sysresetreq

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# SPDX-License-Identifier: GPL-2.0-or-later
# Texas Instruments OMAP 2420
# http://www.ti.com/omap
# as seen in Nokia N8x0 tablets
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME omap2420
}
# NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
reset_config srst_nogate
# Subsidiary TAP: ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6).
jtag newtap $_CHIPNAME iva -irlen 4 -disable
# Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2).
jtag newtap $_CHIPNAME dsp -irlen 38 -disable
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID] } {
set _ETB_TAPID $ETB_TAPID
} else {
set _ETB_TAPID 0x2b900f0f
}
jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID
# Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
if { [info exists CPU_TAPID] } {
set _CPU_TAPID $CPU_TAPID
} else {
set _CPU_TAPID 0x07b3602f
}
jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
# Primary TAP: ICEpick-B (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x01ce4801
}
jtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID
# GDB target: the ARM.
set _TARGETNAME $_CHIPNAME.arm
target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
# scratch: framebuffer, may be initially unavailable in some chips
$_TARGETNAME configure -work-area-phys 0x40210000
$_TARGETNAME configure -work-area-size 0x00081000
$_TARGETNAME configure -work-area-backup 0
# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
etm config $_TARGETNAME 16 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb
# RM_RSTCTRL_WKUP.RST.GS - Trigger a global software reset, and
# give it a chance to finish before we talk to the chip again.
set RM_RSTCTRL_WKUP 0x48008450
$_TARGETNAME configure -event reset-assert \
"halt; $_TARGETNAME mww $RM_RSTCTRL_WKUP 2; sleep 200"

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# SPDX-License-Identifier: GPL-2.0-or-later
# TI OMAP3530
# http://focus.ti.com/docs/prod/folders/print/omap3530.html
# Other OMAP3 chips remove DSP and/or the OpenGL support
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME omap3530
}
# ICEpick-C ... used to route Cortex, DSP, and more not shown here
source [find target/ti/icepick.cfg]
# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
# Subsidiary TAP: CoreSight Debug Access Port (DAP)
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x0b6d602f
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.cpu -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b7ae02f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID
# GDB target: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
# SRAM: 64K at 0x4020.0000; use the first 16K
$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
###################
# the reset sequence is event-driven
# and kind of finicky...
# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
# have the DAP "always" be active
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
proc omap3_dbginit {target} {
# General Cortex-A8 debug initialisation
cortex_a dbginit
# Enable DBGU signal for OMAP353x
$target mww phys 0x5401d030 0x00002000
}
# be absolutely certain the JTAG clock will work with the worst-case
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
# OK to speed up *after* PLL and clock tree setup.
adapter speed 1000
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
# would issue. RST_DPLL3 (4) is a cold reset.
set PRM_RSTCTRL 0x48307250
$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"

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# SPDX-License-Identifier: GPL-2.0-or-later
# OMAP4430
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME omap4430
}
# Although the OMAP4430 supposedly has an ICEpick-D, only the
# ICEpick-C router commands seem to work.
# See http://processors.wiki.ti.com/index.php/ICEPICK
source [find target/ti/icepick.cfg]
#
# A9 DAP
#
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x3BA00477
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.cpu -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 9"
#
# M3 DAPs, one per core
#
if { [info exists M3_DAP_TAPID] } {
set _M3_DAP_TAPID $M3_DAP_TAPID
} else {
set _M3_DAP_TAPID 0x4BA00477
}
jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m31 -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 5"
jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m30 -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 4"
#
# ICEpick-D JRC (JTAG route controller)
#
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x3b95c02f
set _JRC_TAPID2 0x1b85202f
}
# PandaBoard REV EA1 (PEAP platforms)
if { [info exists JRC_TAPID2] } {
set _JRC_TAPID2 $JRC_TAPID2
} else {
set _JRC_TAPID2 0x1b85202f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
# Required by ICEpick to power-up the debug domain
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
#
# GDB target: Cortex-A9, using DAP
#
# The debugger can connect to either core of the A9, but currently
# not both simultaneously. Change -coreid to 1 to connect to the
# second core.
#
set _TARGETNAME $_CHIPNAME.cpu
# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
# 0x80000000 is cpu0 coresight region
#
#
# CORTEX_A8_PADDRDBG_CPU_SHIFT 13
# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
set _coreid 0
set _dbgbase [expr {0x80000000 | ($_coreid << 13)}]
echo "Using dbgbase = [format 0x%x $_dbgbase]"
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase $_dbgbase
# SRAM: 56KiB at 0x4030.0000
$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
#
# M3 targets, separate TAP/DAP for each core
#
dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
# Once the JRC is up, enable our TAPs
jtag configure $_CHIPNAME.jrc -event setup "
jtag tapenable $_CHIPNAME.cpu
jtag tapenable $_CHIPNAME.m30
jtag tapenable $_CHIPNAME.m31
"
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset.
set PRM_RSTCTRL 0x4A307B00
$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
$_CHIPNAME.m30 configure -event reset-assert { }
$_CHIPNAME.m31 configure -event reset-assert { }
# Soft breakpoints don't currently work due to broken cache handling
gdb breakpoint_override hard

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# SPDX-License-Identifier: GPL-2.0-or-later
# OMAP4460
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME omap4460
}
# Although the OMAP4430 supposedly has an ICEpick-D, only the
# ICEpick-C router commands seem to work.
# See http://processors.wiki.ti.com/index.php/ICEPICK
source [find target/ti/icepick.cfg]
#
# A9 DAP
#
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x3BA00477
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.cpu -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 9"
#
# M3 DAPs, one per core
#
if { [info exists M3_DAP_TAPID] } {
set _M3_DAP_TAPID $M3_DAP_TAPID
} else {
set _M3_DAP_TAPID 0x4BA00477
}
jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m31 -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 5"
jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m30 -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 4"
#
# ICEpick-D JRC (JTAG route controller)
#
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x2b94e02f
set _JRC_TAPID2 0x1b85202f
}
# PandaBoard REV EA1 (PEAP platforms)
if { [info exists JRC_TAPID2] } {
set _JRC_TAPID2 $JRC_TAPID2
} else {
set _JRC_TAPID2 0x1b85202f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
# Required by ICEpick to power-up the debug domain
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
#
# GDB target: Cortex-A9, using DAP
#
# The debugger can connect to either core of the A9, but currently
# not both simultaneously. Change -coreid to 1 to connect to the
# second core.
#
set _TARGETNAME $_CHIPNAME.cpu
# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
# 0x80000000 is cpu0 coresight region
#
#
# CORTEX_A8_PADDRDBG_CPU_SHIFT 13
# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
set _coreid 0
set _dbgbase [expr {0x80000000 | ($_coreid << 13)}]
echo "Using dbgbase = [format 0x%x $_dbgbase]"
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase $_dbgbase
# SRAM: 56KiB at 0x4030.0000
$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
#
# M3 targets, separate TAP/DAP for each core
#
dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
# Once the JRC is up, enable our TAPs
jtag configure $_CHIPNAME.jrc -event setup "
jtag tapenable $_CHIPNAME.cpu
jtag tapenable $_CHIPNAME.m30
jtag tapenable $_CHIPNAME.m31
"
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset.
set PRM_RSTCTRL 0x4A307B00
$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
$_CHIPNAME.m30 configure -event reset-assert { }
$_CHIPNAME.m31 configure -event reset-assert { }
# Soft breakpoints don't currently work due to broken cache handling
gdb breakpoint_override hard

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# SPDX-License-Identifier: GPL-2.0-or-later
# TI OMAP5912 dual core processor
# http://focus.ti.com/docs/prod/folders/print/omap5912.html
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME omap5912
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
# NOTE: validated with XOMAP5912 part
set _CPUTAPID 0x0692602f
}
adapter srst delay 100
# NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for
# its standalone siblings (like TMS320VC5502) of the same era
#jtag scan chain
jtag newtap $_CHIPNAME dsp -irlen 38 -expected-id 0x03df1d81
jtag newtap $_CHIPNAME arm -irlen 4 -expected-id $_CPUTAPID
jtag newtap $_CHIPNAME unknown -irlen 8
set _TARGETNAME $_CHIPNAME.arm
target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
proc omap5912_reset {} {
#
# halt target
#
poll
sleep 1
halt
wait_halt
#
# disable wdt
#
mww 0xfffec808 0x000000f5
mww 0xfffec808 0x000000a0
mww 0xfffeb048 0x0000aaaa
sleep 500
mww 0xfffeb048 0x00005555
sleep 500
}
# omap5912 lcd frame buffer as working area
$_TARGETNAME configure -work-area-phys 0x20000000 \
-work-area-size 0x3e800 -work-area-backup 0

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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments DaVinci family: OMAPL138
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME omapl138
}
source [find target/ti/icepick.cfg]
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID] } {
set _ETB_TAPID $ETB_TAPID
} else {
set _ETB_TAPID 0x2b900f0f
}
jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID -disable
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
if { [info exists CPU_TAPID] } {
set _CPU_TAPID $CPU_TAPID
} else {
set _CPU_TAPID 0x07926001
}
jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID -disable
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 2"
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b7d102f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
jtag configure $_CHIPNAME.jrc -event setup \
"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
################
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
# and the ETB memory (4K) are other options, while trace is unused.
# Little-endian; use the OpenOCD default.
set _TARGETNAME $_CHIPNAME.arm
target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
adapter speed 1500
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
# trace setup
etm config $_TARGETNAME 16 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb
gdb breakpoint_override hard
arm7_9 dbgrq enable

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# SPDX-License-Identifier: GPL-2.0-or-later
source [find target/ti/tms570.cfg]

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# SPDX-License-Identifier: GPL-2.0-or-later
# TI/Luminary Stellaris LM3S chip family
# Some devices have errata in returning their device class.
# DEVICECLASS is provided as a manual override
# Manual setting of a device class of 0xff is not allowed
global _DEVICECLASS
if { [info exists DEVICECLASS] } {
set _DEVICECLASS $DEVICECLASS
} else {
set _DEVICECLASS 0xff
}
# Luminary chips support both JTAG and SWD transports.
# Adapt based on what transport is active.
source [find target/swj-dp.tcl]
# For now we ignore the SPI and UART options, which
# are usable only for ISP style initial flash programming.
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lm3s
}
# CPU TAP ID 0x1ba00477 for early Sandstorm parts
# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
# CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
# ... we'll ignore the JTAG version field, rather than list every
# chip revision that turns up.
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x0ba00477
}
# SWD DAP, and JTAG TAP, take same params for now;
# ... even though SWD ignores all except TAPID, and
# JTAG shouldn't need anything more then irlen. (and TAPID).
swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
-expected-id $_CPUTAPID -ignore-version
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
# default to 2K working area
set _WORKAREASIZE 0x800
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
# 8K working area at base of ram, not backed up
#
# NOTE: you may need or want to reconfigure the work area;
# some parts have just 6K, and you may want to use other
# addresses (at end of mem not beginning) or back it up.
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
# JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
# LM3S parts don't support RTCK
#
# NOTE: this may be increased by a reset-init handler, after it
# configures and enables the PLL. Or you might need to decrease
# this, if you're using a slower clock.
adapter speed 500
source [find mem_helper.tcl]
proc reset_peripherals {family} {
source [find chip/ti/lm3s/lm3s.tcl]
echo "Resetting Core Peripherals"
# Disable the PLL and the system clock divider (nop if disabled)
mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV
mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
# RCC and RCC2 to their reset values
mww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}]
mww $SYSCTL_RCC2 0x07806810
mww $SYSCTL_RCC 0x078e3ad1
# Reset the deep sleep clock configuration register
mww $SYSCTL_DSLPCLKCFG 0x07800000
# Reset the clock gating registers
mww $SYSCTL_RCGC0 0x00000040
mww $SYSCTL_RCGC1 0
mww $SYSCTL_RCGC2 0
mww $SYSCTL_SCGC0 0x00000040
mww $SYSCTL_SCGC1 0
mww $SYSCTL_SCGC2 0
mww $SYSCTL_DCGC0 0x00000040
mww $SYSCTL_DCGC1 0
mww $SYSCTL_DCGC2 0
# Reset the remaining SysCtl registers
mww $SYSCTL_PBORCTL 0
mww $SYSCTL_IMC 0
mww $SYSCTL_GPIOHBCTL 0
mww $SYSCTL_MOSCCTL 0
mww $SYSCTL_PIOSCCAL 0
mww $SYSCTL_I2SMCLKCFG 0
# Reset the peripherals
mww $SYSCTL_SRCR0 0xffffffff
mww $SYSCTL_SRCR1 0xffffffff
mww $SYSCTL_SRCR2 0xffffffff
mww $SYSCTL_SRCR0 0
mww $SYSCTL_SRCR1 0
mww $SYSCTL_SRCR2 0
# Clear any pending SysCtl interrupts
mww $SYSCTL_MISC 0xffffffff
# Wait for any pending flash operations to complete
while {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 }
while {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 }
# Reset the flash controller registers
mww $FLASH_FMA 0
mww $FLASH_FCIM 0
mww $FLASH_FCMISC 0xffffffff
mww $FLASH_FWBVAL 0
}
$_TARGETNAME configure -event reset-start {
adapter speed 500
#
# When nRST is asserted on most Stellaris devices, it clears some of
# the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
# and OpenOCD depends on those TRMs. So we won't use SRST on those
# chips. (Only power-on reset should affect debug state, beyond a
# few specified bits; not the chip's nRST input, wired to SRST.)
#
# REVISIT current errata specs don't seem to cover this issue.
# Do we have more details than this email?
# https://lists.berlios.de/pipermail
# /openocd-development/2008-August/003065.html
#
global _DEVICECLASS
if {$_DEVICECLASS != 0xff} {
set device_class $_DEVICECLASS
} else {
set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}]
}
if {$device_class == 0 || $device_class == 1 ||
$device_class == 3 || $device_class == 5 || $device_class == 0xa} {
if {![using_hla]} {
# Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ
cortex_m reset_config sysresetreq
}
} else {
if {![using_hla]} {
# Tempest and Firestorm default to using NVIC VECTRESET
# peripherals will need resetting manually, see proc reset_peripherals
cortex_m reset_config vectreset
}
# reset peripherals, based on code in
# http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
reset_peripherals $device_class
}
}
# flash configuration ... autodetects sizes, autoprobed
flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME

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# SPDX-License-Identifier: GPL-2.0-or-later
adapter speed 1500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME tms570
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN big
}
# TMS570 has an ICEpick-C on which we need the router commands.
source [find target/ti/icepick.cfg]
# Main DAP
# DAP_TAPID should be set before source-ing this file
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -ignore-version
jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
# ICEpick-C (JTAG route controller)
# JRC_TAPID should be set before source-ing this file
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
}
set _JRC_TAPID2 0x0B7B302F
set _JRC_TAPID3 0x0B95502F
set _JRC_TAPID4 0x0B97102F
set _JRC_TAPID5 0x0D8A002F
set _JRC_TAPID6 0x0B8A002F
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID \
-expected-id $_JRC_TAPID2 \
-expected-id $_JRC_TAPID3 \
-expected-id $_JRC_TAPID4 \
-expected-id $_JRC_TAPID5 \
-expected-id $_JRC_TAPID6 \
-ignore-version
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
# Cortex-R4 target
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000
# TMS570 uses quirky BE-32 mode
$_CHIPNAME.dap ti_be_32_quirks 1
$_TARGETNAME configure -event "reset-assert" {
global _CHIPNAME
# assert warm system reset through ICEPick
icepick_c_wreset $_CHIPNAME.jrc
}

6
tcl/target/ti/tms570lc43xx.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
set DAP_TAPID 0x0B95A02F
set JRC_TAPID 0x0B95A02F
source [find target/ti/tms570.cfg]

8
tcl/target/ti/tms570ls1x.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# TMS570LS1114, TMS570LS1115
# TMS570LS1224, TMS570LS1225, TMS570LS1227
set DAP_TAPID 0x0B95502F
set JRC_TAPID 0x0B95502F
source [find target/ti/tms570.cfg]

8
tcl/target/ti/tms570ls20xxx.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# TMS570LS20216, TMS570LS20206, TMS570LS10216
# TMS570LS10206, TMS570LS10116, TMS570LS10106
set DAP_TAPID 0x0B7B302F
set JRC_TAPID 0x0B7B302F
source [find target/ti/tms570.cfg]

7
tcl/target/ti/tms570ls3137.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# TMS570LS3137
set DAP_TAPID 0x0B8A002F
set JRC_TAPID 0x0B8A002F
source [find target/ti/tms570.cfg]