There are two allocated fields that are never freed,
contiguous_regs_desc and contiguous_regs_list.
Additionally, prevent memory leaks and invalid accesses
when xtregs command is called repeatedly.
Change-Id: Id6ab4a2565ddb19e1e9d3f1c3b822182b3a6fb9d
Signed-off-by: Samuel Obuch <samuel.obuch@espressif.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9113
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst+cdns@cadence.com>
The current code for cortex_a watchpoint sets the field DBGWCR:LSC
to '3', that corresponds to 'access' watchpoint.
Thus, any 'r' or 'w' watchpoint is considered to 'a'.
Convert the enum watchpoint_rw to the corresponding values for the
field DBGWCR:LSC.
Change-Id: Iccfddb3e34f3f26927983f3b00d9d5f81b06eb21
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9291
Tested-by: jenkins
aarch64_resume() set the last_run_control_op on the current core
only and left last_run_control_op as is on the rest of the SMP group.
It caused semihosting call on other cores to stop because
last_run_control_op sticked on ARMV8_RUNCONTROL_STEP
Set last_run_control_op to ARMV8_RUNCONTROL_RESUME on all cores
in the SMP group.
Change-Id: I55a97bb1f7ea25bfc5937c3cc846532cdf390064
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9247
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Semihosting worked only on the first/gdb assigned core of a SMP group.
If a semihosting call was issued on another core, aarch64_update_halt_gdb()
emitted 'halted' event on core0 before semihosting decoding started.
Use target's smp_halt_event_postponed flag to keep events from emitting
until semihosting is decoded. If a semihosting call is confirmed,
clear flags and do not send 'halted' event for any core of SMP group.
Change-Id: Ie7eff7e493c2a4df3039f49fce1744d996050a59
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9246
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
update_halt_gdb() called aarch64_poll() recursively with temporary
switching target's smp flag off to prevent deeper recursion.
This was not possible for gdb assigned target or hwthread failed
with "SMP node change, disconnect GDB from core/thread".
Therefore the aarch64_poll(gdb_target) resulted in the useless
recursion back to update_halt_gdb().
Introduce aarch64_poll_smp() with smp parameter to avoid
update_halt_gdb() recursion properly and without fiddling
with target's smp flags.
While on it, add 'aarch64_' prefix to update_halt_gdb() function.
Change-Id: I645166f50c106f4a6d4d35dc70ad49041d2442aa
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9245
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Allow memory access as soon as debug_ap is initiated.
This resolves chicken - egg problem in cortex_m_examine():
examined flag had to be set at the start of examination
to allow memory access during examination.
hla_target has memory ready to access as soon as the adapter
is initialized so we can simply return true.
Change-Id: I30b8bcb8c43775ebbd8e677da09189781bebb4ab
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9179
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Use the new test in target memory access functions
instead of target_was_examined()
Drop the test from target_read/write_u8/16/32/64() helpers
as they directly call a memory access function which does
the test again.
Change-Id: Ic1753e461d2a4b91ce3a3e1bf3e86eb2be743d46
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9178
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
GDB uses this mark when creating a dummy frame for
manual call of a function by GDB command.
With the original setting of all registers as caller_save = true
GDB inferior call fails in EL2H mode with the message
Could not fetch register "ELR_EL3"; remote failure reply '0E'
It also fails similarly in EL0 and EL1 modes.
A standard function should not change EL banked registers anyway.
Avoid marking ELx banked registers as save-restore.
Treat pauth_dmask and pauth_cmask registers similarly.
They are not typically changed in a function.
Change-Id: Ibaf32210f3fcfa9dfb15e924b888243460e85fb4
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9243
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Currently, 'riscv exec_progbuf' command does not select active target.
So with multiple harts with a common debug module, program buffer may
be executed on an incorrect target.
Change-Id: Ic345b09b039c2b1e37e5b99a8534833ac2723277
Signed-off-by: Samuel Obuch <samuel.obuch@espressif.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9312
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Commit d7142a5727 ("target/target: Check checksum_memory
before call") added the error return if target's checksum_memory()
method is not implemented however the slow path with read buffer and
image_calculate_checksum() should be used instead.
Also the code fragment commented as /* convert to target endianness */
is a pure nonsense - it does not convert anything. Drop the conversion
loop.
Change-Id: I804605d31310698445b3ffb5e3fcad1fc43a5579
Suggested-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9242
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Tested-by: jenkins
The GD32VF103 has a perculiar reset procedure that does not fully comply
with the RISC-V Debug Specification.
Move the workaroung to the `deassert-reset-post` handler.
Change-Id: I153c866a5b7e2dff2552cc92772ce6ed77ad606b
Signed-off-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9314
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
The arithmetic addition of the returned error codes was used
as a lazy man's logical or.
Handle error passing properly.
Change-Id: I05f6d575dd7acb49cc3b3ca20b0e0b1f37d77ffe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9269
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The esirisc_trace.c uses macro BIT_MASK(), same name as a macro
from helper/bits.h
Drop the macro definition and use GENMASK() instead.
Change-Id: I0cc6a58e5aff3f48fa9a79a99bd28124f334c4e2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9168
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
On Cortex-M7 only, several registers in System Control Space (SCS)
are not accessible when the CPU is under reset, generating a bus
error.
This causes OpenOCD to fail examining the CPU when the board reset
button is pressed or when the flag 'connect_assert_srst' is used
on 'reset_config' command.
Introduce a deferred identification of the cache and run it during
polling and at target halted (just in case of polling disabled).
Change-Id: Ia5c582ae95f825c5fb8c2dcfb320142f7ac04a9f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9232
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
In a SMP configuration 'resumed' event was emitted only for
the active core, in contradiction to 'halted' event, which
gets emitted for all cores from the SMP group:
> resume
target event 3 (resume-start) for core stm32mp15x.cpu0
target event 2 (resumed) for core stm32mp15x.cpu0
target event 4 (resume-end) for core stm32mp15x.cpu0
target event 7 (gdb-start) for core stm32mp15x.cpu0
> halt
target event 0 (gdb-halt) for core stm32mp15x.cpu1
target event 1 (halted) for core stm32mp15x.cpu1
target event 0 (gdb-halt) for core stm32mp15x.cpu0
target event 1 (halted) for core stm32mp15x.cpu0
target event 8 (gdb-end) for core stm32mp15x.cpu0
Emit 'resumed' event in cortex_a_restore_smp().
While on it replace adding the returned errors together
with the proper error handling.
Change-Id: I9debef0884519cde767707f78f163b136ecc7aa5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9244
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Gdb uses length 3 to set breakpoint on a 4 byte Thumb-2
instruction. Without this patch a breakpoint on down aligned word
address was set. If the requested address was not word aligned,
the breakpoint triggered at previous instruction and was not
recognised properly by gdb.
Set breakpoint on whole word if aligns with requested address,
otherwise use length 2 and set byte mask.
Change-Id: I12d1c57b7154e64abdf23dd7cd31714f9d8ec6f0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9211
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Some targets have no means to find out which watchpoint triggered
the debug halt. Resolve properly the trivial and most used case
when only one watchpoint is set.
Change-Id: I683933ec43e6ca0fed84a08a2aa222ed8a6e277f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9210
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Resolve two problems that occurred when working with semihosting service
through multiple connection cycles (connect-disconnect-reconnect):
1) Double free:
When the same service handles multiple connections sequentially,
the same memory gets freed repeatedly, because function
'semihosting_service_connection_closed_handler()' incorrectly frees
service->priv->name on every connection closure.
2) Memory leak:
Function 'free_services()' misses service->priv->name cleanup for
semihosting redirection. Memory remains allocated after service
destruction.
The solution introduces a new 'dtor()' field in the service structure
that is called exactly once during free_service() execution.
To reproduce the issue, you can do the following:
1. openocd -f target.cfg -c init -c 'arm semihosting enable' -c
'arm semihosting_redirect tcp 4445'
# in another terminal
2. nc localhost 4445
3. Ctr+C
4. nc localhost 4445
5. Ctr+C
Change-Id: I0dc8021cc3e21c5af619c71a1821a1afe9bffe78
Signed-off-by: Kulyatskaya Alexandra <a.kulyatskaya@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9196
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
on ARMv6M variants (mainly Cortex-M0 and Cortex-M0+) and
on ARMv8M baseline (e.g.Cortex-M23). The devices do not have
BASEPRI and FAULTMASK functionally implemented and the corresponding
register bits are just read as zero, write ignored.
ARMv6-M Architecture Reference Manual:
Table D3-2 Programmers’ model feature comparison
Reduced exception priority management: PRIMASK
special-purpose register. No support for changing the
priority of configurable exceptions when they are active.
Armv8-M Architecture Reference Manual:
B3.32 Special-purpose mask registers, PRIMASK, BASEPRI, FAULTMASK,
for configurable priority boosting
A PE without the Main Extension implements PRIMASK, but does not
implement FAULTMASK and BASEPRI.
Change-Id: I332cc79718852c0109148817a214a2657960370b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9174
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Some link if not anymore accessible.
Replace them with current one and add a backup in case one gets
not accessible anymore.
Change-Id: Iffca714555e94e5322a5daac1ea756e36bbd3a8f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9188
Tested-by: jenkins
Commit 4afa32ece1 ("aarch64: unify armv7-a and armv8
debug entry decoding")
probably unintentionally removed DSCR_ENTRY_VECT_CATCH from
reported debug entry reasons. Note the discrepancy between
'case DSCR_ENTRY_BKPT_INSTR:' and its comment.
Hitting vector catch was reported as DBG_REASON_UNDEFINED.
DBG_REASON_UNDEFINED disturbed hwthread/gdb cooperation and
gdb reported the wrong thread as stopped by SIGTRAP.
Revert to the original functionality and report vector
catch as a breakpoint.
Change-Id: I12e938182cff8f633decba340000cfbb7b112ae3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9209
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
gdb uses this mark when creating a dummy frame for
manual call of a function by gdb command.
With the original setting all registers as caller_save = false
call command in gdb always clobbers r0, r1 and pc
and some other registers depending on the called function.
Set 'save-restore' for all registers but banked ones.
Change-Id: I16c49e4bf8001e38d18ce8861ca65988b08ccc88
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9208
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Commit b5d2b1224f ("target/cortex_a: add hypervisor mode")
added sp_hyp, spsr_hyp registers with gdb_index 51 and 52
but did not moved FP regs enum base starting from 51.
Move FP registers indices to make room for added registers.
Change-Id: I4338777545918fdf62016e06764308dacea61e98
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9235
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Switch to LOG_TARGET_DEBUG() and LOG_TARGET_ERROR()
to make analyzing logs of multicore system easier.
Not changed completely in the whole file, the changes were focused
to halt and resume.
Change-Id: I055ad682d3098d5c301a111605d57e504f877b4c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9207
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Restarting the program buffer memory write pipeline when the write of
the last element resulted in the busy response triggers an extra memory
wrtite, that is cought by an assertion:
```
src/target/riscv/riscv-013.c:5048: write_memory_progbuf_inner: Assertion
`next_addr_on_target - args.address <= (target_addr_t)args.size *
args.count' failed.
```
Change-Id: I0f27145cad24686cf539aebfea7f6578b7cd78ab
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9233
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
For all the targets that support SMP, the sub-commands 'smp' and
'smp_gdb' are under the arch name:
- aarch64 smp
- cortex_a smp
- cortex_m smp
- esp32 smp
- mips_m4k smp
Keep consistency among OpenOCD commands, and move under the arch
name 'riscv' the SMP subcommands.
Change-Id: Iede7841c2df8161ff2c6fea3be561d1f26ad6cd0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9165
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
The buffer 'args' is allocated and freed in the caller function
parse_reg_ranges().
There is no reason to free it, only in some special case, in the
called function parse_reg_ranges_impl().
Scan build reports:
src/target/riscv/riscv.c:4537:2: warning: Attempt to free
released memory [unix.Malloc]
Drop the free() in the called function.
Change-Id: I2e308670c502f8e140603b4e5c16fc568088e1a8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9164
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The array 'wps_to_enable' is never freed.
Scan build reports:
src/target/riscv/riscv.c:4271:6: warning: Potential leak
of memory pointed to by 'wps_to_enable' [unix.Malloc]
Add the needed free().
While there, check if the allocation is successful.
Change-Id: I00e7ade37a43a97dcc245113ad93c48784fce609
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9163
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1274
From: Sriram Shanmuga <sriramharshalee@gmail.com>
RISC-V Debug Specification v1.0 [3.14.22. System Bus Access Control and
Status (`sbcs`, at 0x38)] states in `sbasize` field description:
> Width of system bus addresses in bits. (0 indicates there is no bus
access support.)
Before the patch, the error message did not include the information
about `sbcs.sbasize` being zero wich made it quite undescriptive:
```
[riscv.cpu] Turning off memory sampling because it failed.
```
Fixes#1270
Change-Id: I5402dd57dc9a81f65ee4c67d24e11c366006427c
Signed-off-by: Sriram Shanmuga <sriramharshalee@gmail.com>
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9142
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
in command 'riscv resume_order' to prevent segfault
on issuing the command without a parameter.
Change-Id: I5d7f4f92c2fa8e9effaba2c000d111e491b7b64f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9132
Tested-by: jenkins
In the riscv fork, [1] has disable the debug log during target
polling, with message:
Improve low-level logging.
Now logging is consistent and more readable.
I did remove most logging during riscv_poll() since it clutters
up the log/screen and is not generally helpful.
This is questionable, because if the user enables the debug log,
the messages should all be logged.
Drop the code that overwrites the 'debug_level'.
Link: https://github.com/riscv-collab/riscv-openocd/commit/54c65a9a4b71 [1]
Change-Id: Ia86b998cf654760f36c2f217d44bcb9ffd9c3a94
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9072
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The coding style requires the 'case' to be at the same indentation
level of its 'switch' statement.
Align the code accordingly.
While there, put at newline the command after the 'case'.
No changes are reported by
git log -p -w --ignore-blank-lines --patience
apart from the newline after 'case'.
Change-Id: Id856e24100de6fb0442afe8bc51545b0138ef02d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9069
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The advantage of this patch is that it brings the new code closer to
OpenOCD coding style - the disadvantage is that it involves modifying
autogenerated files, making it harder to drop in new versions when
riscv-debug-spec changes.
Change-Id: I4c317e11ab1652333b0bb44168f953ef452d3ef5
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8896
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
The cache handling code is written and optimized for dap queuing.
On hla targets it causes a segmentation fault due to uninitialized
AP pointer still set to NULL.
While it's possible to modify the code to cope with hla targets,
this would lower the OpenOCD performance on modern adapters.
Make cache handling not available on hla targets.
Reported-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Ief4499caedcee477b9517a7ad4597d06b5cb061e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 04da6e2c62 ("target: cortex-m: add support for armv8m caches")
Reviewed-on: https://review.openocd.org/c/openocd/+/9202
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Scan-build is unable to correctly follow the deferred loading of
queued read, finalized by the atomic write, thus it incorrectly
claims that the arrays d_u_ccsidr[] and i_ccsidr[] could carry
not initialized values:
armv7m_cache.c:154:31: warning: 1st function call argument
is an uninitialized value [core.CallAndMessage]
cache->arch[cl].d_u_size = decode_ccsidr(d_u_ccsidr[cl]);
armv7m_cache.c:172:29: warning: 1st function call argument
is an uninitialized value [core.CallAndMessage]
cache->arch[cl].i_size = decode_ccsidr(i_ccsidr[cl]);
Initialize the arrays to zero to hide these false positive.
Change-Id: I6d1e88093cb8807848643139647a571c1b566aa8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 04da6e2c62 ("target: cortex-m: add support for armv8m caches")
Reviewed-on: https://review.openocd.org/c/openocd/+/9167
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
