a482b78941
These target configs implement neither device clock setting nor boost of adapter speed in reset-init event. Therefore it's not necessary to set back the safe speed in reset-start Change-Id: I7dcd6f6d1a977388c7a0bc45fe46ede955bd45cb Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/9129 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
61 lines
1.4 KiB
INI
61 lines
1.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
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# This chip is now at end-of-life. Final orders have been taken.
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME pxa255
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x69264013
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}
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME xscale -endian $_ENDIAN \
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-chain-position $_CHIPNAME.cpu
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# PXA255 comes out of reset using 3.6864 MHz oscillator.
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# Until the PLL kicks in, keep the JTAG clock slow enough
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# that we get no errors.
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adapter speed 300
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# both TRST and SRST are *required* for debug
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# DCSR is often accessed with SRST active
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reset_config trst_and_srst separate srst_nogate
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# reset processing that works with PXA
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proc init_reset {mode} {
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# assert both resets; equivalent to power-on reset
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adapter assert trst assert srst
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# drop TRST after at least 32 cycles
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sleep 1
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adapter deassert trst assert srst
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# minimum 32 TCK cycles to wake up the controller
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runtest 50
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# now the TAP will be responsive; validate scanchain
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jtag arp_init
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# ... and take it out of reset
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adapter deassert trst deassert srst
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}
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proc jtag_init {} {
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init_reset startup
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}
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