Files
openocd/tcl/target/vd_riscv.cfg
Jacek Wuwer 2065bac380 jtag/vdebug: implement a polling mechanism
This change adds a polling mechanism to the driver. When not busy
the driver issues a wait, allowing the target to advance time.
The wait period gets adjusted to match the polling setting.

Change-Id: I67f481d05d7c5ce5352b5cb97de78dbaa97d82ae
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8221
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2025-06-07 10:05:05 +00:00

18 lines
405 B
INI

# SPDX-License-Identifier: GPL-2.0-or-later
# Cadence virtual debug interface
# RISCV core
if {![info exists HARTID]} {
set HARTID 0x00
}
if {![info exists CHIPNAME]} {
set CHIPNAME riscv
}
set _TARGETNAME $CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid $HARTID
riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120
riscv set_mem_access sysbus progbuf