STM32U37/U38x devices have 1Mb flash (split into pages of 4 Kb)
Note: add wait for the BSY bit to be cleared in FLASH_SR
Change-Id: I8208aa81951b9e2f7b0a6bbfce3f7c8ad0f78ade
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8874
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Embedded flash also has a user signature area. This is a 512
bytes large page whose data are not erased by asserting ERASE pin or by
software ERASE command. It may be used to store configuration, keys,
trimming values etc.
This commit adds option to access this area from OpenOCD.
Change-Id: If870aa85938b9cccd94f958dd1f3d93dbdf779f0
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8302
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Processors.
QCS6490 and QCM6490 are 6nm processors designed for enterprise and IOT
applications featuring global 5G and Wi-Fi 6E support with similar
architecture.
This configuration file will allow debugging applications on these
processors.
Verified with Olimex(ARM-USB-OCD-H):
openocd -f tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg
-c 'transport select jtag'
-f <path_to_qcs6490_cfg>
and Jlink:
openocd -f tcl/interface/jlink.cfg
-c 'transport select jtag'
-f <path_to_qcs6490_cfg>
Change-Id: I05e923293134eaa9b70d3cf0d18efac9a024b6c7
Signed-off-by: Ashi Gupta <quic_ashig@quicinc.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8615
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The Rockchip RK3588 SoC is used in systems such as the GenBook RK3588
open-hardware laptop and the Coolpi CM5 compute module. This patch adds
support for debugging those. Tested using the ST-LINK/V2 debug adapter
in SWD mode connected to the SDMMC_D2 (SWCLK) and SDMMC_D3 (SWDIO) pins
on the 50-pin J17 connector inside the GenBook RK3588 laptop.
Change-Id: Ia5da403054b6c9aa41184a4e092a74aa882a267d
Signed-off-by: Andreas Dannenberg <andre@miauco.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9013
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Update jtag driver code to reflect these changes and properly drive
Angie probe.
The rationale behind this is to increase the probe performances,
especially in use cases when large files shall be loaded on a target.
The USB transfer performances are now close to those obtained with a
standard FTDI probe.
Change-Id: I3b31d75a3f66c2d07fed8c7423f765acc30925f8
Signed-off-by: Adrien Charruel <acharruel@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8711
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The max32xxx tcl files have been updated to work with the new flashing
algorithm. A new max32xxx.cfg file contains common configuration and
functionality.
Change-Id: Ifaed58836d221ece6192faafa382b30fb72c77a6
Signed-off-by: Henrik Mau <henrik.mau@analog.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8976
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add support for the targets stm32mp21x, stm32mp23x and stm32mp25x.
Add support for the boards stm32mp235f-dk and stm32mp257f-dk.
The board stm32mp215f-dk has no configuration file as it only
provides a generic JTAG/SWD connector for the stm32mp21x SoC.
Change-Id: I0256bebd8a5d5600066d8ae191d83344a35d3d37
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8985
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Align the target script to the handshake implemented in the latest
version of stm32wrapper4dbg to get access to the debug port.
Use hwthread with the SMP node.
Allow ignoring/masking some CPU from the configuration with the
variables EN_<cpu>.
Change-Id: I7117dd7df20b4f6b6e28f911e3e91ee763bdd200
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8984
Tested-by: jenkins
Align the target script to the handshake implemented in the latest
version of stm32wrapper4dbg to get access to the debug port.
Change-Id: Ia1c7773330fda776abb4385331fddbf431d11c39
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8983
Tested-by: jenkins
Move the existing files for STM32MP13x and STM32MP15x in the
folder "st".
Rename the board files using the correct names.
While there, add the missing URL to one of the boards.
Change-Id: If8b92f55e3390ebc75df6a2ea09fcf798ea0b8cf
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8982
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Microchip's PIC64GX Curiosity Board has a RISC-V core complex with 4
application processors and one monitor processor. The Curiosity kit also
has an on-board debug interface based around an FTDI 4232H device.
This patch adds basic target, interface and board support for PIC64GX
Curiosity Kit.
Change-Id: I2234d8725744fbae00b3909773b370e5c18debd8
Signed-off-by: Liam Fletcher <liam.fletcher@microchip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8878
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Microchip's PolarFire SoC has a RISC-V core complex with four
application processors and one monitor processor. This basic
configuration can be used to attach to all proccessor's or a single
processor, specified by the run-time argument $COREID
It can be used with most FTDI based debug interfaces and has been tested
with interface/ftdi/olimex-arm-usb-tiny-h.cfg.
Change-Id: I75dd965f1ce550807706d00fe17de887d36f0b02
Signed-off-by: Liam Fletcher <liam.fletcher@microchip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8877
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The Allwinner H618 is an updated H616 but appears functionally
equivalent. It is used in small boards such as Orange Pi Zero 3.
Change-Id: I299a42be746189f3e8e31070aa26b83ab7d806a4
Signed-off-by: Electric Worry <me@electricworry.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/8936
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
raspberrypi.com is the home for technical information, raspberrypi.org
is the Foundation's site (though there are intelligent redirects).
Several pages have moved around, fix these.
Also tweak a few comments for style and correctness.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
Change-Id: I7f52bcc362fb213b50987e3a42866fe4a6fec883
Reviewed-on: https://review.openocd.org/c/openocd/+/8885
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This change adds a polling mechanism to the driver. When not busy
the driver issues a wait, allowing the target to advance time.
The wait period gets adjusted to match the polling setting.
Change-Id: I67f481d05d7c5ce5352b5cb97de78dbaa97d82ae
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8221
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Enable the trace port (GPIOE) clock, otherwise the following pin
configurations have no effect.
Change-Id: I3942d2527c64340463c3b6c607addb4214f83081
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8823
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Move target configuration files into a dedicated vendor directory as
required by the new guideline for configuration files.
Note that the moved files are still accessible via the old path to ensure
backwards compatibility. This works because of the extended file search in
vendor folders.
Change-Id: If3935985769dc543e8c7d72cda590c9d79303abb
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8905
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The command was already tagged as deprecated in 2015 with commit
0df5577282 ("armv7a: remove l1 flush all data handler") but has
never been removed.
An equivalent command 'cache l2x conf' was introduced at the same
time in commit cd440bd32a ("add armv7a_cache handlers").
Drop it and deprecate it.
Replace the old command in the Tcl script.
Change-Id: Ie24eccc99a78786903704d10ee1d9f6c924529b5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8857
Tested-by: jenkins
Allow flash size override and suppress flash size detection
by setting FLASHSIZE Tcl variable.
reset-init event calls 'connect XIP' ROM API function to make
flash content accessible at the XIP mapping memory area.
Ported from rp2350.cfg
Change-Id: I9b352b1ef6d4c6d4b78a6b61e900ce01355c8eff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8461
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Tested-by: jenkins
While on it use calloc() instead of malloc()/memset()
Drop useless implementation of rp2040_flash_free_driver_priv()
- exactly same as default_flash_free_driver_priv()
Code style fixes forced by checkpatch
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I5c56c4a7d586c0dcab164a45e8f6200ea9a3bd1d
Reviewed-on: https://review.openocd.org/c/openocd/+/8455
Tested-by: jenkins
Also keep size override by FLASHSIZE Tcl variable possible.
Partially backported from former upstream rp2040.c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I224c3644450e8b46e35714bfc5436219ffdee563
Reviewed-on: https://review.openocd.org/c/openocd/+/8451
Tested-by: jenkins
A0 chip: remove pad isolation
A2 chip: instead of reset init fixes we will fix the flash driver
with the following patch by Luke Wren:
8729: flash/nor/rp2xxx: fix flash operation after halt in RISC-V bootsel
https://review.openocd.org/c/openocd/+/8729
I don't have A1 version to test.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I9e9fab04ead929fe6e0a17c6c2f32a6f02e9beb9
Reviewed-on: https://review.openocd.org/c/openocd/+/8450
Tested-by: jenkins
RP2350 has 2 slots where either Cortex-M33 or RISC-V can be selected.
Tcl variable USE_CORE selects what cores will be configured for debug.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I56fe1aa94304bdfd1ec98bba57cc3fa792a35f69
Reviewed-on: https://review.openocd.org/c/openocd/+/8449
Tested-by: jenkins
Add support for the Real-Time CPU (RCPU) of K1, which is a 32-bit RISC-V
N308 High-Efficiency Processor Core designed by Nuclei System Technology
Co. Ltd.
The JTAG interface can be configured to connect to either X60s or RCPU
processors. To enable JTAG for RCPU, set TARGET to "rcpu".
For example:
openocd -c "set TARGET rcpu" -f interface/cmsis-dap.cfg \
-f target/spacemit-k1.cfg
Change-Id: I9cd62fac332137afac17efa52702818de8f0b6f5
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-on: https://review.openocd.org/c/openocd/+/8821
Reviewed-by: liangzhen <zhen.liang@spacemit.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add SWD multidrop setting.
Fix the name of AP #1 to AUX-AP
Set AUX-AP CSW Prot bit[0] to make RISC-V debug accessible on AUX-AP.
Change-Id: I496e07acfe90dd858e4403176a8330d8c1a0b560
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8752
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
AM261[1] is a optimized cutdown of AM263P SoC. The key difference is
the reduced number of R5F cores which is now dropped down to 2, and
the DIE ID is different from AM263p, but all other definitions are
compatible, so reuse the definition.
[1] https://www.ti.com/product/AM2612
Change-Id: Ib6ca0b59d0b8991df6e4ab349d371187438cb393
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8792
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
AM263P[1] adds additional features to AM263 SoC. [2] provides a
detailed list of differences, however, the key difference from
processor usage perspective is the increased SRAM and Remote L2(RL2)
Cache for improved performance of R5F. To differentiate the DIE ID
is different, however rest of the processor description remain
compatible to AM263, hence reuse the definition.
[1] https://www.ti.com/product/AM263P4
[2] https://www.ti.com/lit/pdf/spradb3
Change-Id: If47935caf1f995d7e606547e0d6545c39544678a
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8770
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
TI K3 Debug systems have a Power Access Port (Power-AP) which allows
for functionality such as reset via debugger that using the SPREC
register. SoCs/Boards that do not have support for SRST or TRST can
make use of this to force a system reset via debug access.
Change-Id: Ic5f9cc7f7fba77b353b0c0b42d8afc02502251a0
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8769
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
BL602, BL702 and BL702L series of chips are sharing same architecture,
so they all need same software reset mechanism as well.
Only difference (in terms of configuration needed for JTAG) are TAP ID,
workarea address and size. This is addressed by creating bl602_common.cfg
tcl file, which contains all those common stuff between the chips.
The script is prefixed by bl602, as this was
first *publicly* available chip from Bouffalo with this architecture.
This patch also improves reset mechanism. Previous reset mechanism did not
worked properly when slower JTAG adapter was used (it attached too late).
New reset mechanism uses various methods to keep CPU in BootROM, until
the JTAG adapter does not attach again after reset. Additionally,
we trigger SW Reset by directly using DMI commands to write to register
with system bus method, to avoid getting error about unsuccessful write.
The new method works on both FT232H (8MHz JTAG clock) and
unnamed CMSIS-DAP dongle (1.5MHz JTAG clock).
Change-Id: I5be3694927793fd3f64c9ed4ee6ded2db0d25cae
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8593
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The RISC-V coprocessor is currently not supported. It is attached to the
DAP via AP#2 but the AP implementation is unknown.
The nRFL54L series uses resistive RAM (RRAM) as non-volatile memory
which can be programmed directly. Since it does not fit in the current
flash memory infrastructure of OpenOCD there is no NVM support so far.
Change-Id: I9934af4fd3bb8b7272954fc4b17638c7dabbbee0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8609
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In previous implementation, it was known that it does not perform
full reset, and that some peripherals, such as GLB core,
which handles among other stuff GPIOs, was not reset.
It was presumed, that full reset by software is not possible,
although, by accident, even when comment says that
CTRL_PWRON_RESET is set to 1, it is not
(value written into 0x40000018 supposed to be 0x7, not 0x6).
CTRL_PWRON_RESET indeed triggers full "power-on like" reset,
so this method is implemented in this commit.
There are some workarounds to make reset seamless, without any
error messages, which are described in comments of TCL script.
Only down-side of this reset is, that chip is halted after reset
bit later in BootROM than previous implementation,
but it's still good.
Change-Id: Ife2cdcc6a2d96a2e24039bfec149705baf046318
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8529
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The _targets has to be global as it is accessed at the end of this file.
This is already the case for setup_a5x {}, assure it is the same way for
setup_crx{} . Without this change, the _targets at the end of this file
is empty in case the Cortex-R is the boot core, fix this.
Change-Id: I4979e3125ec7d93bbd56eee0096ae1d9c5f6a565
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8470
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
