The MSPM0 devices support only SWD.
Drop swj support, add swd support.
This also gets rid of the following warnings:
Warn : DEPRECATED: auto-selecting transport "swd". Use 'transport ...
Warn : Transport "swd" was already selected
Tested by programming/verifying firmware on LP-MSPM0G3519 dev board.
Change-Id: Ieafd9c4691343124b2dfb2daa1c0d3a96b13e485
Signed-off-by: Mikhail Iakhiaev <iakhiaev@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9413
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Move the configuration files into a dedicated vendor folder as required
by the developer guidelines.
Change-Id: I9ed39e32b6281a9cb8510914690f3f7751b795c8
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9271
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Corrected the include path for max32xxx_common.cfg in some files.
Cleaned up and standarised some comments in the max32... files.
Change-Id: I94dcc7ba6868bdd9730f03d3aa76fcdbbae33c3e
Signed-off-by: Mark O'Donovan <shiftee@posteo.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/9323
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The assignment of adapter speed 500 was getting overwritten when
max32xxx_common.cfg is sourced at the end.
Also removed incorrect comment.
Change-Id: I49d69073d93dedf28ed69d63ece35758f4707137
Signed-off-by: Mark O'Donovan <shiftee@posteo.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/9322
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Prepare to add stm32wba6x support.
The OTP address is different between the stm32wb5xxx and stm32wb6xxx
microcontrollers, so the configuration file can't be the same for both.
Change-Id: Ib7485e0211779d98cca56e73397197b712460c69
Signed-off-by: Guillaume Faussard <guillaume.faussard@withings.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9326
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Ahmed Haoues <ahmed.haoues@st.com>
Initial release of Flash bank driver for Bouffalo chips.
The driver currently supports BL602, BL702, BL702L series of chips.
Similar SFlash core is inside of BL808, BL606P and BL616 series,
so those might be supported in future as well.
With adapter speed set to 8000, it can reach speed 140 KiB/s.
Since chips have eXecute In Place support, and they also require
boot config in Flash at offset 0x0, it's required to have properly
crafted linker script, so OpenOCD knows where to write firmware
through gdb.
There is required flash bank parameter, which specifies the chip type.
This is required because BL702 and BL702L have same TAP ID CODE, and
there are no usable indicators to use for automatic chip type
recognition in the chip.
Change-Id: Id57336d447be3c608b39ba3ed143527bfdc0af98
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8527
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Configure reset-start event to set/clear DM resethaltreq bit.
In reset-assert event check if srst is configured.
Avoid unnecessary double reset if srst is configured.
Write dmcontrol ackhavereset in reset-deassert-post event if necessary.
Change-Id: I06b201bc5651c301912158c1436b9b3e3bc042a0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9316
Reviewed-by: Tom Hebb <tommyhebb@gmail.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The pluggable reset events are invoked only in the context of
proc ocd_process_reset_inner, so we can use $halt variable
directly and avoid proc init_reset redefinition.
Change-Id: Ie74c340c51cb2c55d8ffc9f74bb1a1a8e3461515
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9315
Tested-by: jenkins
Reviewed-by: Tom Hebb <tommyhebb@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The GD32VF103 has a perculiar reset procedure that does not fully comply
with the RISC-V Debug Specification.
Move the workaroung to the `deassert-reset-post` handler.
Change-Id: I153c866a5b7e2dff2552cc92772ce6ed77ad606b
Signed-off-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9314
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
stm32f334k8 only has 12kbytes of SRAM and
flashing with the default WORKAREA of 16kbytes
will fail for images > 12k.
Change-Id: If9be0b0e7cd6e4ba15a130d8e06c74e4a0e22a61
Signed-off-by: Maximilian Schneider <max@schneidersoft.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/9283
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
With 'proc find' able to handle the replacement of '_' to '-',
drop the now unnecessary hardcoded renames.
Change-Id: I67fe3b5de8bad7611b2229fed8d2eefee848eb81
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9279
Tested-by: jenkins
Reviewed-by: Nishanth Menon <nm@ti.com>
Replace "_" file separator with "-" file separator as recommended by
coding standards guidelines. While doing this, add the files that were
present in previous v0.12.0 release to file_renaming.cfg for this
non-trivial rename.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I88685f08f4a0cc580fa3b03f6db0d85061d65b94
Reviewed-on: https://review.openocd.org/c/openocd/+/9236
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Rename the _swd_native.cfg files as -self-hosted.cfg files as a better
representation of what we are using the configuration files to be.
Change-Id: I4eb469a219b83de6a9e7a8dfef5607306f59a7cd
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9206
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
As part of the cfg file cleanups, let us move the TI evms, launchpads
and other development platform configuration files to board/ti folder.
While at this, drop the "ti_" prefix as the folder structure gives us
the details anyways.
Change-Id: I929b88e0cf6527f3181820ad0b9b4744185eabaf
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9205
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Move the BeagleBoard.org Foundation boards to it's own folder. This
allows additional support such as BeagleV-Fire and other non TI SoC
vendor support to be subsequently added.
While doing this,
* Use "-" as separator for the file names as recommended
by coding standards.
* To maintain compatibility, add the non-trivial renames to
file_renaming.cfg
Change-Id: Ie916c9bf81fc3922bf19ed9ed2db841549d29ca9
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9204
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Move the ti targets to a TI folder. Since the folder is ti, we can
drop the "ti" prefix from the files themselves.
Done via the following script:
mkdir target/ti
FILES=`ls target/ti*.cfg target/omap*.cfg target/am335x.cfg
target/amdm37x.cfg target/icepick.cfg target/stellaris.cfg
target/davinci.cfg`
for cname in $FILES
do
bname=`basename $cname`
nname=`echo $bname|sed -e "s/^ti-//g"|sed -e "s/ti_//g"`
npath="target/ti/$nname"
echo "$cname => $npath"
fref=`git grep $cname .|cut -d ':' -f1|sort -u`
sed -i -e "s&$cname&$npath&g" $fref
git mv $cname $npath
done
Change-Id: I9f94dc6bb01f73721d4ff96be92cb51de2cbf0e2
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9203
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For stm32l4, stm32wbx, stm32wlx the target tcl scripts try to change the
MSI oscillator's speed to 24 MHz before boosting the interface
frequency, but don't clear the RCC_CR_MSIRANGE field correctly before.
This causes the register write access to fail and leaves the clock
frequency unchanged. For the stm32wlx, the script also neglects to set
the MSIRGSEL bit, such that the frequency setting is not actually
applied.
The issue appears to not cause a problem when using an ST-Link adapter.
When using an FT4232HP, communication to the target fails after the
reset-init event, possibly because this adapter actually supports the
higher interface frequency.
This commit fixes the register accesses to make sure the RCC_CR_MSIRANGE
is cleared to zero before OR-ing the new value. For the stm32wlx, also
set the MSIRGSEL bit. Just to be safe, also fix the write access to the
FLASH_ACR_LATENCY field to clear it before OR-ing, even though it should
be zero at reset anyways.
Change-Id: Ie8320fa6ee2086981c0b1f3c18f51e171709078d
Signed-off-by: Niklas Gürtler <profclonk@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9282
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
These changes bring over some lines from the independently-developed
gd32vf103.cfg that I contributed[1] to the riscv-openocd fork of
OpenOCD. They're all minor, so I'm squashing them into one review. The
changes are as follows:
- Add boundary scan TAP.
- Mention inconsistency of CPU ID between vendor SDK and real hardware.
- Specify that there's no MMU so we don't look for one at runtime.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Change-Id: Ie8033eff436d6dbdc3eab156769a8908ccb547f6
Reviewed-on: https://review.openocd.org/c/openocd/+/6959
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
cJTAG OSCAN1, in lieu of 4-wire JTAG, is starting to be a configuration
option for some SiFive hardware. An FTDI-based adapter that can be
configured to drive the bidirectional pin TMSC is assumed for this
topology. Specifically, the Olimex ARM-USB-TINY-H with the ARM-JTAG-SWD
adapter, connected to a SiFive cJTAG-enabled target board is the only
known concrete topology, currently. But in theory, other FTDI based
devices that can drive a two-wire bidirectional signaling pattern could
be made to work in this scheme in the future.
These code changes are offered as a way to drive that topology. It's
translating IR/DR and JTAG traversal commands to the two-wire clocking
and signaling.
See:
- https://github.com/riscv-collab/riscv-openocd/pull/320
- https://github.com/riscv-collab/riscv-openocd/pull/736
Signed-off-by: Greg Savin <greg.savin@sifive.com>
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Change-Id: Ia1daa2c01227c4b0005be947b2bb0de81a800874
Reviewed-on: https://review.openocd.org/c/openocd/+/6981
Tested-by: jenkins
Change 7732: jtag/drivers/bcm2835gpio: Support all 54 GPIO pins [1]
reduces the time needed for GPIO handling.
Adjust the speed offsets to the new and faster bcm2835gpio code.
Measured with Sigrok/PulseView, sampled at 800 MHz.
Configured as SWD with the fast path in the driver - other
modes are expected to be slower.
Adjusted to keep all half periods of SWCLK in the sampled poll
sequence longer or equal than the half period of the nominal
adapter speed.
Link: [1] https://review.openocd.org/c/openocd/+/7732
Change-Id: Ia9e932dfd7547c8011c1d20d9e90bc0294050e8a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9234
Tested-by: jenkins
Reviewed-by: Vincent Fazio <vfazio@gmail.com>
drop unneeded reset-init event
The speed is set to 1800 kHz at initialization, but increases to 4000 kHz
before flash programming, with debugging continuing at this higher speed.
So, setting 4000 kHz from the start makes sense.
Change-Id: I6bccb5837c624943212b727368b40153e42ccebb
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9027
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
These target configs implement neither device clock setting
nor boost of adapter speed in reset-init event.
Therefore it's not necessary to set back the safe speed in reset-start
Change-Id: I7dcd6f6d1a977388c7a0bc45fe46ede955bd45cb
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9129
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Adds support for direct memory access via SWD emulation for AM64x and
J784s4 boards, configuring addresses and parameters required for
direct memory operations.
Change-Id: Iebc16612b3990b2ef19ddc4143b66ab1bcbfe0f3
Signed-off-by: Joao Lima <joao.lima@hbkworld.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9021
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Remove the configuration file, a replacement is already available.
Link the old filename to the new configuration file to ensure backwards
compatibility.
Change-Id: I77cbd62d805b1c9b9bb8f56a823c3f6476d1a5a9
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9150
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Remove the configuration file, a replacement is already available.
Link the old filename to the new configuration file to ensure backwards
compatibility.
Change-Id: I11361e471bb7ec277a850f956e51cd7d0fab408d
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9149
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Adds support for BL616 series of chips, BL616 and BL618.
No flash bank support yet.
BL616 in comparison with BL602-series have new architecture,
using T-Head E907 RISC-V cores, instead of SiFive ones.
As BL602-series, the ndmreset bit in RISC-V Debug Module
does not reset the chip as it should, so we need to do it
manually with registers almost the same way as in BL602.
Additionally, JTAG Debug Transport Module in the chip have wrongly
implemented Test-Logic-Reset state, causing automatic chain scan
not working at all after initial JTAG usage. This is because
Test-Logic-State do not set IR instruction to IDCODE,
as it should by JTAG spec. We can fix this by getting state machine
to known state and configure IR instruction manually to IDCODE.
This bug was so far found in T-Head C906 and E907 IP cores.
This patch was tested heavily and works reliably on
BL616, BL618 and QCC74X.
Change-Id: Idc80a702e817d78fc0ca925572c68d4d0c28ce4e
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9145
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The reset-init handler needs to call the ROM API function to enable
XIP from flash.
Correct syntax for this command is to supply two-letter function code
as the first argument, flash bank number sholudn't be there.
Reported-by: Thomas D. Dean <tomdean@wavecable.com>
Fixes: 376d11c2e3
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: I94713630300ead32bc9db6a1a77658fa5d5214d4
Reviewed-on: https://review.openocd.org/c/openocd/+/9134
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
pico-debug and pico2-debug are virtual CMSIS-DAP adapters that
run on the otherwise dormant second core of the RP2040 and RP2350
respectively.
Change-Id: Ifd7dcbbabeb86c738cc58854add0e897633197de
Signed-off-by: Peter Lawrence <majbthrd@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9099
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Make the driver more flexible and define adapter-specific configurations
in Tcl instead of C using the adapter GPIO subsystem.
The rework also includes coding style fixes and improvements of the
documentation. All modifications are done such that backwards
compatibility is ensured.
Tested with Olimex ARM-JTAG cable [1] and APM32F103 target device on
Linux and FreeBSD. The driver works on Linux using direct I/O and PPDEV.
On FreeBSD, only PPDEV works. The build with direct I/O already failed
before the patch. This problem will be fixed in a subsequent patch.
The patch is not tested on Windows because there is no documentation
for it.
[1] https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG/
Change-Id: Ib671d52a919eaf2959cf6365f2c8004257ae074c
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8943
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Create a new backend for cmsis_dap driver that allows CMSIS-DAP protocol
to run over TCP/IP instead of USB.
An example implementation of the firmware for an SWD programmer that
uses this cmsis_dap_tcp protocol can be found at the link below.
https://github.com/bkuschak/cmsis_dap_tcp_esp32
Using this cmsis_dap_tcp backend with the firmware above on an ESP32-C6
programmer and STM32F401RE target shows the following performance:
- loading 96KB image to RAM: 80 KB/sec
- dumping 96KB image from RAM: 72 KB/sec
- flashing 512KB image completes in about 13.5 seconds (including erase,
program, and verify).
Change-Id: I6e3e45016bd16ef2259561b1046788f5536b0687
Signed-off-by: Brian Kuschak <bkuschak@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8973
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
STM32U37/U38x devices have 1Mb flash (split into pages of 4 Kb)
Note: add wait for the BSY bit to be cleared in FLASH_SR
Change-Id: I8208aa81951b9e2f7b0a6bbfce3f7c8ad0f78ade
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8874
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
