The Orange Pi Zero 3 is an SBC that uses an Allwinner H618
SoC. As such, JTAG support is fully available, however the
SoC multiplexes JTAG function with UART1 and microSD.
Unfortunately Xunlong has used UART1 for the Wifi-BT
chip, leaving JTAG accessible only via the microSD using
a microSD breakout board (for example).
Change-Id: I0dc078cd2f3176815271917eb5e948cc8ef94525
Signed-off-by: Electric Worry <me@electricworry.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/8938
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The Allwinner H618 is an updated H616 but appears functionally
equivalent. It is used in small boards such as Orange Pi Zero 3.
Change-Id: I299a42be746189f3e8e31070aa26b83ab7d806a4
Signed-off-by: Electric Worry <me@electricworry.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/8936
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
raspberrypi.com is the home for technical information, raspberrypi.org
is the Foundation's site (though there are intelligent redirects).
Several pages have moved around, fix these.
Also tweak a few comments for style and correctness.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
Change-Id: I7f52bcc362fb213b50987e3a42866fe4a6fec883
Reviewed-on: https://review.openocd.org/c/openocd/+/8885
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This change adds a polling mechanism to the driver. When not busy
the driver issues a wait, allowing the target to advance time.
The wait period gets adjusted to match the polling setting.
Change-Id: I67f481d05d7c5ce5352b5cb97de78dbaa97d82ae
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8221
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Enable the trace port (GPIOE) clock, otherwise the following pin
configurations have no effect.
Change-Id: I3942d2527c64340463c3b6c607addb4214f83081
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8823
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Board configuration files for specific external debug adapters are not /
no longer supported.
Checkpatch-ignore: LONG_LINE_STRING
Change-Id: I0f391dfb1a2d7ceb92c2ad3e34eaeb8a85b2cdc5
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8865
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add the old configuration files to the 'file_renaming' list in order to
ensure backwards compatibility.
Change-Id: Ia61df8e5cd8c19cee19a494635c8025e36f3f4a7
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8907
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Move board configuration files into a dedicated vendor directory as
required by the new guideline for configuration files.
Change-Id: Icbf368d7a453c82813e685d2935b186eb738c3ea
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8864
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Move target configuration files into a dedicated vendor directory as
required by the new guideline for configuration files.
Note that the moved files are still accessible via the old path to ensure
backwards compatibility. This works because of the extended file search in
vendor folders.
Change-Id: If3935985769dc543e8c7d72cda590c9d79303abb
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8905
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The TCL configuration files are going to be dispatched in vendor
specific folders.
Old user configuration files will fail to find the new files to
include, so a set of fallback files reporting the deprecation
should replace the renamed files.
To prevent such enormous proliferation of fallback files, extend
the search of files in the vendor folders too.
For non-trivial renames, a dedicated table is added in the file
tcl/file_renaming.cfg to track old --> new file names.
The deprecated message is then part of the extended search.
E.g.:
old file names:
- path/to/a/certain/vendor_config_file
- path/to/a/certain/vendor-config_file
trigger search of:
- path/to/a/certain/vendor/config_file
and
- path/to/a/certain/config_file
trigger search of:
- path/to/a/certain/${vendor}/config_file
among a possible vendors list.
This is a temporarily feature that should be removed as soon as
possible to prevent clashing on files with the same name.
The names in tcl/file_renaming.cfg are for demonstration purpose
only and should be dropped when the first real entries are added.
Change-Id: If4793fef27dc570d5df4ff4d77a5e36004f394f6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8929
Tested-by: jenkins
The command was already tagged as deprecated in 2015 with commit
0df5577282 ("armv7a: remove l1 flush all data handler") but has
never been removed.
An equivalent command 'cache l2x conf' was introduced at the same
time in commit cd440bd32a ("add armv7a_cache handlers").
Drop it and deprecate it.
Replace the old command in the Tcl script.
Change-Id: Ie24eccc99a78786903704d10ee1d9f6c924529b5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8857
Tested-by: jenkins
Commit 34ec5536c0 ("stlink: deprecate HLA support") makes hard
to use the still functional HLA transport with the stlink listed
in board config files.
Now that the prefixes 'hla_' and 'dapdirect_' has been dropped
from the transport name, allow overriding the transport by using
the 'stlink-hla' script in front of the board file, e.g.:
openocd -f interface/stlink-hla.cfg -f board/st_nucleo_f4.cfg
Revert the documentation changes of the change above.
Improve the documentation to explain how to use the compatibility
HLA mode.
Improve the error message in stlink driver to guide the user to
update the stlink firmware and to use the compatibility HLA mode.
Change-Id: I5d0bc7954511692cebe024bda2aaa72767b97681
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8679
Tested-by: jenkins
Allow flash size override and suppress flash size detection
by setting FLASHSIZE Tcl variable.
reset-init event calls 'connect XIP' ROM API function to make
flash content accessible at the XIP mapping memory area.
Ported from rp2350.cfg
Change-Id: I9b352b1ef6d4c6d4b78a6b61e900ce01355c8eff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8461
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Tested-by: jenkins
While on it use calloc() instead of malloc()/memset()
Drop useless implementation of rp2040_flash_free_driver_priv()
- exactly same as default_flash_free_driver_priv()
Code style fixes forced by checkpatch
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I5c56c4a7d586c0dcab164a45e8f6200ea9a3bd1d
Reviewed-on: https://review.openocd.org/c/openocd/+/8455
Tested-by: jenkins
Also keep size override by FLASHSIZE Tcl variable possible.
Partially backported from former upstream rp2040.c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I224c3644450e8b46e35714bfc5436219ffdee563
Reviewed-on: https://review.openocd.org/c/openocd/+/8451
Tested-by: jenkins
A0 chip: remove pad isolation
A2 chip: instead of reset init fixes we will fix the flash driver
with the following patch by Luke Wren:
8729: flash/nor/rp2xxx: fix flash operation after halt in RISC-V bootsel
https://review.openocd.org/c/openocd/+/8729
I don't have A1 version to test.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I9e9fab04ead929fe6e0a17c6c2f32a6f02e9beb9
Reviewed-on: https://review.openocd.org/c/openocd/+/8450
Tested-by: jenkins
RP2350 has 2 slots where either Cortex-M33 or RISC-V can be selected.
Tcl variable USE_CORE selects what cores will be configured for debug.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I56fe1aa94304bdfd1ec98bba57cc3fa792a35f69
Reviewed-on: https://review.openocd.org/c/openocd/+/8449
Tested-by: jenkins
Add support for the Real-Time CPU (RCPU) of K1, which is a 32-bit RISC-V
N308 High-Efficiency Processor Core designed by Nuclei System Technology
Co. Ltd.
The JTAG interface can be configured to connect to either X60s or RCPU
processors. To enable JTAG for RCPU, set TARGET to "rcpu".
For example:
openocd -c "set TARGET rcpu" -f interface/cmsis-dap.cfg \
-f target/spacemit-k1.cfg
Change-Id: I9cd62fac332137afac17efa52702818de8f0b6f5
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-on: https://review.openocd.org/c/openocd/+/8821
Reviewed-by: liangzhen <zhen.liang@spacemit.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add SWD multidrop setting.
Fix the name of AP #1 to AUX-AP
Set AUX-AP CSW Prot bit[0] to make RISC-V debug accessible on AUX-AP.
Change-Id: I496e07acfe90dd858e4403176a8330d8c1a0b560
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8752
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
AM261[1] is a optimized cutdown of AM263P SoC. The key difference is
the reduced number of R5F cores which is now dropped down to 2, and
the DIE ID is different from AM263p, but all other definitions are
compatible, so reuse the definition.
[1] https://www.ti.com/product/AM2612
Change-Id: Ib6ca0b59d0b8991df6e4ab349d371187438cb393
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8792
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
AM263P[1] adds additional features to AM263 SoC. [2] provides a
detailed list of differences, however, the key difference from
processor usage perspective is the increased SRAM and Remote L2(RL2)
Cache for improved performance of R5F. To differentiate the DIE ID
is different, however rest of the processor description remain
compatible to AM263, hence reuse the definition.
[1] https://www.ti.com/product/AM263P4
[2] https://www.ti.com/lit/pdf/spradb3
Change-Id: If47935caf1f995d7e606547e0d6545c39544678a
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8770
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
TI K3 Debug systems have a Power Access Port (Power-AP) which allows
for functionality such as reset via debugger that using the SPREC
register. SoCs/Boards that do not have support for SRST or TRST can
make use of this to force a system reset via debug access.
Change-Id: Ic5f9cc7f7fba77b353b0c0b42d8afc02502251a0
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8769
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
BL602, BL702 and BL702L series of chips are sharing same architecture,
so they all need same software reset mechanism as well.
Only difference (in terms of configuration needed for JTAG) are TAP ID,
workarea address and size. This is addressed by creating bl602_common.cfg
tcl file, which contains all those common stuff between the chips.
The script is prefixed by bl602, as this was
first *publicly* available chip from Bouffalo with this architecture.
This patch also improves reset mechanism. Previous reset mechanism did not
worked properly when slower JTAG adapter was used (it attached too late).
New reset mechanism uses various methods to keep CPU in BootROM, until
the JTAG adapter does not attach again after reset. Additionally,
we trigger SW Reset by directly using DMI commands to write to register
with system bus method, to avoid getting error about unsuccessful write.
The new method works on both FT232H (8MHz JTAG clock) and
unnamed CMSIS-DAP dongle (1.5MHz JTAG clock).
Change-Id: I5be3694927793fd3f64c9ed4ee6ded2db0d25cae
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8593
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
To alleviate the need to bitbang SWD, I've written a SWD SPI
implementation. This code is inspired by the work of luppy@appkaki.com
as shown at github.com/lupyuen/openocd-spi but with the desire to be
more generic. This implementation makes use of the more common 4 wire
SPI port using full duplex transfers to be able to capture the SWD ACK
bits when a SWD TX operation is in progress.
TEST:
Connects successfully with the following combinations:
Hosts:
Raspberry Pi 4B
Unnamed Qualcomm SoC with QUPv3 based SPI port
Targets:
Raspberry Pi 2040
Nordic nRF52840
NXP RT500
Change-Id: Ic2f38a1806085d527e6f999a3d15aea6f32d1019
Signed-off-by: Richard Pasek <rpasek@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8645
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
Previously, Linux assigned gpiochip numbers sequentially depending on
when the chip driver was probed. As RP1 is on the end of a PCIe link, it
is probed later than the on-board chips (including expanders connected
over SPI/I2C). This meant that RP1's gpiochip assignment was at an
offset that could potentially change.
A downstream kernel patch now assigns fixed offsets for RP1 and the
onboard gpiochips. Query the device tree to get proper GPIO_CHIP index.
Change-Id: I759978d4b3021c815a7d9febb41961cd1d3d185c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8650
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Tested-by: jenkins
The RISC-V coprocessor is currently not supported. It is attached to the
DAP via AP#2 but the AP implementation is unknown.
The nRFL54L series uses resistive RAM (RRAM) as non-volatile memory
which can be programmed directly. Since it does not fit in the current
flash memory infrastructure of OpenOCD there is no NVM support so far.
Change-Id: I9934af4fd3bb8b7272954fc4b17638c7dabbbee0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8609
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In previous implementation, it was known that it does not perform
full reset, and that some peripherals, such as GLB core,
which handles among other stuff GPIOs, was not reset.
It was presumed, that full reset by software is not possible,
although, by accident, even when comment says that
CTRL_PWRON_RESET is set to 1, it is not
(value written into 0x40000018 supposed to be 0x7, not 0x6).
CTRL_PWRON_RESET indeed triggers full "power-on like" reset,
so this method is implemented in this commit.
There are some workarounds to make reset seamless, without any
error messages, which are described in comments of TCL script.
Only down-side of this reset is, that chip is halted after reset
bit later in BootROM than previous implementation,
but it's still good.
Change-Id: Ife2cdcc6a2d96a2e24039bfec149705baf046318
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8529
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Provide cable specific configuration files like for the FTDI interface.
Depcrecate the old configuration files but keep them until the next
release for compatibility reasons.
Change-Id: I436bd60779a107120c9e1b1f0b8a69a39a240ad4
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8514
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
