The MSPM0 devices support only SWD.
Drop swj support, add swd support.
This also gets rid of the following warnings:
Warn : DEPRECATED: auto-selecting transport "swd". Use 'transport ...
Warn : Transport "swd" was already selected
Tested by programming/verifying firmware on LP-MSPM0G3519 dev board.
Change-Id: Ieafd9c4691343124b2dfb2daa1c0d3a96b13e485
Signed-off-by: Mikhail Iakhiaev <iakhiaev@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9413
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Move the configuration files into a dedicated vendor folder as required
by the developer guidelines.
Change-Id: I9ed39e32b6281a9cb8510914690f3f7751b795c8
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9271
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Corrected the include path for max32xxx_common.cfg in some files.
Cleaned up and standarised some comments in the max32... files.
Change-Id: I94dcc7ba6868bdd9730f03d3aa76fcdbbae33c3e
Signed-off-by: Mark O'Donovan <shiftee@posteo.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/9323
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The assignment of adapter speed 500 was getting overwritten when
max32xxx_common.cfg is sourced at the end.
Also removed incorrect comment.
Change-Id: I49d69073d93dedf28ed69d63ece35758f4707137
Signed-off-by: Mark O'Donovan <shiftee@posteo.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/9322
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Prepare to add stm32wba6x support.
The OTP address is different between the stm32wb5xxx and stm32wb6xxx
microcontrollers, so the configuration file can't be the same for both.
Change-Id: Ib7485e0211779d98cca56e73397197b712460c69
Signed-off-by: Guillaume Faussard <guillaume.faussard@withings.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9326
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Ahmed Haoues <ahmed.haoues@st.com>
Initial release of Flash bank driver for Bouffalo chips.
The driver currently supports BL602, BL702, BL702L series of chips.
Similar SFlash core is inside of BL808, BL606P and BL616 series,
so those might be supported in future as well.
With adapter speed set to 8000, it can reach speed 140 KiB/s.
Since chips have eXecute In Place support, and they also require
boot config in Flash at offset 0x0, it's required to have properly
crafted linker script, so OpenOCD knows where to write firmware
through gdb.
There is required flash bank parameter, which specifies the chip type.
This is required because BL702 and BL702L have same TAP ID CODE, and
there are no usable indicators to use for automatic chip type
recognition in the chip.
Change-Id: Id57336d447be3c608b39ba3ed143527bfdc0af98
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8527
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Configure reset-start event to set/clear DM resethaltreq bit.
In reset-assert event check if srst is configured.
Avoid unnecessary double reset if srst is configured.
Write dmcontrol ackhavereset in reset-deassert-post event if necessary.
Change-Id: I06b201bc5651c301912158c1436b9b3e3bc042a0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9316
Reviewed-by: Tom Hebb <tommyhebb@gmail.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The pluggable reset events are invoked only in the context of
proc ocd_process_reset_inner, so we can use $halt variable
directly and avoid proc init_reset redefinition.
Change-Id: Ie74c340c51cb2c55d8ffc9f74bb1a1a8e3461515
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9315
Tested-by: jenkins
Reviewed-by: Tom Hebb <tommyhebb@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The GD32VF103 has a perculiar reset procedure that does not fully comply
with the RISC-V Debug Specification.
Move the workaroung to the `deassert-reset-post` handler.
Change-Id: I153c866a5b7e2dff2552cc92772ce6ed77ad606b
Signed-off-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9314
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
stm32f334k8 only has 12kbytes of SRAM and
flashing with the default WORKAREA of 16kbytes
will fail for images > 12k.
Change-Id: If9be0b0e7cd6e4ba15a130d8e06c74e4a0e22a61
Signed-off-by: Maximilian Schneider <max@schneidersoft.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/9283
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Move the ti targets to a TI folder. Since the folder is ti, we can
drop the "ti" prefix from the files themselves.
Done via the following script:
mkdir target/ti
FILES=`ls target/ti*.cfg target/omap*.cfg target/am335x.cfg
target/amdm37x.cfg target/icepick.cfg target/stellaris.cfg
target/davinci.cfg`
for cname in $FILES
do
bname=`basename $cname`
nname=`echo $bname|sed -e "s/^ti-//g"|sed -e "s/ti_//g"`
npath="target/ti/$nname"
echo "$cname => $npath"
fref=`git grep $cname .|cut -d ':' -f1|sort -u`
sed -i -e "s&$cname&$npath&g" $fref
git mv $cname $npath
done
Change-Id: I9f94dc6bb01f73721d4ff96be92cb51de2cbf0e2
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9203
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For stm32l4, stm32wbx, stm32wlx the target tcl scripts try to change the
MSI oscillator's speed to 24 MHz before boosting the interface
frequency, but don't clear the RCC_CR_MSIRANGE field correctly before.
This causes the register write access to fail and leaves the clock
frequency unchanged. For the stm32wlx, the script also neglects to set
the MSIRGSEL bit, such that the frequency setting is not actually
applied.
The issue appears to not cause a problem when using an ST-Link adapter.
When using an FT4232HP, communication to the target fails after the
reset-init event, possibly because this adapter actually supports the
higher interface frequency.
This commit fixes the register accesses to make sure the RCC_CR_MSIRANGE
is cleared to zero before OR-ing the new value. For the stm32wlx, also
set the MSIRGSEL bit. Just to be safe, also fix the write access to the
FLASH_ACR_LATENCY field to clear it before OR-ing, even though it should
be zero at reset anyways.
Change-Id: Ie8320fa6ee2086981c0b1f3c18f51e171709078d
Signed-off-by: Niklas Gürtler <profclonk@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9282
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
These changes bring over some lines from the independently-developed
gd32vf103.cfg that I contributed[1] to the riscv-openocd fork of
OpenOCD. They're all minor, so I'm squashing them into one review. The
changes are as follows:
- Add boundary scan TAP.
- Mention inconsistency of CPU ID between vendor SDK and real hardware.
- Specify that there's no MMU so we don't look for one at runtime.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Change-Id: Ie8033eff436d6dbdc3eab156769a8908ccb547f6
Reviewed-on: https://review.openocd.org/c/openocd/+/6959
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
drop unneeded reset-init event
The speed is set to 1800 kHz at initialization, but increases to 4000 kHz
before flash programming, with debugging continuing at this higher speed.
So, setting 4000 kHz from the start makes sense.
Change-Id: I6bccb5837c624943212b727368b40153e42ccebb
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9027
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
These target configs implement neither device clock setting
nor boost of adapter speed in reset-init event.
Therefore it's not necessary to set back the safe speed in reset-start
Change-Id: I7dcd6f6d1a977388c7a0bc45fe46ede955bd45cb
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9129
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Adds support for direct memory access via SWD emulation for AM64x and
J784s4 boards, configuring addresses and parameters required for
direct memory operations.
Change-Id: Iebc16612b3990b2ef19ddc4143b66ab1bcbfe0f3
Signed-off-by: Joao Lima <joao.lima@hbkworld.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9021
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Adds support for BL616 series of chips, BL616 and BL618.
No flash bank support yet.
BL616 in comparison with BL602-series have new architecture,
using T-Head E907 RISC-V cores, instead of SiFive ones.
As BL602-series, the ndmreset bit in RISC-V Debug Module
does not reset the chip as it should, so we need to do it
manually with registers almost the same way as in BL602.
Additionally, JTAG Debug Transport Module in the chip have wrongly
implemented Test-Logic-Reset state, causing automatic chain scan
not working at all after initial JTAG usage. This is because
Test-Logic-State do not set IR instruction to IDCODE,
as it should by JTAG spec. We can fix this by getting state machine
to known state and configure IR instruction manually to IDCODE.
This bug was so far found in T-Head C906 and E907 IP cores.
This patch was tested heavily and works reliably on
BL616, BL618 and QCC74X.
Change-Id: Idc80a702e817d78fc0ca925572c68d4d0c28ce4e
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9145
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The reset-init handler needs to call the ROM API function to enable
XIP from flash.
Correct syntax for this command is to supply two-letter function code
as the first argument, flash bank number sholudn't be there.
Reported-by: Thomas D. Dean <tomdean@wavecable.com>
Fixes: 376d11c2e3
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: I94713630300ead32bc9db6a1a77658fa5d5214d4
Reviewed-on: https://review.openocd.org/c/openocd/+/9134
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32U37/U38x devices have 1Mb flash (split into pages of 4 Kb)
Note: add wait for the BSY bit to be cleared in FLASH_SR
Change-Id: I8208aa81951b9e2f7b0a6bbfce3f7c8ad0f78ade
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8874
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Embedded flash also has a user signature area. This is a 512
bytes large page whose data are not erased by asserting ERASE pin or by
software ERASE command. It may be used to store configuration, keys,
trimming values etc.
This commit adds option to access this area from OpenOCD.
Change-Id: If870aa85938b9cccd94f958dd1f3d93dbdf779f0
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8302
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Processors.
QCS6490 and QCM6490 are 6nm processors designed for enterprise and IOT
applications featuring global 5G and Wi-Fi 6E support with similar
architecture.
This configuration file will allow debugging applications on these
processors.
Verified with Olimex(ARM-USB-OCD-H):
openocd -f tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg
-c 'transport select jtag'
-f <path_to_qcs6490_cfg>
and Jlink:
openocd -f tcl/interface/jlink.cfg
-c 'transport select jtag'
-f <path_to_qcs6490_cfg>
Change-Id: I05e923293134eaa9b70d3cf0d18efac9a024b6c7
Signed-off-by: Ashi Gupta <quic_ashig@quicinc.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8615
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The Rockchip RK3588 SoC is used in systems such as the GenBook RK3588
open-hardware laptop and the Coolpi CM5 compute module. This patch adds
support for debugging those. Tested using the ST-LINK/V2 debug adapter
in SWD mode connected to the SDMMC_D2 (SWCLK) and SDMMC_D3 (SWDIO) pins
on the 50-pin J17 connector inside the GenBook RK3588 laptop.
Change-Id: Ia5da403054b6c9aa41184a4e092a74aa882a267d
Signed-off-by: Andreas Dannenberg <andre@miauco.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9013
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Update jtag driver code to reflect these changes and properly drive
Angie probe.
The rationale behind this is to increase the probe performances,
especially in use cases when large files shall be loaded on a target.
The USB transfer performances are now close to those obtained with a
standard FTDI probe.
Change-Id: I3b31d75a3f66c2d07fed8c7423f765acc30925f8
Signed-off-by: Adrien Charruel <acharruel@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8711
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The max32xxx tcl files have been updated to work with the new flashing
algorithm. A new max32xxx.cfg file contains common configuration and
functionality.
Change-Id: Ifaed58836d221ece6192faafa382b30fb72c77a6
Signed-off-by: Henrik Mau <henrik.mau@analog.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8976
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add support for the targets stm32mp21x, stm32mp23x and stm32mp25x.
Add support for the boards stm32mp235f-dk and stm32mp257f-dk.
The board stm32mp215f-dk has no configuration file as it only
provides a generic JTAG/SWD connector for the stm32mp21x SoC.
Change-Id: I0256bebd8a5d5600066d8ae191d83344a35d3d37
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8985
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Align the target script to the handshake implemented in the latest
version of stm32wrapper4dbg to get access to the debug port.
Use hwthread with the SMP node.
Allow ignoring/masking some CPU from the configuration with the
variables EN_<cpu>.
Change-Id: I7117dd7df20b4f6b6e28f911e3e91ee763bdd200
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8984
Tested-by: jenkins
Align the target script to the handshake implemented in the latest
version of stm32wrapper4dbg to get access to the debug port.
Change-Id: Ia1c7773330fda776abb4385331fddbf431d11c39
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8983
Tested-by: jenkins
Move the existing files for STM32MP13x and STM32MP15x in the
folder "st".
Rename the board files using the correct names.
While there, add the missing URL to one of the boards.
Change-Id: If8b92f55e3390ebc75df6a2ea09fcf798ea0b8cf
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8982
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Microchip's PIC64GX Curiosity Board has a RISC-V core complex with 4
application processors and one monitor processor. The Curiosity kit also
has an on-board debug interface based around an FTDI 4232H device.
This patch adds basic target, interface and board support for PIC64GX
Curiosity Kit.
Change-Id: I2234d8725744fbae00b3909773b370e5c18debd8
Signed-off-by: Liam Fletcher <liam.fletcher@microchip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8878
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Microchip's PolarFire SoC has a RISC-V core complex with four
application processors and one monitor processor. This basic
configuration can be used to attach to all proccessor's or a single
processor, specified by the run-time argument $COREID
It can be used with most FTDI based debug interfaces and has been tested
with interface/ftdi/olimex-arm-usb-tiny-h.cfg.
Change-Id: I75dd965f1ce550807706d00fe17de887d36f0b02
Signed-off-by: Liam Fletcher <liam.fletcher@microchip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8877
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The Allwinner H618 is an updated H616 but appears functionally
equivalent. It is used in small boards such as Orange Pi Zero 3.
Change-Id: I299a42be746189f3e8e31070aa26b83ab7d806a4
Signed-off-by: Electric Worry <me@electricworry.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/8936
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
