A target reset can cause a power cycle, causing the DAP to switch
from SWD to JTAG. The adapter can loose the connection because it
keeps using SWD, triggering error messages.
While some ST-Link FW can automatically reconnect the lost SWD
connection, this is not possible with older FW nor with other
adapters.
Force a DAP initialization after reset to eventually switch it
back to SWD.
Change-Id: I29ea49d2d5ee013ad33371265fd6996353f391d6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9462
Tested-by: jenkins
reset-assert of network CPU should be handled by empty dummy handler
to prevent the Cortex-M target native processing. Unfortunately configuring
the empty string does not define a new handler, it drops the existing one.
Use semicolon to fix configuration and to make the emtpy handler
clearly visible.
Fixes: commit 17be341d38 ("tcl/target: add nRF53 and nRF91 config files")
Reported-by: Lawrence King <lawrencek52@gmail.com>
Change-Id: I3bd229a78860ed05d694e708ab62cb1670a77010
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9492
Tested-by: jenkins
Reviewed-by: Lawrence King <lawrencek52@gmail.com>
The STM32U0xx devices support only SWD.
Add swd transport in the target file.
Remove swd transport from the associated board files.
Change-Id: I2d31856951d15fcf2d1986ee5b1b31464e68db1c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9427
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Ahmed Haoues <ahmed.haoues@st.com>
The STM32L0xx devices support only SWD.
Drop swj support.
Add swd transport.
Remove swd transport from the associated board files.
Change-Id: I5f8fb4344b33f8bdefd67fd86326f4dccb674d92
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9426
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Ahmed Haoues <ahmed.haoues@st.com>
Tested-by: jenkins
The datasheets for all STM32G0xx devices report that only SWD is
supported. No TDI/TDO pin is present.
Drop swj support.
Add swd transport.
Remove swd transport from the associated board files.
Change-Id: Ib29171dd614eb84346e90cb447bc7292465095ac
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9425
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Ahmed Haoues <ahmed.haoues@st.com>
The datasheets for all STM32F0xx devices report that only SWD is
supported. No TDI/TDO pin is present.
Drop swj support.
Add swd transport.
Remove swd transport from the associated board files.
Change-Id: I65a08b6a441d794aa209cff8583a971d3546f49e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9424
Reviewed-by: Ahmed Haoues <ahmed.haoues@st.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The datasheets for all STM32C0xx devices report that only SWD is
supported. No TDI/TDO pin is present.
Drop swj support.
Add swd transport.
Remove swd transport from the associated board files.
Change-Id: If6e630858aa64fbb3938a520604748f3f0ff7356
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9423
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Ahmed Haoues <ahmed.haoues@st.com>
Tested-by: jenkins
Historically swj_newdap was necessary to handle HLA properly
Since commit 60f104f450 ("hla_transport: split command
registration per transport") there is no point in using
swj_newdap on SWD only devices.
There are no relevant board files.
Change-Id: I2119e0c0895ca97895ade92a1b1becef6bd6cfdb
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9438
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Historically swj_newdap was necessary to handle HLA properly
Since commit 60f104f450 ("hla_transport: split command
registration per transport") there is no point in using
swj_newdap on SWD only devices.
There are no relevant board files.
Change-Id: Id66a808475f061307fc6a0b3e0d2a9840b543e7f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9437
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Historically swj_newdap was necessary to handle HLA properly.
Since commit 60f104f450 ("hla_transport: split command
registration per transport") there is no point in using
swj_newdap on SWD only devices.
There are no relevant board files.
Change-Id: I7ff7b2dee316c10a24e2ab38f8c03f504295d868
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9436
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Historically swj_newdap was necessary to handle HLA properly.
Since commit 60f104f450 ("hla_transport: split command
registration per transport") there is no point in using
swj_newdap on SWD only devices.
Drop 'transport select swd' from board files referring to
these targets.
While on it remove useless endianness option handling.
Change-Id: Icb4c04c79998369059044c203edcca61648aa936
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9435
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Historically swj_newdap was necessary to handle HLA properly.
Since commit 60f104f450 ("hla_transport: split command
registration per transport") there is no point in using
swj_newdap on SWD only devices.
No board files referring these targets select swd transport.
Change-Id: I002ce7029936f56b1d8b41505bca8dc771c33187
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9434
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Historically swj_newdap was necessary to handle HLA properly.
Since commit 60f104f450 ("hla_transport: split command
registration per transport") there is no point in using
swj_newdap on SWD only devices.
No board files referring these targets select swd transport.
While on it remove useless endianness option handling.
Change-Id: I3b47750cc69fc9009fdd4cfdccfc213792d1b7ee
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9433
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Historically swj_newdap was necessary to handle HLA properly.
Since commit 60f104f450 ("hla_transport: split command
registration per transport") there is no point in using
swj_newdap on SWD only devices.
Change-Id: Ib4d7eb5935e0b44087cc8ea73ab187a417413db6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9421
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The MSPM0 devices support only SWD.
Drop swj support, add swd support.
This also gets rid of the following warnings:
Warn : DEPRECATED: auto-selecting transport "swd". Use 'transport ...
Warn : Transport "swd" was already selected
Tested by programming/verifying firmware on LP-MSPM0G3519 dev board.
Change-Id: Ieafd9c4691343124b2dfb2daa1c0d3a96b13e485
Signed-off-by: Mikhail Iakhiaev <iakhiaev@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9413
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Move the configuration files into a dedicated vendor folder as required
by the developer guidelines.
Change-Id: I9ed39e32b6281a9cb8510914690f3f7751b795c8
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9271
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Corrected the include path for max32xxx_common.cfg in some files.
Cleaned up and standarised some comments in the max32... files.
Change-Id: I94dcc7ba6868bdd9730f03d3aa76fcdbbae33c3e
Signed-off-by: Mark O'Donovan <shiftee@posteo.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/9323
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The assignment of adapter speed 500 was getting overwritten when
max32xxx_common.cfg is sourced at the end.
Also removed incorrect comment.
Change-Id: I49d69073d93dedf28ed69d63ece35758f4707137
Signed-off-by: Mark O'Donovan <shiftee@posteo.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/9322
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Prepare to add stm32wba6x support.
The OTP address is different between the stm32wb5xxx and stm32wb6xxx
microcontrollers, so the configuration file can't be the same for both.
Change-Id: Ib7485e0211779d98cca56e73397197b712460c69
Signed-off-by: Guillaume Faussard <guillaume.faussard@withings.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9326
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Ahmed Haoues <ahmed.haoues@st.com>
Initial release of Flash bank driver for Bouffalo chips.
The driver currently supports BL602, BL702, BL702L series of chips.
Similar SFlash core is inside of BL808, BL606P and BL616 series,
so those might be supported in future as well.
With adapter speed set to 8000, it can reach speed 140 KiB/s.
Since chips have eXecute In Place support, and they also require
boot config in Flash at offset 0x0, it's required to have properly
crafted linker script, so OpenOCD knows where to write firmware
through gdb.
There is required flash bank parameter, which specifies the chip type.
This is required because BL702 and BL702L have same TAP ID CODE, and
there are no usable indicators to use for automatic chip type
recognition in the chip.
Change-Id: Id57336d447be3c608b39ba3ed143527bfdc0af98
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8527
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Configure reset-start event to set/clear DM resethaltreq bit.
In reset-assert event check if srst is configured.
Avoid unnecessary double reset if srst is configured.
Write dmcontrol ackhavereset in reset-deassert-post event if necessary.
Change-Id: I06b201bc5651c301912158c1436b9b3e3bc042a0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9316
Reviewed-by: Tom Hebb <tommyhebb@gmail.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The pluggable reset events are invoked only in the context of
proc ocd_process_reset_inner, so we can use $halt variable
directly and avoid proc init_reset redefinition.
Change-Id: Ie74c340c51cb2c55d8ffc9f74bb1a1a8e3461515
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9315
Tested-by: jenkins
Reviewed-by: Tom Hebb <tommyhebb@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The GD32VF103 has a perculiar reset procedure that does not fully comply
with the RISC-V Debug Specification.
Move the workaroung to the `deassert-reset-post` handler.
Change-Id: I153c866a5b7e2dff2552cc92772ce6ed77ad606b
Signed-off-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9314
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
stm32f334k8 only has 12kbytes of SRAM and
flashing with the default WORKAREA of 16kbytes
will fail for images > 12k.
Change-Id: If9be0b0e7cd6e4ba15a130d8e06c74e4a0e22a61
Signed-off-by: Maximilian Schneider <max@schneidersoft.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/9283
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Move the ti targets to a TI folder. Since the folder is ti, we can
drop the "ti" prefix from the files themselves.
Done via the following script:
mkdir target/ti
FILES=`ls target/ti*.cfg target/omap*.cfg target/am335x.cfg
target/amdm37x.cfg target/icepick.cfg target/stellaris.cfg
target/davinci.cfg`
for cname in $FILES
do
bname=`basename $cname`
nname=`echo $bname|sed -e "s/^ti-//g"|sed -e "s/ti_//g"`
npath="target/ti/$nname"
echo "$cname => $npath"
fref=`git grep $cname .|cut -d ':' -f1|sort -u`
sed -i -e "s&$cname&$npath&g" $fref
git mv $cname $npath
done
Change-Id: I9f94dc6bb01f73721d4ff96be92cb51de2cbf0e2
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9203
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For stm32l4, stm32wbx, stm32wlx the target tcl scripts try to change the
MSI oscillator's speed to 24 MHz before boosting the interface
frequency, but don't clear the RCC_CR_MSIRANGE field correctly before.
This causes the register write access to fail and leaves the clock
frequency unchanged. For the stm32wlx, the script also neglects to set
the MSIRGSEL bit, such that the frequency setting is not actually
applied.
The issue appears to not cause a problem when using an ST-Link adapter.
When using an FT4232HP, communication to the target fails after the
reset-init event, possibly because this adapter actually supports the
higher interface frequency.
This commit fixes the register accesses to make sure the RCC_CR_MSIRANGE
is cleared to zero before OR-ing the new value. For the stm32wlx, also
set the MSIRGSEL bit. Just to be safe, also fix the write access to the
FLASH_ACR_LATENCY field to clear it before OR-ing, even though it should
be zero at reset anyways.
Change-Id: Ie8320fa6ee2086981c0b1f3c18f51e171709078d
Signed-off-by: Niklas Gürtler <profclonk@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9282
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
These changes bring over some lines from the independently-developed
gd32vf103.cfg that I contributed[1] to the riscv-openocd fork of
OpenOCD. They're all minor, so I'm squashing them into one review. The
changes are as follows:
- Add boundary scan TAP.
- Mention inconsistency of CPU ID between vendor SDK and real hardware.
- Specify that there's no MMU so we don't look for one at runtime.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Change-Id: Ie8033eff436d6dbdc3eab156769a8908ccb547f6
Reviewed-on: https://review.openocd.org/c/openocd/+/6959
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
drop unneeded reset-init event
The speed is set to 1800 kHz at initialization, but increases to 4000 kHz
before flash programming, with debugging continuing at this higher speed.
So, setting 4000 kHz from the start makes sense.
Change-Id: I6bccb5837c624943212b727368b40153e42ccebb
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9027
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
These target configs implement neither device clock setting
nor boost of adapter speed in reset-init event.
Therefore it's not necessary to set back the safe speed in reset-start
Change-Id: I7dcd6f6d1a977388c7a0bc45fe46ede955bd45cb
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9129
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Adds support for direct memory access via SWD emulation for AM64x and
J784s4 boards, configuring addresses and parameters required for
direct memory operations.
Change-Id: Iebc16612b3990b2ef19ddc4143b66ab1bcbfe0f3
Signed-off-by: Joao Lima <joao.lima@hbkworld.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9021
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Adds support for BL616 series of chips, BL616 and BL618.
No flash bank support yet.
BL616 in comparison with BL602-series have new architecture,
using T-Head E907 RISC-V cores, instead of SiFive ones.
As BL602-series, the ndmreset bit in RISC-V Debug Module
does not reset the chip as it should, so we need to do it
manually with registers almost the same way as in BL602.
Additionally, JTAG Debug Transport Module in the chip have wrongly
implemented Test-Logic-Reset state, causing automatic chain scan
not working at all after initial JTAG usage. This is because
Test-Logic-State do not set IR instruction to IDCODE,
as it should by JTAG spec. We can fix this by getting state machine
to known state and configure IR instruction manually to IDCODE.
This bug was so far found in T-Head C906 and E907 IP cores.
This patch was tested heavily and works reliably on
BL616, BL618 and QCC74X.
Change-Id: Idc80a702e817d78fc0ca925572c68d4d0c28ce4e
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9145
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The reset-init handler needs to call the ROM API function to enable
XIP from flash.
Correct syntax for this command is to supply two-letter function code
as the first argument, flash bank number sholudn't be there.
Reported-by: Thomas D. Dean <tomdean@wavecable.com>
Fixes: 376d11c2e3
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: I94713630300ead32bc9db6a1a77658fa5d5214d4
Reviewed-on: https://review.openocd.org/c/openocd/+/9134
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32U37/U38x devices have 1Mb flash (split into pages of 4 Kb)
Note: add wait for the BSY bit to be cleared in FLASH_SR
Change-Id: I8208aa81951b9e2f7b0a6bbfce3f7c8ad0f78ade
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8874
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Embedded flash also has a user signature area. This is a 512
bytes large page whose data are not erased by asserting ERASE pin or by
software ERASE command. It may be used to store configuration, keys,
trimming values etc.
This commit adds option to access this area from OpenOCD.
Change-Id: If870aa85938b9cccd94f958dd1f3d93dbdf779f0
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8302
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Processors.
QCS6490 and QCM6490 are 6nm processors designed for enterprise and IOT
applications featuring global 5G and Wi-Fi 6E support with similar
architecture.
This configuration file will allow debugging applications on these
processors.
Verified with Olimex(ARM-USB-OCD-H):
openocd -f tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg
-c 'transport select jtag'
-f <path_to_qcs6490_cfg>
and Jlink:
openocd -f tcl/interface/jlink.cfg
-c 'transport select jtag'
-f <path_to_qcs6490_cfg>
Change-Id: I05e923293134eaa9b70d3cf0d18efac9a024b6c7
Signed-off-by: Ashi Gupta <quic_ashig@quicinc.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8615
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The Rockchip RK3588 SoC is used in systems such as the GenBook RK3588
open-hardware laptop and the Coolpi CM5 compute module. This patch adds
support for debugging those. Tested using the ST-LINK/V2 debug adapter
in SWD mode connected to the SDMMC_D2 (SWCLK) and SDMMC_D3 (SWDIO) pins
on the 50-pin J17 connector inside the GenBook RK3588 laptop.
Change-Id: Ia5da403054b6c9aa41184a4e092a74aa882a267d
Signed-off-by: Andreas Dannenberg <andre@miauco.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9013
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
