Replace "_" file separator with "-" file separator as recommended by
coding standards guidelines. While doing this, add the files that were
present in previous v0.12.0 release to file_renaming.cfg for this
non-trivial rename.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I88685f08f4a0cc580fa3b03f6db0d85061d65b94
Reviewed-on: https://review.openocd.org/c/openocd/+/9236
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Rename the _swd_native.cfg files as -self-hosted.cfg files as a better
representation of what we are using the configuration files to be.
Change-Id: I4eb469a219b83de6a9e7a8dfef5607306f59a7cd
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9206
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
As part of the cfg file cleanups, let us move the TI evms, launchpads
and other development platform configuration files to board/ti folder.
While at this, drop the "ti_" prefix as the folder structure gives us
the details anyways.
Change-Id: I929b88e0cf6527f3181820ad0b9b4744185eabaf
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9205
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Move the BeagleBoard.org Foundation boards to it's own folder. This
allows additional support such as BeagleV-Fire and other non TI SoC
vendor support to be subsequently added.
While doing this,
* Use "-" as separator for the file names as recommended
by coding standards.
* To maintain compatibility, add the non-trivial renames to
file_renaming.cfg
Change-Id: Ie916c9bf81fc3922bf19ed9ed2db841549d29ca9
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9204
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Move the ti targets to a TI folder. Since the folder is ti, we can
drop the "ti" prefix from the files themselves.
Done via the following script:
mkdir target/ti
FILES=`ls target/ti*.cfg target/omap*.cfg target/am335x.cfg
target/amdm37x.cfg target/icepick.cfg target/stellaris.cfg
target/davinci.cfg`
for cname in $FILES
do
bname=`basename $cname`
nname=`echo $bname|sed -e "s/^ti-//g"|sed -e "s/ti_//g"`
npath="target/ti/$nname"
echo "$cname => $npath"
fref=`git grep $cname .|cut -d ':' -f1|sort -u`
sed -i -e "s&$cname&$npath&g" $fref
git mv $cname $npath
done
Change-Id: I9f94dc6bb01f73721d4ff96be92cb51de2cbf0e2
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9203
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For stm32l4, stm32wbx, stm32wlx the target tcl scripts try to change the
MSI oscillator's speed to 24 MHz before boosting the interface
frequency, but don't clear the RCC_CR_MSIRANGE field correctly before.
This causes the register write access to fail and leaves the clock
frequency unchanged. For the stm32wlx, the script also neglects to set
the MSIRGSEL bit, such that the frequency setting is not actually
applied.
The issue appears to not cause a problem when using an ST-Link adapter.
When using an FT4232HP, communication to the target fails after the
reset-init event, possibly because this adapter actually supports the
higher interface frequency.
This commit fixes the register accesses to make sure the RCC_CR_MSIRANGE
is cleared to zero before OR-ing the new value. For the stm32wlx, also
set the MSIRGSEL bit. Just to be safe, also fix the write access to the
FLASH_ACR_LATENCY field to clear it before OR-ing, even though it should
be zero at reset anyways.
Change-Id: Ie8320fa6ee2086981c0b1f3c18f51e171709078d
Signed-off-by: Niklas Gürtler <profclonk@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9282
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
These changes bring over some lines from the independently-developed
gd32vf103.cfg that I contributed[1] to the riscv-openocd fork of
OpenOCD. They're all minor, so I'm squashing them into one review. The
changes are as follows:
- Add boundary scan TAP.
- Mention inconsistency of CPU ID between vendor SDK and real hardware.
- Specify that there's no MMU so we don't look for one at runtime.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Change-Id: Ie8033eff436d6dbdc3eab156769a8908ccb547f6
Reviewed-on: https://review.openocd.org/c/openocd/+/6959
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
cJTAG OSCAN1, in lieu of 4-wire JTAG, is starting to be a configuration
option for some SiFive hardware. An FTDI-based adapter that can be
configured to drive the bidirectional pin TMSC is assumed for this
topology. Specifically, the Olimex ARM-USB-TINY-H with the ARM-JTAG-SWD
adapter, connected to a SiFive cJTAG-enabled target board is the only
known concrete topology, currently. But in theory, other FTDI based
devices that can drive a two-wire bidirectional signaling pattern could
be made to work in this scheme in the future.
These code changes are offered as a way to drive that topology. It's
translating IR/DR and JTAG traversal commands to the two-wire clocking
and signaling.
See:
- https://github.com/riscv-collab/riscv-openocd/pull/320
- https://github.com/riscv-collab/riscv-openocd/pull/736
Signed-off-by: Greg Savin <greg.savin@sifive.com>
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Change-Id: Ia1daa2c01227c4b0005be947b2bb0de81a800874
Reviewed-on: https://review.openocd.org/c/openocd/+/6981
Tested-by: jenkins
Change 7732: jtag/drivers/bcm2835gpio: Support all 54 GPIO pins [1]
reduces the time needed for GPIO handling.
Adjust the speed offsets to the new and faster bcm2835gpio code.
Measured with Sigrok/PulseView, sampled at 800 MHz.
Configured as SWD with the fast path in the driver - other
modes are expected to be slower.
Adjusted to keep all half periods of SWCLK in the sampled poll
sequence longer or equal than the half period of the nominal
adapter speed.
Link: [1] https://review.openocd.org/c/openocd/+/7732
Change-Id: Ia9e932dfd7547c8011c1d20d9e90bc0294050e8a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9234
Tested-by: jenkins
Reviewed-by: Vincent Fazio <vfazio@gmail.com>
drop unneeded reset-init event
The speed is set to 1800 kHz at initialization, but increases to 4000 kHz
before flash programming, with debugging continuing at this higher speed.
So, setting 4000 kHz from the start makes sense.
Change-Id: I6bccb5837c624943212b727368b40153e42ccebb
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9027
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
These target configs implement neither device clock setting
nor boost of adapter speed in reset-init event.
Therefore it's not necessary to set back the safe speed in reset-start
Change-Id: I7dcd6f6d1a977388c7a0bc45fe46ede955bd45cb
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9129
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Adds support for direct memory access via SWD emulation for AM64x and
J784s4 boards, configuring addresses and parameters required for
direct memory operations.
Change-Id: Iebc16612b3990b2ef19ddc4143b66ab1bcbfe0f3
Signed-off-by: Joao Lima <joao.lima@hbkworld.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9021
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Remove the configuration file, a replacement is already available.
Link the old filename to the new configuration file to ensure backwards
compatibility.
Change-Id: I77cbd62d805b1c9b9bb8f56a823c3f6476d1a5a9
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9150
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Remove the configuration file, a replacement is already available.
Link the old filename to the new configuration file to ensure backwards
compatibility.
Change-Id: I11361e471bb7ec277a850f956e51cd7d0fab408d
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9149
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Adds support for BL616 series of chips, BL616 and BL618.
No flash bank support yet.
BL616 in comparison with BL602-series have new architecture,
using T-Head E907 RISC-V cores, instead of SiFive ones.
As BL602-series, the ndmreset bit in RISC-V Debug Module
does not reset the chip as it should, so we need to do it
manually with registers almost the same way as in BL602.
Additionally, JTAG Debug Transport Module in the chip have wrongly
implemented Test-Logic-Reset state, causing automatic chain scan
not working at all after initial JTAG usage. This is because
Test-Logic-State do not set IR instruction to IDCODE,
as it should by JTAG spec. We can fix this by getting state machine
to known state and configure IR instruction manually to IDCODE.
This bug was so far found in T-Head C906 and E907 IP cores.
This patch was tested heavily and works reliably on
BL616, BL618 and QCC74X.
Change-Id: Idc80a702e817d78fc0ca925572c68d4d0c28ce4e
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9145
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The reset-init handler needs to call the ROM API function to enable
XIP from flash.
Correct syntax for this command is to supply two-letter function code
as the first argument, flash bank number sholudn't be there.
Reported-by: Thomas D. Dean <tomdean@wavecable.com>
Fixes: 376d11c2e3
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: I94713630300ead32bc9db6a1a77658fa5d5214d4
Reviewed-on: https://review.openocd.org/c/openocd/+/9134
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
pico-debug and pico2-debug are virtual CMSIS-DAP adapters that
run on the otherwise dormant second core of the RP2040 and RP2350
respectively.
Change-Id: Ifd7dcbbabeb86c738cc58854add0e897633197de
Signed-off-by: Peter Lawrence <majbthrd@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9099
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Make the driver more flexible and define adapter-specific configurations
in Tcl instead of C using the adapter GPIO subsystem.
The rework also includes coding style fixes and improvements of the
documentation. All modifications are done such that backwards
compatibility is ensured.
Tested with Olimex ARM-JTAG cable [1] and APM32F103 target device on
Linux and FreeBSD. The driver works on Linux using direct I/O and PPDEV.
On FreeBSD, only PPDEV works. The build with direct I/O already failed
before the patch. This problem will be fixed in a subsequent patch.
The patch is not tested on Windows because there is no documentation
for it.
[1] https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG/
Change-Id: Ib671d52a919eaf2959cf6365f2c8004257ae074c
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8943
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Create a new backend for cmsis_dap driver that allows CMSIS-DAP protocol
to run over TCP/IP instead of USB.
An example implementation of the firmware for an SWD programmer that
uses this cmsis_dap_tcp protocol can be found at the link below.
https://github.com/bkuschak/cmsis_dap_tcp_esp32
Using this cmsis_dap_tcp backend with the firmware above on an ESP32-C6
programmer and STM32F401RE target shows the following performance:
- loading 96KB image to RAM: 80 KB/sec
- dumping 96KB image from RAM: 72 KB/sec
- flashing 512KB image completes in about 13.5 seconds (including erase,
program, and verify).
Change-Id: I6e3e45016bd16ef2259561b1046788f5536b0687
Signed-off-by: Brian Kuschak <bkuschak@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8973
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
STM32U37/U38x devices have 1Mb flash (split into pages of 4 Kb)
Note: add wait for the BSY bit to be cleared in FLASH_SR
Change-Id: I8208aa81951b9e2f7b0a6bbfce3f7c8ad0f78ade
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8874
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Embedded flash also has a user signature area. This is a 512
bytes large page whose data are not erased by asserting ERASE pin or by
software ERASE command. It may be used to store configuration, keys,
trimming values etc.
This commit adds option to access this area from OpenOCD.
Change-Id: If870aa85938b9cccd94f958dd1f3d93dbdf779f0
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8302
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Move the configuration files into a dedicated vendor folder as required
by the developer guidelines.
Change-Id: I5bf048f2d8d0fccbcfe40e0a0e7b30dfbab192d1
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9082
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Processors.
QCS6490 and QCM6490 are 6nm processors designed for enterprise and IOT
applications featuring global 5G and Wi-Fi 6E support with similar
architecture.
This configuration file will allow debugging applications on these
processors.
Verified with Olimex(ARM-USB-OCD-H):
openocd -f tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg
-c 'transport select jtag'
-f <path_to_qcs6490_cfg>
and Jlink:
openocd -f tcl/interface/jlink.cfg
-c 'transport select jtag'
-f <path_to_qcs6490_cfg>
Change-Id: I05e923293134eaa9b70d3cf0d18efac9a024b6c7
Signed-off-by: Ashi Gupta <quic_ashig@quicinc.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8615
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The Rockchip RK3588 SoC is used in systems such as the GenBook RK3588
open-hardware laptop and the Coolpi CM5 compute module. This patch adds
support for debugging those. Tested using the ST-LINK/V2 debug adapter
in SWD mode connected to the SDMMC_D2 (SWCLK) and SDMMC_D3 (SWDIO) pins
on the 50-pin J17 connector inside the GenBook RK3588 laptop.
Change-Id: Ia5da403054b6c9aa41184a4e092a74aa882a267d
Signed-off-by: Andreas Dannenberg <andre@miauco.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9013
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Update jtag driver code to reflect these changes and properly drive
Angie probe.
The rationale behind this is to increase the probe performances,
especially in use cases when large files shall be loaded on a target.
The USB transfer performances are now close to those obtained with a
standard FTDI probe.
Change-Id: I3b31d75a3f66c2d07fed8c7423f765acc30925f8
Signed-off-by: Adrien Charruel <acharruel@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8711
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The max32xxx tcl files have been updated to work with the new flashing
algorithm. A new max32xxx.cfg file contains common configuration and
functionality.
Change-Id: Ifaed58836d221ece6192faafa382b30fb72c77a6
Signed-off-by: Henrik Mau <henrik.mau@analog.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8976
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add a board configuration file for the MikroElektronika Clicker 4 for
STM32F745VG (MIKROE-6331), which contains their CMSIS-DAP-compatible
on-board CODEGRIP programmer.
Place this into its own subdirectory, since MikroElektronika has quite a
few boards in their portfolio.
Change-Id: If24ca286d65e024f3c3a8522b67727e268ab0bc9
Signed-off-by: Ondřej Hošek <ondra.hosek@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8997
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add support for the targets stm32mp21x, stm32mp23x and stm32mp25x.
Add support for the boards stm32mp235f-dk and stm32mp257f-dk.
The board stm32mp215f-dk has no configuration file as it only
provides a generic JTAG/SWD connector for the stm32mp21x SoC.
Change-Id: I0256bebd8a5d5600066d8ae191d83344a35d3d37
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8985
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Align the target script to the handshake implemented in the latest
version of stm32wrapper4dbg to get access to the debug port.
Use hwthread with the SMP node.
Allow ignoring/masking some CPU from the configuration with the
variables EN_<cpu>.
Change-Id: I7117dd7df20b4f6b6e28f911e3e91ee763bdd200
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8984
Tested-by: jenkins
Align the target script to the handshake implemented in the latest
version of stm32wrapper4dbg to get access to the debug port.
Change-Id: Ia1c7773330fda776abb4385331fddbf431d11c39
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8983
Tested-by: jenkins
Move the existing files for STM32MP13x and STM32MP15x in the
folder "st".
Rename the board files using the correct names.
While there, add the missing URL to one of the boards.
Change-Id: If8b92f55e3390ebc75df6a2ea09fcf798ea0b8cf
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8982
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Microchip's PIC64GX Curiosity Board has a RISC-V core complex with 4
application processors and one monitor processor. The Curiosity kit also
has an on-board debug interface based around an FTDI 4232H device.
This patch adds basic target, interface and board support for PIC64GX
Curiosity Kit.
Change-Id: I2234d8725744fbae00b3909773b370e5c18debd8
Signed-off-by: Liam Fletcher <liam.fletcher@microchip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8878
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Microchip's PolarFire SoC has a RISC-V core complex with four
application processors and one monitor processor. This basic
configuration can be used to attach to all proccessor's or a single
processor, specified by the run-time argument $COREID
It can be used with most FTDI based debug interfaces and has been tested
with interface/ftdi/olimex-arm-usb-tiny-h.cfg.
Change-Id: I75dd965f1ce550807706d00fe17de887d36f0b02
Signed-off-by: Liam Fletcher <liam.fletcher@microchip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8877
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
