Commit 4afa32ece1 ("aarch64: unify armv7-a and armv8
debug entry decoding")
probably unintentionally removed DSCR_ENTRY_VECT_CATCH from
reported debug entry reasons. Note the discrepancy between
'case DSCR_ENTRY_BKPT_INSTR:' and its comment.
Hitting vector catch was reported as DBG_REASON_UNDEFINED.
DBG_REASON_UNDEFINED disturbed hwthread/gdb cooperation and
gdb reported the wrong thread as stopped by SIGTRAP.
Revert to the original functionality and report vector
catch as a breakpoint.
Change-Id: I12e938182cff8f633decba340000cfbb7b112ae3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9209
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
gdb uses this mark when creating a dummy frame for
manual call of a function by gdb command.
With the original setting all registers as caller_save = false
call command in gdb always clobbers r0, r1 and pc
and some other registers depending on the called function.
Set 'save-restore' for all registers but banked ones.
Change-Id: I16c49e4bf8001e38d18ce8861ca65988b08ccc88
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9208
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Commit b5d2b1224f ("target/cortex_a: add hypervisor mode")
added sp_hyp, spsr_hyp registers with gdb_index 51 and 52
but did not moved FP regs enum base starting from 51.
Move FP registers indices to make room for added registers.
Change-Id: I4338777545918fdf62016e06764308dacea61e98
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9235
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Switch to LOG_TARGET_DEBUG() and LOG_TARGET_ERROR()
to make analyzing logs of multicore system easier.
Not changed completely in the whole file, the changes were focused
to halt and resume.
Change-Id: I055ad682d3098d5c301a111605d57e504f877b4c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9207
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Change 7732: jtag/drivers/bcm2835gpio: Support all 54 GPIO pins [1]
reduces the time needed for GPIO handling.
Adjust the speed offsets to the new and faster bcm2835gpio code.
Measured with Sigrok/PulseView, sampled at 800 MHz.
Configured as SWD with the fast path in the driver - other
modes are expected to be slower.
Adjusted to keep all half periods of SWCLK in the sampled poll
sequence longer or equal than the half period of the nominal
adapter speed.
Link: [1] https://review.openocd.org/c/openocd/+/7732
Change-Id: Ia9e932dfd7547c8011c1d20d9e90bc0294050e8a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9234
Tested-by: jenkins
Reviewed-by: Vincent Fazio <vfazio@gmail.com>
Previously, only the first 32 GPIO were supported on the BCM2835.
Performance was cited as being the primary justification for not
supporting all 54 pins, notably:
1. There is overhead for calculating the memory offset for the pin
2. GPIO values cannot be written in bulk if pins span memory offsets
Now, all 54 GPIO pins are supported by the driver.
Since pins may use different offsets, multiple pins cannot be toggled
with one memory store. Multiple stores now need to occur when one
sufficed before.
To offset some of the performance overhead for the additional stores,
memory addresses, masks, and shift bits are calculated once and cached
into struct. Calculating these once reduces the number of instructions
a function needs to run in order to manipulate a given GPIO.
The following functions have been updated to leverage the new struct
as they represent some of the hottest paths:
bcm2835_swdio_drive
bcm2835_swdio_read
bcm2835gpio_swd_write_fast
bcm2835gpio_read
bcm2835gpio_write
For `bcm2835gpio_swd_write_fast`, performance should be roughly the same
as the number of memory stores hasn't changed.
For `bcm2835_write`, there is a slight performance degradation since
TMS/TDI/TCK are set separately which incurs an additional memory store.
Instruction counts across the above functions are reduced by ~10-40%.
Macros to access registers have been reworked into inline functions to
support access to all pins and to avoid checkpatch headaches.
The `initial_gpio_state.output_level` member has been retyped to bool to
better align with the expected values.
Support for adjusting pads for the expanded pin range has been left out
as support for manipulating these settings should be moved out of this
driver and into its own utility.
Change-Id: I18853d1a2c86776658630326c71a6bf236fcc6da
Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7732
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Restarting the program buffer memory write pipeline when the write of
the last element resulted in the busy response triggers an extra memory
wrtite, that is cought by an assertion:
```
src/target/riscv/riscv-013.c:5048: write_memory_progbuf_inner: Assertion
`next_addr_on_target - args.address <= (target_addr_t)args.size *
args.count' failed.
```
Change-Id: I0f27145cad24686cf539aebfea7f6578b7cd78ab
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9233
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This is a cherry-pick of:
Link: efce094b40
Fake step is a hack introduced to make things work with real RTOSs that
have a concept of a current thread. The hwthread rtos always has access
to all threads, so doesn't need it.
This fixes a bug when running my MulticoreRegTest against HiFive
Unleashed where OpenOCD would return the registers of the wrong thread
after gdb stepped a hart.
Change-Id: I64f538a133fb078c05a0c6b8121388b0b9d7f1b8
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9177
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
For all the targets that support SMP, the sub-commands 'smp' and
'smp_gdb' are under the arch name:
- aarch64 smp
- cortex_a smp
- cortex_m smp
- esp32 smp
- mips_m4k smp
Keep consistency among OpenOCD commands, and move under the arch
name 'riscv' the SMP subcommands.
Change-Id: Iede7841c2df8161ff2c6fea3be561d1f26ad6cd0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9165
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
The buffer 'args' is allocated and freed in the caller function
parse_reg_ranges().
There is no reason to free it, only in some special case, in the
called function parse_reg_ranges_impl().
Scan build reports:
src/target/riscv/riscv.c:4537:2: warning: Attempt to free
released memory [unix.Malloc]
Drop the free() in the called function.
Change-Id: I2e308670c502f8e140603b4e5c16fc568088e1a8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9164
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The array 'wps_to_enable' is never freed.
Scan build reports:
src/target/riscv/riscv.c:4271:6: warning: Potential leak
of memory pointed to by 'wps_to_enable' [unix.Malloc]
Add the needed free().
While there, check if the allocation is successful.
Change-Id: I00e7ade37a43a97dcc245113ad93c48784fce609
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9163
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Now that the whole code is aligned with the coding style, enforce
the check through checkpatch.
Change-Id: Ie74ed98c5dfa61978d5551b60eb90acf746a3cc5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9057
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1274
From: Sriram Shanmuga <sriramharshalee@gmail.com>
RISC-V Debug Specification v1.0 [3.14.22. System Bus Access Control and
Status (`sbcs`, at 0x38)] states in `sbasize` field description:
> Width of system bus addresses in bits. (0 indicates there is no bus
access support.)
Before the patch, the error message did not include the information
about `sbcs.sbasize` being zero wich made it quite undescriptive:
```
[riscv.cpu] Turning off memory sampling because it failed.
```
Fixes#1270
Change-Id: I5402dd57dc9a81f65ee4c67d24e11c366006427c
Signed-off-by: Sriram Shanmuga <sriramharshalee@gmail.com>
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9142
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
If it fails, then pass that failure on. If it's simply not implemented,
then we can fall through and try target_get_gdb_reg_list_noread().
This difference matters when the target representing the current
hwthread is unavailable, but the target that is linked to the gdb
connection is available. In that case we want the operation to return an
error to gdb, instead of reading the register from the target that is
available.
Change-Id: I9c84ca556f818c5580e25ab349a34a226fcf0f43
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9138
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
'smp' and 'smp_gdb' command do not have 'riscv' prefix.
Document 'riscv use_bscan_tunnel' and 'riscv set_bscan_tunnel_ir'
as {Config Command}
Change-Id: I7b57613c9fedcccd6d6b1438d7fc2d28ea34ba65
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9133
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
in command 'riscv resume_order' to prevent segfault
on issuing the command without a parameter.
Change-Id: I5d7f4f92c2fa8e9effaba2c000d111e491b7b64f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9132
Tested-by: jenkins
In the riscv fork, [1] has disable the debug log during target
polling, with message:
Improve low-level logging.
Now logging is consistent and more readable.
I did remove most logging during riscv_poll() since it clutters
up the log/screen and is not generally helpful.
This is questionable, because if the user enables the debug log,
the messages should all be logged.
Drop the code that overwrites the 'debug_level'.
Link: https://github.com/riscv-collab/riscv-openocd/commit/54c65a9a4b71 [1]
Change-Id: Ia86b998cf654760f36c2f217d44bcb9ffd9c3a94
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9072
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The coding style requires the 'case' to be at the same indentation
level of its 'switch' statement.
Align the code accordingly.
While there, put at newline the command after the 'case'.
No changes are reported by
git log -p -w --ignore-blank-lines --patience
apart from the newline after 'case'.
Change-Id: Id856e24100de6fb0442afe8bc51545b0138ef02d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9069
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The advantage of this patch is that it brings the new code closer to
OpenOCD coding style - the disadvantage is that it involves modifying
autogenerated files, making it harder to drop in new versions when
riscv-debug-spec changes.
Change-Id: I4c317e11ab1652333b0bb44168f953ef452d3ef5
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8896
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
The cache handling code is written and optimized for dap queuing.
On hla targets it causes a segmentation fault due to uninitialized
AP pointer still set to NULL.
While it's possible to modify the code to cope with hla targets,
this would lower the OpenOCD performance on modern adapters.
Make cache handling not available on hla targets.
Reported-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Ief4499caedcee477b9517a7ad4597d06b5cb061e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 04da6e2c62 ("target: cortex-m: add support for armv8m caches")
Reviewed-on: https://review.openocd.org/c/openocd/+/9202
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
drop unneeded reset-init event
The speed is set to 1800 kHz at initialization, but increases to 4000 kHz
before flash programming, with debugging continuing at this higher speed.
So, setting 4000 kHz from the start makes sense.
Change-Id: I6bccb5837c624943212b727368b40153e42ccebb
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9027
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Prepare support for STM32H7R/S
Rename methods to follow the STM32l4 driver naming
Change-Id: Iad14ba89a48a63c158dae05a53dcbf92f6fe2f53
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8889
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Replace individual #define constants for STM32H7 flash registers with an
enum to improve code readability and maintainability.
While there, replace a magic number with the macro
MASS_ERASE_TIMEOUT.
while there, remove the unneeded inline attribute
Change-Id: Ib35cbdace5c2f4d12aa91c370d6ec0ce348b397f
Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8888
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
These target configs implement neither device clock setting
nor boost of adapter speed in reset-init event.
Therefore it's not necessary to set back the safe speed in reset-start
Change-Id: I7dcd6f6d1a977388c7a0bc45fe46ede955bd45cb
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9129
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Adds support for direct memory access via SWD emulation for AM64x and
J784s4 boards, configuring addresses and parameters required for
direct memory operations.
Change-Id: Iebc16612b3990b2ef19ddc4143b66ab1bcbfe0f3
Signed-off-by: Joao Lima <joao.lima@hbkworld.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9021
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
I think this may have been a typo/thinko from first implementation, but
for the 4200 the layout is 8 16KB chunks and then 1 128KB chunk. We were
previously only writing 240KB
Signed-off-by: Jonathan Steinert <hachi@kuiki.net>
Change-Id: Ic3cff75ba21f6bc6ac440dfb30e24c328c7cd47c
Reviewed-on: https://review.openocd.org/c/openocd/+/9172
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.au>
Tested-by: jenkins
The cmsis-dap driver is not added to the list of drivers if none of the
USB backends is available.
Add cmsis-dap driver also if TCP backend is available.
Change-Id: I877fac528e7102af74ee54dfcca77c5aded6a7ce
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9162
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Scan-build is unable to correctly follow the deferred loading of
queued read, finalized by the atomic write, thus it incorrectly
claims that the arrays d_u_ccsidr[] and i_ccsidr[] could carry
not initialized values:
armv7m_cache.c:154:31: warning: 1st function call argument
is an uninitialized value [core.CallAndMessage]
cache->arch[cl].d_u_size = decode_ccsidr(d_u_ccsidr[cl]);
armv7m_cache.c:172:29: warning: 1st function call argument
is an uninitialized value [core.CallAndMessage]
cache->arch[cl].i_size = decode_ccsidr(i_ccsidr[cl]);
Initialize the arrays to zero to hide these false positive.
Change-Id: I6d1e88093cb8807848643139647a571c1b566aa8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 04da6e2c62 ("target: cortex-m: add support for armv8m caches")
Reviewed-on: https://review.openocd.org/c/openocd/+/9167
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
