helper/log: Fix build issue on MSYS2 and Cygwin

On MSYS2 (native) and Cygwin, the mallinfo struct uses 'size_t' instead
of 'int', which leads to a compile-time error with the current code.

Update the preprocessor logic so that Cygwin and MSYS2 builds use
the 'size_t' format specifier.

Checkpatch-ignore: COMMIT_LOG_LONG_LINE

Build error on MSYS2:

../src/helper/log.c: In function 'get_free_memory_space':
../src/helper/log.c:78:45: error: format '%d' expects argument of type 'int', but argument 4 has type 'size_t' {aka 'long unsigned int'} [-Werror=format=]
   78 |                 snprintf(s, MEM_STR_LEN, " %d", info.fordblks);
      |                                            ~^   ~~~~~~~~~~~~~
      |                                             |       |
      |                                             int     size_t {aka long unsigned int}
      |                                            %ld

Change-Id: I18d772facba6426ab627fb45a6d50bfc19ec9c05
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9479
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins

.checkpatch.conf

@@ -14,16 +14,13 @@
 --ignore ENOSYS
 --ignore FILE_PATH_CHANGES
 --ignore GERRIT_CHANGE_ID
---ignore LINE_SPACING
 --ignore LOGICAL_CONTINUATIONS
 --ignore MACRO_WITH_FLOW_CONTROL
---ignore NEW_TYPEDEFS
 --ignore PARENTHESIS_ALIGNMENT
 --ignore PREFER_DEFINED_ATTRIBUTE_MACRO
 --ignore PREFER_FALLTHROUGH
 --ignore PREFER_KERNEL_TYPES
 --ignore SPLIT_STRING
 --ignore SSCANF_TO_KSTRTO
---ignore SWITCH_CASE_INDENT_LEVEL
 --ignore TRACING_LOGGING
 --ignore VOLATILE

.editorconfig

@@ -0,0 +1,17 @@
+# EditorConfig: https://editorconfig.org/
+
+# top-most EditorConfig file
+root = true
+
+# All (Defaults)
+[*]
+charset = utf-8
+end_of_line = lf
+insert_final_newline = true
+trim_trailing_whitespace = true
+indent_style = tab
+indent_size = 4
+tab_width = 4
+
+[*.patch,*.diff]
+trim_trailing_whitespace = false

.github/workflows/snapshot.yml

@@ -8,7 +8,7 @@ name: OpenOCD Snapshot
 
 jobs:
   package:
-    runs-on: [ubuntu-18.04]
+    runs-on: [ubuntu-latest]
     env:
       DL_DIR: ../downloads
       BUILD_DIR: ../build
@@ -18,7 +18,7 @@ jobs:
           sudo apt-get update
           sudo apt-get install autotools-dev autoconf automake libtool pkg-config cmake texinfo texlive g++-mingw-w64-i686
       - name: Checkout Code
-        uses: actions/checkout@v1
+        uses: actions/checkout@v4
       - run: ./bootstrap
       - name: Prepare libusb1
         env:
@@ -30,7 +30,7 @@ jobs:
           echo "LIBUSB1_SRC=$PWD/libusb-${LIBUSB1_VER}" >> $GITHUB_ENV
       - name: Prepare hidapi
         env:
-          HIDAPI_VER: 0.11.2
+          HIDAPI_VER: 0.13.1
         run: |
           mkdir -p $DL_DIR && cd $DL_DIR
           wget "https://github.com/libusb/hidapi/archive/hidapi-${HIDAPI_VER}.tar.gz"
@@ -56,6 +56,24 @@ jobs:
           wget "https://github.com/aquynh/capstone/archive/${CAPSTONE_VER}.tar.gz"
           tar -xzf ${CAPSTONE_VER}.tar.gz
           echo "CAPSTONE_SRC=$PWD/capstone-${CAPSTONE_VER}" >> $GITHUB_ENV
+      - name: Prepare libjaylink
+        env:
+          LIBJAYLINK_VER: 0.3.1
+        run: |
+          mkdir -p $DL_DIR && cd $DL_DIR
+          wget https://gitlab.zapb.de/libjaylink/libjaylink/-/archive/${LIBJAYLINK_VER}/libjaylink-${LIBJAYLINK_VER}.tar.gz
+          tar -xzf libjaylink-${LIBJAYLINK_VER}.tar.gz
+          cd libjaylink-${LIBJAYLINK_VER}
+          ./autogen.sh
+          echo "LIBJAYLINK_SRC=$PWD" >> $GITHUB_ENV
+      - name: Prepare jimtcl
+        env:
+          JIMTCL_VER: 0.83
+        run: |
+          mkdir -p $DL_DIR && cd $DL_DIR
+          wget https://github.com/msteveb/jimtcl/archive/refs/tags/${JIMTCL_VER}.tar.gz
+          tar -xzf ${JIMTCL_VER}.tar.gz
+          echo "JIMTCL_SRC=$PWD/jimtcl-${JIMTCL_VER}" >> $GITHUB_ENV
       - name: Package OpenOCD for windows
         env:
           MAKE_JOBS: 2
@@ -64,6 +82,8 @@ jobs:
           HIDAPI_CONFIG: --enable-shared --disable-static --disable-testgui
           LIBFTDI_CONFIG: -DSTATICLIBS=OFF -DEXAMPLES=OFF -DFTDI_EEPROM=OFF
           CAPSTONE_CONFIG: "CAPSTONE_BUILD_CORE_ONLY=yes CAPSTONE_STATIC=yes CAPSTONE_SHARED=no"
+          LIBJAYLINK_CONFIG: --enable-shared --disable-static
+          JIMTCL_CONFIG: --with-ext=json --minimal --disable-ssl
         run: |
           # check if there is tag pointing at HEAD, otherwise take the HEAD SHA-1 as OPENOCD_TAG
           OPENOCD_TAG="`git tag --points-at HEAD`"
@@ -82,7 +102,8 @@ jobs:
           # add missing dlls
           cd $HOST-root/usr
           cp `$HOST-gcc --print-file-name=libwinpthread-1.dll` ./bin/
-          cp `$HOST-gcc --print-file-name=libgcc_s_sjlj-1.dll` ./bin/
+          # required by libftdi1.dll
+          cp `$HOST-gcc --print-file-name=libgcc_s_dw2-1.dll` ./bin/
           # prepare the artifact
           ARTIFACT="openocd-${OPENOCD_TAG}-${HOST}.tar.gz"
           tar -czf $ARTIFACT *
@@ -90,16 +111,15 @@ jobs:
           echo "IS_PRE_RELEASE=$IS_PRE_RELEASE" >> $GITHUB_ENV
           echo "ARTIFACT_PATH=$PWD/$ARTIFACT" >> $GITHUB_ENV
       - name: Publish OpenOCD packaged for windows
-        uses: actions/upload-artifact@v2
+        uses: actions/upload-artifact@v4
         with:
           path: ${{ env.ARTIFACT_PATH }}
       - name: Delete 'latest' Release
-        uses: dev-drprasad/delete-tag-and-release@v0.2.0
+        uses: dev-drprasad/delete-tag-and-release@v1.1
         with:
           delete_release: true
           tag_name: ${{ env.RELEASE_NAME }}
-        env:
-          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+          github_token: ${{ secrets.GITHUB_TOKEN }}
       - name: Create Release
         uses: ncipollo/release-action@v1
         with:

.gitignore

@@ -11,9 +11,9 @@
 *.la
 *.in
 
-# generated source files
-src/jtag/minidriver_imp.h
-src/jtag/jtag_minidriver.h
+# coverage files (gcov)
+*.gcda
+*.gcno
 
 # OpenULINK driver files generated by SDCC
 src/jtag/drivers/OpenULINK/*.rel
@@ -84,6 +84,9 @@ patches
 .cproject
 .settings
 
+# VSCode stuff
+.vscode
+
 # Emacs temp files
 *~
 
@@ -103,3 +106,11 @@ GTAGS
 
 # checkpatch script files
 .checkpatch-camelcase.*
+
+# clangd (e.g. for advanced code completion and linting) generates cache files
+# into .cache
+.cache
+
+# A compile_commands.json can be generated using bear and will help tools such
+# as clangd to locate header files and use correct $CFLAGS
+compile_commands.json

.gitmodules

@@ -1,6 +1,3 @@
-[submodule "tools/git2cl"]
-	path = tools/git2cl
-	url = https://git.savannah.nongnu.org/git/git2cl.git
 [submodule "jimtcl"]
 	path = jimtcl
 	url = https://github.com/msteveb/jimtcl.git

AUTHORS

@@ -1,12 +1,2 @@
-Dominic Rath <Dominic.Rath@gmx.de>
-Magnus Lundin <lundin@mlu.mine.nu>
-Michael Fischer <fischermi@t-online.de>
-Spencer Oliver <spen@spen-soft.co.uk>
-Carsten Schlote <schlote@vahanus.net>
-Øyvind Harboe <oyvind.harboe@zylin.com>
-Duane Ellis <openocd@duaneellis.com>
-Michael Schwingen <michael@schwingen.org>
-Rick Altherr <kc8apf@users.berlios.de>
-David Brownell <dbrownell@users.sourceforge.net>
-Vincint Palatin <vpalatin@users.berlios.de>
-Zachary T Welch <zw@superlucidity.net>
+Please check the source code files and/or Git history for a list of all authors
+and contributors.

HACKING

@@ -77,6 +77,37 @@ patch:
   src/openocd -s ../tcl -f /path/to/openocd.cfg
   @endcode
 
+- Sparse Static Analyzer
+
+  Using this tool allows identifying some bug in C code.
+  In the future, OpenOCD would use the sparse attribute 'bitwise' to
+  detect incorrect endianness assignments.
+
+  Example usage:
+  @code
+  mkdir build-sparse; cd build-sparse
+  ../configure CC=cgcc CFLAGS="-Wsparse-all -Wno-declaration-after-statement \
+	   -Wno-unknown-attribute -Wno-transparent-union -Wno-tautological-compare \
+       -Wno-vla -Wno-flexible-array-array -D__FLT_EVAL_METHOD__=0"
+  make
+  @endcode
+
+- Code coverage analysis
+
+  By inspecting the code coverage, you can identify potential gaps in your testing
+  and use that information to improve your test scenarios.
+
+  Example usage:
+  @code
+  mkdir build-gcov; cd build-gcov
+  ../configure --enable-gcov [...]
+  make
+  # ... Now execute your test scenarios to collect OpenOCD code coverage ...
+  lcov --capture --directory ./src --output-file openocd-coverage.info
+  genhtml openocd-coverage.info --output-directory coverage_report
+  # ... Open coverage_report/index.html in a web browser ...
+  @endcode
+
 Please consider performing these additional checks where appropriate
 (especially Clang Static Analyzer for big portions of new code) and
 mention the results (e.g. "Valgrind-clean, no new Clang analyzer
@@ -138,11 +169,9 @@ git remote add review https://USERNAME:PASSWORD@review.openocd.org/p/openocd.git
 Gerrit server, even if you plan to use several local branches for different
 topics. It is possible because @c for/master is not a traditional Git
 branch.
-  -# You will need to install this hook, we will look into a better solution:
-@code
-scp -p -P 29418 USERNAME@review.openocd.org:hooks/commit-msg .git/hooks/
-@endcode
-  Or with http only:
+  -# You will need to install this hook to automatically add the
+     field "Change-Id:" in the commit message, as required by Gerrit.
+     We will look into a better solution:
 @code
 wget https://review.openocd.org/tools/hooks/commit-msg
 mv commit-msg .git/hooks
@@ -219,6 +248,12 @@ doc: fix typos
 @code
 git pull --rebase origin master
 @endcode
+
+-# When you create a new version of an old patch, check that the new patch
+   keeps the same 'Change-Id:' field of the old patch.
+   This allows the Gerrit server to recognize the patch as a new version of
+   the older one and keeps track of the history and the review process.
+
 -# Send the patches to the Gerrit server for review:
 @code
 git push review
@@ -276,6 +311,13 @@ Only for <em>exceptional cases</em>, it is allowed to submit patches
 to Gerrit with the special field 'Checkpatch-ignore:' in the commit
 message. This field will cause checkpatch to ignore the error types
 listed in the field, only for the patch itself.
+For errors in the commit message, the special field has to be put in
+the commit message before the line that produces the error.
+The special field must be added <em>before</em> the 'Signed-off-by:'
+line, otherwise it is ignored.
+To ignore multiple errors, either add multiple lines with the special
+field or add multiple error types, separated by space or commas, in a
+single line.
 The error type is printed by checkpatch on failure.
 For example the names of Windows APIs mix lower and upper case chars,
 in violation of OpenOCD coding style, triggering a 'CAMELCASE' error:

LICENSES/dual/CC-BY-4.0

@@ -0,0 +1,409 @@
+Valid-License-Identifier: CC-BY-4.0
+SPDX-URL: https://spdx.org/licenses/CC-BY-4.0
+Usage-Guide:
+  Do NOT use on OpenOCD code. This license is not GPL2 compatible. It may only
+  be used for dual-licensed files where the other license is GPL2 compatible.
+  If you end up using this it MUST be used together with a GPL2 compatible
+  license using "OR".
+  To use the Creative Commons Attribution 4.0 International license put
+  the following SPDX tag/value pair into a comment according to the
+  placement guidelines in the licensing rules documentation:
+    SPDX-License-Identifier: CC-BY-4.0
+License-Text:
+
+Creative Commons Attribution 4.0 International
+
+=======================================================================
+
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+
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+
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LICENSES/license-rules.txt

@@ -173,7 +173,6 @@ OpenOCD, can be broken down into:
 
    File format examples::
 
-      Valid-License-Identifier: GPL-2.0
       Valid-License-Identifier: GPL-2.0-only
       Valid-License-Identifier: GPL-2.0-or-later
       SPDX-URL: https://spdx.org/licenses/GPL-2.0.html
@@ -182,15 +181,27 @@ OpenOCD, can be broken down into:
         tag/value pairs into a comment according to the placement
         guidelines in the licensing rules documentation.
         For 'GNU General Public License (GPL) version 2 only' use:
-          SPDX-License-Identifier: GPL-2.0
-        or
           SPDX-License-Identifier: GPL-2.0-only
         For 'GNU General Public License (GPL) version 2 or any later version' use:
           SPDX-License-Identifier: GPL-2.0-or-later
       License-Text:
         Full license text
 
-2. Exceptions:
+2. Dual Licensing Only:
+
+   These licenses should only be used to dual license code with another
+   license in addition to a preferred license.  These licenses are available
+   from the directory::
+
+      LICENSES/dual/
+
+   in the OpenOCD source tree.
+
+   The files in this directory contain the full license text and
+   `Metatags`_.  The file names are identical to the SPDX license
+   identifier which shall be used for the license in source files.
+
+3. Exceptions:
 
    Some licenses can be amended with exceptions which grant certain rights
    which the original license does not.  These exceptions are available
@@ -247,7 +258,7 @@ OpenOCD, can be broken down into:
       License-Text:
         Full license text
 
-3. Stand-alone licenses:
+4. Stand-alone licenses:
 
    These licenses should only be used for stand-alone applications that are
    distributed with OpenOCD but are not included in the OpenOCD binary.

LICENSES/preferred/CC0-1.0

@@ -0,0 +1,130 @@
+Valid-License-Identifier: CC0-1.0
+SPDX-URL: https://spdx.org/licenses/CC0-1.0.html
+Usage-Guide:
+  To use the Creative Commons Zero v1.0 Universal License put the following
+  SPDX tag/value pair into a comment according to the placement guidelines in
+  the licensing rules documentation:
+    SPDX-License-Identifier: CC0-1.0
+License-Text:
+
+Creative Commons Legal Code
+
+CC0 1.0 Universal
+
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+
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LICENSES/preferred/GFDL-1.2

@@ -18,7 +18,7 @@ License-Text:
 
 
  Copyright (C) 2000,2001,2002  Free Software Foundation, Inc.
-     51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+     <https://fsf.org/>
  Everyone is permitted to copy and distribute verbatim copies
  of this license document, but changing it is not allowed.
 

LICENSES/preferred/GPL-2.0

@@ -1,4 +1,3 @@
-Valid-License-Identifier: GPL-2.0
 Valid-License-Identifier: GPL-2.0-only
 Valid-License-Identifier: GPL-2.0-or-later
 SPDX-URL: https://spdx.org/licenses/GPL-2.0.html
@@ -7,8 +6,6 @@ Usage-Guide:
   tag/value pairs into a comment according to the placement
   guidelines in the licensing rules documentation.
   For 'GNU General Public License (GPL) version 2 only' use:
-    SPDX-License-Identifier: GPL-2.0
-  or
     SPDX-License-Identifier: GPL-2.0-only
   For 'GNU General Public License (GPL) version 2 or any later version' use:
     SPDX-License-Identifier: GPL-2.0-or-later
@@ -18,7 +15,7 @@ License-Text:
                        Version 2, June 1991
 
  Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ <https://fsf.org/>
  Everyone is permitted to copy and distribute verbatim copies
  of this license document, but changing it is not allowed.
 
@@ -320,8 +317,7 @@ the "copyright" line and a pointer to where the full notice is found.
     GNU General Public License for more details.
 
     You should have received a copy of the GNU General Public License along
-    with this program; if not, write to the Free Software Foundation, Inc.,
-    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+    with this program; if not, see <https://www.gnu.org/licenses/>.
 
 Also add information on how to contact you by electronic and paper mail.
 

LICENSES/preferred/LGPL-2.1

@@ -0,0 +1,503 @@
+Valid-License-Identifier: LGPL-2.1-only
+Valid-License-Identifier: LGPL-2.1-or-later
+SPDX-URL: https://spdx.org/licenses/LGPL-2.1.html
+Usage-Guide:
+  To use this license in source code, put one of the following SPDX
+  tag/value pairs into a comment according to the placement
+  guidelines in the licensing rules documentation.
+  For 'GNU Lesser General Public License (LGPL) version 2.1 only' use:
+    SPDX-License-Identifier: LGPL-2.1-only
+  For 'GNU Lesser General Public License (LGPL) version 2.1 or any later
+  version' use:
+    SPDX-License-Identifier: LGPL-2.1-or-later
+License-Text:
+
+GNU LESSER GENERAL PUBLIC LICENSE
+Version 2.1, February 1999
+
+Copyright (C) 1991, 1999 Free Software Foundation, Inc.
+<https://fsf.org/>
+
+Everyone is permitted to copy and distribute verbatim copies of this
+license document, but changing it is not allowed.
+
+[This is the first released version of the Lesser GPL. It also counts as
+the successor of the GNU Library Public License, version 2, hence the
+version number 2.1.]
+
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+
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+    infringement or for any other reason (not limited to patent issues),
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+
+    This section is intended to make thoroughly clear what is believed to
+    be a consequence of the rest of this License.
+
+12. If the distribution and/or use of the Library is restricted in certain
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+    explicit geographical distribution limitation excluding those
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+    not thus excluded. In such case, this License incorporates the
+    limitation as if written in the body of this License.
+
+13. The Free Software Foundation may publish revised and/or new versions of
+    the Lesser General Public License from time to time. Such new versions
+    will be similar in spirit to the present version, but may differ in
+    detail to address new problems or concerns.
+
+    Each version is given a distinguishing version number. If the Library
+    specifies a version number of this License which applies to it and "any
+    later version", you have the option of following the terms and
+    conditions either of that version or of any later version published by
+    the Free Software Foundation. If the Library does not specify a license
+    version number, you may choose any version ever published by the Free
+    Software Foundation.
+
+14. If you wish to incorporate parts of the Library into other free
+    programs whose distribution conditions are incompatible with these,
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+    Foundation; we sometimes make exceptions for this. Our decision will be
+    guided by the two goals of preserving the free status of all
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+
+NO WARRANTY
+
+15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+    FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
+    OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+    PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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+    NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+    WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+    REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU FOR
+    DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL
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+    OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+END OF TERMS AND CONDITIONS
+
+How to Apply These Terms to Your New Libraries
+
+If you develop a new library, and you want it to be of the greatest
+possible use to the public, we recommend making it free software that
+everyone can redistribute and change. You can do so by permitting
+redistribution under these terms (or, alternatively, under the terms of the
+ordinary General Public License).
+
+To apply these terms, attach the following notices to the library. It is
+safest to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least the
+"copyright" line and a pointer to where the full notice is found.
+
+one line to give the library's name and an idea of what it does.
+Copyright (C) year name of author
+
+This library is free software; you can redistribute it and/or modify it
+under the terms of the GNU Lesser General Public License as published by
+the Free Software Foundation; either version 2.1 of the License, or (at
+your option) any later version.
+
+This library is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
+for more details.
+
+You should have received a copy of the GNU Lesser General Public License
+along with this library; if not, see <https://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the library, if
+necessary. Here is a sample; alter the names:
+
+Yoyodyne, Inc., hereby disclaims all copyright interest in
+the library `Frob' (a library for tweaking knobs) written
+by James Random Hacker.
+
+signature of Ty Coon, 1 April 1990
+Ty Coon, President of Vice
+That's all there is to it!

LICENSES/stand-alone/Apache-2.0

@@ -0,0 +1,189 @@
+Valid-License-Identifier: Apache-2.0
+SPDX-URL: https://spdx.org/licenses/Apache-2.0.html
+Usage-Guide:
+  Do NOT use on OpenOCD code. The Apache-2.0 is not GPL2 compatible. It may only
+  be used for dual-licensed files where the other license is GPL2 compatible.
+  If you end up using this it MUST be used together with a GPL2 compatible
+  license using "OR".
+  It may also be used for stand-alone code NOT linked within the OpenOCD binary
+  but distributed with OpenOCD.
+  To use the Apache License version 2.0 put the following SPDX tag/value
+  pair into a comment according to the placement guidelines in the
+  licensing rules documentation:
+    SPDX-License-Identifier: Apache-2.0
+License-Text:
+
+Apache License
+
+Version 2.0, January 2004
+
+http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
+"License" shall mean the terms and conditions for use, reproduction, and
+distribution as defined by Sections 1 through 9 of this document.
+
+"Licensor" shall mean the copyright owner or entity authorized by the
+copyright owner that is granting the License.
+
+"Legal Entity" shall mean the union of the acting entity and all other
+entities that control, are controlled by, or are under common control with
+that entity. For the purposes of this definition, "control" means (i) the
+power, direct or indirect, to cause the direction or management of such
+entity, whether by contract or otherwise, or (ii) ownership of fifty
+percent (50%) or more of the outstanding shares, or (iii) beneficial
+ownership of such entity.
+
+"You" (or "Your") shall mean an individual or Legal Entity exercising
+permissions granted by this License.
+
+"Source" form shall mean the preferred form for making modifications,
+including but not limited to software source code, documentation source,
+and configuration files.
+
+"Object" form shall mean any form resulting from mechanical transformation
+or translation of a Source form, including but not limited to compiled
+object code, generated documentation, and conversions to other media types.
+
+"Work" shall mean the work of authorship, whether in Source or Object form,
+made available under the License, as indicated by a copyright notice that
+is included in or attached to the work (an example is provided in the
+Appendix below).
+
+"Derivative Works" shall mean any work, whether in Source or Object form,
+that is based on (or derived from) the Work and for which the editorial
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+a whole, an original work of authorship. For the purposes of this License,
+Derivative Works shall not include works that remain separable from, or
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+Works thereof.
+
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+
+5. Submission of Contributions. Unless You explicitly state otherwise, any
+   Contribution intentionally submitted for inclusion in the Work by You to
+   the Licensor shall be under the terms and conditions of this License,
+   without any additional terms or conditions. Notwithstanding the above,
+   nothing herein shall supersede or modify the terms of any separate
+   license agreement you may have executed with Licensor regarding such
+   Contributions.
+
+6. Trademarks. This License does not grant permission to use the trade
+   names, trademarks, service marks, or product names of the Licensor,
+   except as required for reasonable and customary use in describing the
+   origin of the Work and reproducing the content of the NOTICE file.
+
+7. Disclaimer of Warranty. Unless required by applicable law or agreed to
+   in writing, Licensor provides the Work (and each Contributor provides
+   its Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
+   OF ANY KIND, either express or implied, including, without limitation,
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+   MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely
+   responsible for determining the appropriateness of using or
+   redistributing the Work and assume any risks associated with Your
+   exercise of permissions under this License.
+
+8. Limitation of Liability. In no event and under no legal theory, whether
+   in tort (including negligence), contract, or otherwise, unless required
+   by applicable law (such as deliberate and grossly negligent acts) or
+   agreed to in writing, shall any Contributor be liable to You for
+   damages, including any direct, indirect, special, incidental, or
+   consequential damages of any character arising as a result of this
+   License or out of the use or inability to use the Work (including but
+   not limited to damages for loss of goodwill, work stoppage, computer
+   failure or malfunction, or any and all other commercial damages or
+   losses), even if such Contributor has been advised of the possibility of
+   such damages.
+
+9. Accepting Warranty or Additional Liability. While redistributing the
+   Work or Derivative Works thereof, You may choose to offer, and charge a
+   fee for, acceptance of support, warranty, indemnity, or other liability
+   obligations and/or rights consistent with this License. However, in
+   accepting such obligations, You may act only on Your own behalf and on
+   Your sole responsibility, not on behalf of any other Contributor, and
+   only if You agree to indemnify, defend, and hold each Contributor
+   harmless for any liability incurred by, or claims asserted against, such
+   Contributor by reason of your accepting any such warranty or additional
+   liability.
+
+END OF TERMS AND CONDITIONS

Makefile.am

@@ -1,16 +1,14 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
-# not a GNU package. You can remove this line, if
-# have all needed files, that a GNU package needs
-AUTOMAKE_OPTIONS = gnu 1.6
+AUTOMAKE_OPTIONS = foreign 1.14
 
 .DELETE_ON_ERROR:
 
 # make sure we pass the correct jimtcl flags to distcheck
-DISTCHECK_CONFIGURE_FLAGS = --disable-install-jim
+AM_DISTCHECK_CONFIGURE_FLAGS = --disable-install-jim
 
 # do not run Jim Tcl tests (esp. during distcheck)
-check-recursive: SUBDIRS :=
+check-recursive: SUBDIRS := $(SUBDIRS:jimtcl=)
 
 nobase_dist_pkgdata_DATA = \
 	contrib/libdcc/dcc_stdio.c \
@@ -26,14 +24,22 @@ noinst_LTLIBRARIES =
 info_TEXINFOS =
 dist_man_MANS =
 EXTRA_DIST =
+DISTCLEANFILES =
 
 if INTERNAL_JIMTCL
 SUBDIRS += jimtcl
 DIST_SUBDIRS += jimtcl
+EXTRA_DIST += jimtcl/configure.gnu
+# jimtcl from 0.79 to 0.82 miss cleaning jsmn.o
+DISTCLEANFILES += jimtcl/jsmn/jsmn.o
 endif
 
+SUBDIRS += testing
+DIST_SUBDIRS += testing
+
 # common flags used in openocd build
 AM_CFLAGS = $(GCC_WARNINGS)
+AM_LDFLAGS =
 
 AM_CPPFLAGS = $(HOST_CPPFLAGS)\
 			  -I$(top_srcdir)/src \
@@ -44,26 +50,38 @@ AM_CPPFLAGS = $(HOST_CPPFLAGS)\
 if INTERNAL_JIMTCL
 AM_CPPFLAGS += -I$(top_srcdir)/jimtcl \
 			   -I$(top_builddir)/jimtcl
+else
+AM_CPPFLAGS += $(JIMTCL_CFLAGS)
 endif
+
+if USE_GCOV
+AM_CFLAGS += --coverage
+AM_LDFLAGS += --coverage
+endif
+
 EXTRA_DIST += \
 	BUGS \
 	HACKING \
 	NEWTAPS \
-	README.Windows \
-	README.macOS \
+	README.Windows.md \
+	README.macOS.md \
 	$(EXTRA_DIST_NEWS) \
 	Doxyfile.in \
 	LICENSES/license-rules.txt \
+	LICENSES/dual/CC-BY-4.0 \
 	LICENSES/exceptions/eCos-exception-2.0 \
 	LICENSES/preferred/BSD-1-Clause \
 	LICENSES/preferred/BSD-2-Clause \
 	LICENSES/preferred/BSD-2-Clause-Views \
 	LICENSES/preferred/BSD-3-Clause \
 	LICENSES/preferred/BSD-Source-Code \
+	LICENSES/preferred/CC0-1.0 \
 	LICENSES/preferred/GFDL-1.2 \
 	LICENSES/preferred/gfdl-1.2.texi.readme \
 	LICENSES/preferred/GPL-2.0 \
+	LICENSES/preferred/LGPL-2.1 \
 	LICENSES/preferred/MIT \
+	LICENSES/stand-alone/Apache-2.0 \
 	LICENSES/stand-alone/GPL-3.0 \
 	tools/logger.pl \
 	tools/rlink_make_speed_table \
@@ -107,9 +125,13 @@ TCL_PATH = tcl
 TCL_FILES = find $(srcdir)/$(TCL_PATH) -name '*.cfg' -o -name '*.tcl' -o -name '*.txt' | \
 		sed -e 's,^$(srcdir)/$(TCL_PATH),,'
 
+# The git log command below generates many empty text lines with only some space characters
+# for indentation purposes, so use sed to trim all trailing whitespace.
 dist-hook:
 	if test -d $(srcdir)/.git -a \( ! -e $(distdir)/ChangeLog -o -w $(distdir)/ChangeLog \) ; then \
-		git --git-dir $(srcdir)/.git log | $(srcdir)/tools/git2cl/git2cl > $(distdir)/ChangeLog ; \
+		git --git-dir $(srcdir)/.git log --date=short --pretty="format:%ad  %aN <%aE>%n%n%w(0,4,6)* %B" \
+		| sed 's/[[:space:]]*$$//' > $(distdir)/ChangeLog.tmp && \
+		mv $(distdir)/ChangeLog.tmp $(distdir)/ChangeLog; \
 	fi
 	for i in $$($(TCL_FILES)); do \
 		j="$(distdir)/$(TCL_PATH)/$$i" && \
@@ -129,9 +151,9 @@ uninstall-hook:
 
 distclean-local:
 	rm -rf Doxyfile doxygen
-	rm -f $(srcdir)/jimtcl/configure.gnu
+	-rm -f $(srcdir)/jimtcl/configure.gnu
 
-DISTCLEANFILES = doxygen.log
+DISTCLEANFILES += doxygen.log
 
 METASOURCES = AUTO
 

NEWS

@@ -2,126 +2,29 @@ This file includes highlights of the changes made in the OpenOCD
 source archive release.
 
 JTAG Layer:
-	* add default to adapter speed when unspecified (100 kHz)
-	* AM335X gpio (BeagleBones) adapter driver
-	* BCM2835 support for SWD
-	* Cadence Virtual Debug (vdebug) adapter driver
-	* CMSIS-DAP support for SWO and SWD multidrop
-	* Espressif USB JTAG Programmer adapter driver
-	* Remote bitbang support for Windows host
-	* ST-LINK add TCP server support to adapter driver
-	* SWD multidrop support
 
 Boundary Scan:
 
 Target Layer:
-	* aarch64: support watchpoints
-	* arm: support independent TPIU and SWO for trace
-	* arm adi v5: support Large Physical Address Extension
-	* arm adi v6: support added, for jtag and swd transport
-	* cortex_a: support watchpoints
-	* elf 64bit load support
-	* Espressif: support ESP32, ESP32-S2 and ESP32-S3 cores
-	* semihosting: support user defined operations
-	* Xtensa: support Xtensa LX architecture via JTAG and ADIv5 DAP
 
 Flash Layer:
-	* Atmel/Microchip SAM E51G18A, E51G19A, R35J18B, LAN9255 support
-	* GigaDevice GD32E23x, GD32F1x0/3x0, GD32VF103 support
-	* Nuvoton NPCX series support
-	* onsemi RSL10 support
-	* Raspberry Pi Pico RP2040 support
-	* ST BlueNRG-LPS support
-	* ST STM32 G05x, G06x, G0Bx, G0Cx, U57x, U58x, WB1x, WL5x support
-	* ST STM32 G0, G4, L4, L4+, L5, WB, WL OTP support
 
 Board, Target, and Interface Configuration Scripts:
-	* Ampere Computing eMAG8180, Altra ("Quicksilver") and Altra Max ("Mystique") board config
-	* Cadence KC705 FPGA (Xtensa Development Platform) via JTAG and ADIv5 DAP board config
-	* Digilent Nexys Video board config
-	* Espressif ESP32 ETHERNET-KIT and WROVER-KIT board config
-	* Espressif ESP32 via ESP USB Bridge generic board config
-	* Espressif ESP32-S2 Kaluga 1 board config
-	* Espressif ESP32-S2 with ESP USB Bridge board config
-	* Espressif ESP32-S3 example board config
-	* Kontron SMARC-sAL28 board config
-	* LambdaConcept ECPIX-5 board config
-	* Microchip ATSAMA5D27-SOM1-EK1 board config
-	* Microchip EVB-LAN9255 board config
-	* Microchip SAME51 Curiosity Nano board config
-	* NXP FRDM-K64F, LS1046ARDB and LS1088ARDB board config
-	* NXP RT6XX board config
-	* Olimex H405 board config
-	* Radiona ULX3S board config
-	* Raspberry Pi 3 and Raspberry Pi 4 model B board config
-	* Raspberry Pi Pico-Debug board config
-	* Renesas R-Car V3U Falcon board config
-	* ST BlueNRG-LPS steval-idb012v1 board config
-	* ST NUCLEO-8S208RB board config
-	* ST NUCLEO-G031K8, NUCLEO-G070RB, NUCLEO-G071RB board config
-	* ST NUCLEO-G431KB, NUCLEO-G431RB, NUCLEO-G474RE board config
-	* ST STM32MP13x-DK board config
-	* TI AM625 EVM, AM642 EVM and AM654 EVM board config
-	* TI J721E EVM, J721S2 EVM and J7200 EVM board config
-	* Ampere Computing eMAG, Altra ("Quicksilver") and Altra Max ("Mystique") target config
-	* Cadence Xtensa generic and Xtensa VDebug target config
-	* Broadcom BCM2711, BCM2835, BCM2836 and BCM2837 target config
-	* Espressif ESP32, ESP32-S2 and ESP32-S3 target config
-	* Microchip ATSAMA5D2 series target config
-	* NanoXplore NG-Ultra SoC target config
-	* NXP IMX8QM target config
-	* NXP LS1028A, LS1046A and LS1088A target config
-	* NXP RT600 (Xtensa HiFi DSP) target config
-	* onsemi RSL10 target config
-	* Raspberry Pi Pico RP2040 target config
-	* Renesas R8A779A0 V3U target config
-	* Renesas RZ/Five target config
-	* Renesas RZ/G2 MPU family target config
-	* Rockchip RK3399 target config
-	* ST BlueNRG-LPS target config
-	* ST STM32MP13x target config
-	* TI AM625, AM654, J721E and J721S2 target config
-	* Ashling Opella-LD interface config
-	* Aspeed AST2600 linuxgpiod based interface config
-	* Blinkinlabs JTAG_Hat interface config
-	* Cadence Virtual Debug (vdebug) interface config
-	* Espressif ESP32-S2 Kaluga 1 board's interface config
-	* Espressif USB Bridge jtag interface config
-	* Infineon DAP miniWiggler V3 interface config
-	* PLS SPC5 interface config
-	* Tigard interface config
-	* Lattice MachXO3 family FPGA config
 
 Server Layer:
-	* GDB: add per-target remote protocol extensions
-	* GDB: more 'Z' packets support
-	* IPDBG JtagHost server functionality
-	* semihosting: I/O redirection to TCP server
-	* telnet: support for command's autocomplete
 
 RTOS:
-	* 'none' rtos support
-	* Zephyr rtos support
 
 Documentation:
 
 Build and Release:
-	* Add json extension to jimtcl build
-	* Drop dependency from libusb0
-	* Drop repository repo.or.cz for submodules
-	* Move gerrit to https://review.openocd.org/
-	* Require autoconf 2.69 or newer
-	* Update jep106 to revision JEP106BE
-	* Update jimtcl to version 0.81
-	* Update libjaylink to version 0.3.1
-	* New configure flag '--enable-jimtcl-maintainer' for jimtcl build
 
 
 This release also contains a number of other important functional and
 cosmetic bugfixes. For more details about what has changed since the
 last release, see the git repository history:
 
-http://sourceforge.net/p/openocd/code/ci/v0.12.0-rc1/log/?path=
+http://sourceforge.net/p/openocd/code/ci/v0.x.0/log/?path=
 
 
 For older NEWS, see the NEWS files associated with each release

NEWS-0.12.0

@@ -0,0 +1,132 @@
+This file includes highlights of the changes made in the OpenOCD
+source archive release.
+
+JTAG Layer:
+	* add default to adapter speed when unspecified (100 kHz)
+	* AM335X gpio (BeagleBones) adapter driver
+	* BCM2835 support for SWD
+	* Cadence Virtual Debug (vdebug) adapter driver
+	* CMSIS-DAP support for SWO and SWD multidrop
+	* Espressif USB JTAG Programmer adapter driver
+	* Remote bitbang support for Windows host
+	* ST-LINK add TCP server support to adapter driver
+	* SWD multidrop support
+
+Boundary Scan:
+
+Target Layer:
+	* aarch64: support watchpoints
+	* arm: support independent TPIU and SWO for trace
+	* arm adi v5: support Large Physical Address Extension
+	* arm adi v6: support added, for jtag and swd transport
+	* cortex_a: support watchpoints
+	* elf 64bit load support
+	* Espressif: support ESP32, ESP32-S2 and ESP32-S3 cores
+	* semihosting: support user defined operations
+	* Xtensa: support Xtensa LX architecture via JTAG and ADIv5 DAP
+
+Flash Layer:
+	* Atmel/Microchip SAM E51G18A, E51G19A, R35J18B, LAN9255 support
+	* GigaDevice GD32E23x, GD32F1x0/3x0, GD32VF103 support
+	* Nuvoton NPCX series support
+	* onsemi RSL10 support
+	* Raspberry Pi Pico RP2040 support
+	* ST BlueNRG-LPS support
+	* ST STM32 G05x, G06x, G0Bx, G0Cx, U57x, U58x, WB1x, WL5x support
+	* ST STM32 G0, G4, L4, L4+, L5, WB, WL OTP support
+
+Board, Target, and Interface Configuration Scripts:
+	* Ampere Computing eMAG8180, Altra ("Quicksilver") and Altra Max ("Mystique") board config
+	* Cadence KC705 FPGA (Xtensa Development Platform) via JTAG and ADIv5 DAP board config
+	* Digilent Nexys Video board config
+	* Espressif ESP32 ETHERNET-KIT and WROVER-KIT board config
+	* Espressif ESP32 via ESP USB Bridge generic board config
+	* Espressif ESP32-S2 Kaluga 1 board config
+	* Espressif ESP32-S2 with ESP USB Bridge board config
+	* Espressif ESP32-S3 example board config
+	* Kontron SMARC-sAL28 board config
+	* LambdaConcept ECPIX-5 board config
+	* Microchip ATSAMA5D27-SOM1-EK1 board config
+	* Microchip EVB-LAN9255 board config
+	* Microchip SAME51 Curiosity Nano board config
+	* NXP FRDM-K64F, LS1046ARDB and LS1088ARDB board config
+	* NXP RT6XX board config
+	* Olimex H405 board config
+	* Radiona ULX3S board config
+	* Raspberry Pi 3 and Raspberry Pi 4 model B board config
+	* Raspberry Pi Pico-Debug board config
+	* Renesas R-Car V3U Falcon board config
+	* ST BlueNRG-LPS steval-idb012v1 board config
+	* ST NUCLEO-8S208RB board config
+	* ST NUCLEO-G031K8, NUCLEO-G070RB, NUCLEO-G071RB board config
+	* ST NUCLEO-G431KB, NUCLEO-G431RB, NUCLEO-G474RE board config
+	* ST STM32MP13x-DK board config
+	* TI AM625 EVM, AM642 EVM and AM654 EVM board config
+	* TI J721E EVM, J721S2 EVM and J7200 EVM board config
+	* Ampere Computing eMAG, Altra ("Quicksilver") and Altra Max ("Mystique") target config
+	* Cadence Xtensa generic and Xtensa VDebug target config
+	* Broadcom BCM2711, BCM2835, BCM2836 and BCM2837 target config
+	* Espressif ESP32, ESP32-S2 and ESP32-S3 target config
+	* Microchip ATSAMA5D2 series target config
+	* NanoXplore NG-Ultra SoC target config
+	* NXP IMX8QM target config
+	* NXP LS1028A, LS1046A and LS1088A target config
+	* NXP RT600 (Xtensa HiFi DSP) target config
+	* onsemi RSL10 target config
+	* Raspberry Pi Pico RP2040 target config
+	* Renesas R8A779A0 V3U target config
+	* Renesas RZ/Five target config
+	* Renesas RZ/G2 MPU family target config
+	* Rockchip RK3399 target config
+	* ST BlueNRG-LPS target config
+	* ST STM32MP13x target config
+	* TI AM625, AM654, J721E and J721S2 target config
+	* Ashling Opella-LD interface config
+	* Aspeed AST2600 linuxgpiod based interface config
+	* Blinkinlabs JTAG_Hat interface config
+	* Cadence Virtual Debug (vdebug) interface config
+	* Espressif ESP32-S2 Kaluga 1 board's interface config
+	* Espressif USB Bridge jtag interface config
+	* Infineon DAP miniWiggler V3 interface config
+	* PLS SPC5 interface config
+	* Tigard interface config
+	* Lattice MachXO3 family FPGA config
+
+Server Layer:
+	* GDB: add per-target remote protocol extensions
+	* GDB: more 'Z' packets support
+	* IPDBG JtagHost server functionality
+	* semihosting: I/O redirection to TCP server
+	* telnet: support for command's autocomplete
+
+RTOS:
+	* 'none' rtos support
+	* Zephyr rtos support
+
+Documentation:
+
+Build and Release:
+	* Add json extension to jimtcl build
+	* Drop dependency from libusb0
+	* Drop repository repo.or.cz for submodules
+	* Move gerrit to https://review.openocd.org/
+	* Require autoconf 2.69 or newer
+	* Update jep106 to revision JEP106BF.01
+	* Update jimtcl to version 0.81
+	* Update libjaylink to version 0.3.1
+	* New configure flag '--enable-jimtcl-maintainer' for jimtcl build
+
+
+This release also contains a number of other important functional and
+cosmetic bugfixes. For more details about what has changed since the
+last release, see the git repository history:
+
+http://sourceforge.net/p/openocd/code/ci/v0.12.0/log/?path=
+
+
+For older NEWS, see the NEWS files associated with each release
+(i.e. NEWS-<version>).
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES.txt files in the source archive).

README.Windows.md

@@ -1,29 +1,19 @@
-Building OpenOCD for Windows
-----------------------------
+# OpenOCD for Windows
+
+This README contains instructions that are specific to Windows.
+
+## Building
 
 You can build OpenOCD for Windows natively with either MinGW-w64/MSYS
-or Cygwin (plain MinGW might work with --disable-werror but is not
+or Cygwin (plain MinGW might work with `--disable-werror` but is not
 recommended as it doesn't provide enough C99 compatibility).
 Alternatively, one can cross-compile it using MinGW-w64 on a *nix
-host. See README for the generic instructions.
+host. See [README](README.md) for the generic instructions.
 
 Also, the MSYS2 project provides both ready-made binaries and an easy
 way to self-compile from their software repository out of the box.
 
-Native MinGW-w64/MSYS compilation
------------------------------
-
-As MSYS doesn't come with pkg-config pre-installed, you need to add it
-manually. The easiest way to do that is to download pkg-config-lite
-from:
-
-  http://sourceforge.net/projects/pkgconfiglite/
-
-Then simply unzip the archive to the root directory of your MinGW-w64
-installation.
-
-USB adapters
-------------
+## USB adapters
 
 For the adapters that use a HID-based protocol, e.g. CMSIS-DAP, you do
 not need to perform any additional configuration.
@@ -31,9 +21,7 @@ not need to perform any additional configuration.
 For all the others you usually need to have WinUSB.sys (or
 libusbK.sys) driver installed. Some vendor software (e.g. for
 ST-LINKv2) does it on its own. For the other cases the easiest way to
-assign WinUSB to a device is to use the latest Zadig installer:
-
-  http://zadig.akeo.ie
+assign WinUSB to a device is to use the latest Zadig installer: <https://zadig.akeo.ie>
 
 When using a composite USB device, it's often necessary to assign
 WinUSB.sys to the composite parent instead of the specific
@@ -42,7 +30,7 @@ Zadig installer.
 
 If you need to use the same adapter with other applications that may
 require another driver, a solution for Windows Vista and above is to
-activate the IgnoreHWSerNum registry setting for the USB device.
+activate the `IgnoreHWSerNum` registry setting for the USB device.
 
 That setting forces Windows to associate the driver per port instead of
 per serial number, the same behaviour as when the device does not contain
@@ -52,5 +40,5 @@ port depending on which application to use.
 
 For more information, see:
 
-  http://msdn.microsoft.com/en-us/library/windows/hardware/jj649944(v=vs.85).aspx
-  http://www.ftdichip.com/Support/Knowledgebase/index.html?ignorehardwareserialnumber.htm
+- <https://learn.microsoft.com/en-us/windows-hardware/drivers/usbcon/usb-device-specific-registry-settings>
+- <https://www.ftdichip.com/Support/Knowledgebase/index.html?ignorehardwareserialnumber.htm>

README.macOS

@@ -1,54 +0,0 @@
-Building OpenOCD for macOS
---------------------------
-
-There are a few prerequisites you will need first:
-
-- Xcode (install from the AppStore)
-- Command Line Tools (install from Xcode -> Preferences -> Downloads)
-- Gentoo Prefix (http://www.gentoo.org/proj/en/gentoo-alt/prefix/bootstrap.xml)
-  or
-- Homebrew (http://mxcl.github.io/homebrew/)
-  or
-- MacPorts (http://www.macports.org/install.php)
-
-
-If you're building manually you need Texinfo version 5.0 or later. The
-simplest way to get it is to use Homebrew (brew install texinfo) and
-then ``export PATH=/usr/local/opt/texinfo/bin:$PATH``.
-
-
-With Gentoo Prefix you can build the release version or the latest
-devel version (-9999) the usual way described in the Gentoo
-documentation. Alternatively, install the prerequisites and build
-manually from the sources.
-
-
-With Homebrew you can either run:
-  brew install [--HEAD] openocd (where optional --HEAD asks brew to
-                                 install the current git version)
-    or
-  brew install libtool automake libusb [hidapi] [libftdi]
-    (to install the needed dependencies and then proceed with the
-     manual building procedure)
-
-
-For building with MacPorts you need to run:
-  sudo port install libtool automake autoconf pkgconfig \
-    libusb [libftdi1]
-
-You should also specify LDFLAGS and CPPFLAGS to allow configure to use
-MacPorts' libraries, so run configure like this:
-  LDFLAGS=-L/opt/local/lib CPPFLAGS=-I/opt/local/include ./configure [options]
-
-
-See README for the generic building instructions.
-
-If you're using a USB adapter and have a driver kext matched to it,
-you will need to unload it prior to running OpenOCD. E.g. with Apple
-driver (OS X 10.9 or later) for FTDI run:
-  sudo kextunload -b com.apple.driver.AppleUSBFTDI
-for FTDI vendor driver use:
-  sudo kextunload FTDIUSBSerialDriver.kext
-
-To learn more on the topic please refer to the official libusb FAQ:
-https://github.com/libusb/libusb/wiki/FAQ

README.macOS.md

@@ -0,0 +1,72 @@
+# OpenOCD for macOS
+
+This README contains instructions that are specific to macOS.
+
+## Building
+
+There are a few prerequisites you will need first:
+
+- Xcode (install from the AppStore)
+- Command Line Tools (install from Xcode -> Preferences -> Downloads)
+- One of the following tools:
+  - Gentoo Prefix (<https://wiki.gentoo.org/wiki/Project:Prefix/Bootstrap>)
+  - Homebrew (<https://brew.sh/>)
+  - MacPorts (<https://www.macports.org/install.php>)
+
+If you're building manually you need Texinfo version 5.0 or later. The
+simplest way to get it is to use Homebrew (`brew install texinfo`) and
+then `export PATH=/usr/local/opt/texinfo/bin:$PATH`.
+
+With Gentoo Prefix you can build the release version or the latest
+devel version (-9999) the usual way described in the Gentoo
+documentation. Alternatively, install the prerequisites and build
+manually from the sources.
+
+With Homebrew you can either run:
+
+```sh
+brew install [--HEAD] open-ocd
+```
+
+Where ``--HEAD`` asks ``brew`` to install the current Git version instead of the
+lastest release.
+
+You can also run:
+
+```sh
+brew install libtool automake libusb [hidapi] [libftdi]
+```
+
+to install the needed dependencies and then proceed with the manual building
+procedure.
+
+For building with MacPorts you need to run:
+
+```sh
+sudo port install libtool automake autoconf pkgconfig libusb [libftdi1]
+```
+
+You should also specify LDFLAGS and CPPFLAGS to allow `configure` to use
+MacPorts' libraries, so run configure like this:
+
+```sh
+LDFLAGS=-L/opt/local/lib CPPFLAGS=-I/opt/local/include ./configure [options]
+```
+
+See [README](README.md) for the generic building instructions.
+
+If you're using a USB adapter and have a driver kext matched to it,
+you will need to unload it prior to running OpenOCD. E.g. with Apple
+driver (OS X 10.9 or later) for FTDI run:
+
+```sh
+sudo kextunload -b com.apple.driver.AppleUSBFTDI
+```
+
+for FTDI vendor driver use:
+
+```sh
+sudo kextunload FTDIUSBSerialDriver.kext
+```
+
+To learn more on the topic please refer to the official libusb FAQ: <https://github.com/libusb/libusb/wiki/FAQ>

README.md

@@ -1,5 +1,4 @@
-Welcome to OpenOCD!
-===================
+# Welcome to OpenOCD
 
 OpenOCD provides on-chip programming and debugging support with a
 layered architecture of JTAG interface and TAP support including:
@@ -9,10 +8,10 @@ layered architecture of JTAG interface and TAP support including:
 - debug target support (e.g. ARM, MIPS): single-stepping,
   breakpoints/watchpoints, gprof profiling, etc;
 - flash chip drivers (e.g. CFI, NAND, internal flash);
-- embedded TCL interpreter for easy scripting.
+- embedded Tcl interpreter for easy scripting.
 
 Several network interfaces are available for interacting with OpenOCD:
-telnet, TCL, and GDB. The GDB server enables OpenOCD to function as a
+telnet, Tcl, and GDB. The GDB server enables OpenOCD to function as a
 "remote target" for source-level debugging of embedded systems using
 the GNU GDB program (and the others who talk GDB protocol, e.g. IDA
 Pro).
@@ -25,147 +24,78 @@ This README file contains an overview of the following topics:
 - the installation and build process,
 - packaging tips.
 
-
-============================
-Quickstart for the impatient
-============================
+## Quickstart for the impatient
 
 If you have a popular board then just start OpenOCD with its config,
 e.g.:
 
-  openocd -f board/stm32f4discovery.cfg
+```sh
+openocd -f board/stm32f4discovery.cfg
+```
 
 If you are connecting a particular adapter with some specific target,
 you need to source both the jtag interface and the target configs,
 e.g.:
 
-  openocd -f interface/ftdi/jtagkey2.cfg -c "transport select jtag" \
-          -f target/ti_calypso.cfg
+```sh
+openocd -f interface/ftdi/jtagkey2.cfg -c "transport select jtag" \
+        -f target/ti/calypso.cfg
+```
 
-  openocd -f interface/stlink.cfg -c "transport select hla_swd" \
-          -f target/stm32l0.cfg
+```sh
+openocd -f interface/stlink.cfg -c "transport select swd" \
+        -f target/stm32l0.cfg
+```
 
 After OpenOCD startup, connect GDB with
 
-  (gdb) target extended-remote localhost:3333
+```gdb
+(gdb) target extended-remote localhost:3333
+```
 
+## Installing OpenOCD
 
-=====================
-OpenOCD Documentation
-=====================
+The easiest way to install OpenOCD is through your operating system's package
+manager.
 
-In addition to the in-tree documentation, the latest manuals may be
-viewed online at the following URLs:
+- Debian / Ubuntu
 
-  OpenOCD User's Guide:
-    http://openocd.org/doc/html/index.html
+  ```sh
+  sudo apt install openocd
+  ```
 
-  OpenOCD Developer's Manual:
-    http://openocd.org/doc/doxygen/html/index.html
+- Fedora
 
-These reflect the latest development versions, so the following section
-introduces how to build the complete documentation from the package.
+  ```sh
+  sudo dnf install openocd
+  ```
 
-For more information, refer to these documents or contact the developers
-by subscribing to the OpenOCD developer mailing list:
+- macOS (via Homebrew)
 
-	openocd-devel@lists.sourceforge.net
+  ```sh
+  brew install open-ocd
+  ```
 
-Building the OpenOCD Documentation
-----------------------------------
+- Windows (via MSYS2)
 
-By default the OpenOCD build process prepares documentation in the
-"Info format" and installs it the standard way, so that "info openocd"
-can access it.
+  ```sh
+  pacman -S mingw-w64-x86_64-openocd
+  ```
 
-Additionally, the OpenOCD User's Guide can be produced in the
-following different formats:
+These packages are often more stable than the bleeding-edge Git mainline, where
+active development happens.
+"Packagers" create binary releases of OpenOCD after the developers publish new
+source code releases.
+Older OpenOCD versions are not suitable for diagnosing issues in the current
+release.
+Users should stay in touch with their distribution maintainers or interface
+vendors to ensure that appropriate updates are provided regularly.
 
-  # If PDFVIEWER is set, this creates and views the PDF User Guide.
-  make pdf && ${PDFVIEWER} doc/openocd.pdf
+If you use one of these binary packages, you must contact the Packager for
+support or for newer binary versions.
+The OpenOCD developers do not provide direct support for packaged binaries.
 
-  # If HTMLVIEWER is set, this creates and views the HTML User Guide.
-  make html && ${HTMLVIEWER} doc/openocd.html/index.html
-
-The OpenOCD Developer Manual contains information about the internal
-architecture and other details about the code:
-
-  # NB! make sure doxygen is installed, type doxygen --version
-  make doxygen && ${HTMLVIEWER} doxygen/index.html
-
-
-==================
-Supported hardware
-==================
-
-JTAG adapters
--------------
-
-AICE, AM335x, ARM-JTAG-EW, ARM-USB-OCD, ARM-USB-TINY, AT91RM9200, axm0432, BCM2835,
-Bus Blaster, Buspirate, Cadence DPI, Cadence vdebug, Chameleon, CMSIS-DAP,
-Cortino, Cypress KitProg, DENX, Digilent JTAG-SMT2, DLC 5, DLP-USB1232H,
-embedded projects, Espressif USB JTAG Programmer,
-eStick, FlashLINK, FlossJTAG, Flyswatter, Flyswatter2,
-FTDI FT232R, Gateworks, Hoegl, ICDI, ICEBear, J-Link, JTAG VPI, JTAGkey,
-JTAGkey2, JTAG-lock-pick, KT-Link, Linux GPIOD, Lisa/L, LPC1768-Stick,
-Mellanox rshim, MiniModule, NGX, Nuvoton Nu-Link, Nu-Link2, NXHX, NXP IMX GPIO,
-OOCDLink, Opendous, OpenJTAG, Openmoko, OpenRD, OSBDM, Presto, Redbee,
-Remote Bitbang, RLink, SheevaPlug devkit, Stellaris evkits,
-ST-LINK (SWO tracing supported), STM32-PerformanceStick, STR9-comStick,
-sysfsgpio, Tigard, TI XDS110, TUMPA, Turtelizer, ULINK, USB-A9260, USB-Blaster,
-USB-JTAG, USBprog, VPACLink, VSLLink, Wiggler, XDS100v2, Xilinx XVC/PCIe,
-Xverve.
-
-Debug targets
--------------
-
-ARM: AArch64, ARM11, ARM7, ARM9, Cortex-A/R (v7-A/R), Cortex-M (ARMv{6/7/8}-M),
-FA526, Feroceon/Dragonite, XScale.
-ARCv2, AVR32, DSP563xx, DSP5680xx, EnSilica eSi-RISC, EJTAG (MIPS32, MIPS64),
-ESP32, ESP32-S2, ESP32-S3, Intel Quark, LS102x-SAP, NDS32, RISC-V, ST STM8,
-Xtensa.
-
-Flash drivers
--------------
-
-ADUC702x, AT91SAM, AT91SAM9 (NAND), ATH79, ATmega128RFA1, Atmel SAM, AVR, CFI,
-DSP5680xx, EFM32, EM357, eSi-RISC, eSi-TSMC, EZR32HG, FM3, FM4, Freedom E SPI,
-GD32, i.MX31, Kinetis, LPC8xx/LPC1xxx/LPC2xxx/LPC541xx, LPC2900, LPC3180, LPC32xx,
-LPCSPIFI, Marvell QSPI, MAX32, Milandr, MXC, NIIET, nRF51, nRF52 , NuMicro,
-NUC910, Nuvoton NPCX, onsemi RSL10, Orion/Kirkwood, PIC32mx, PSoC4/5LP/6,
-Raspberry RP2040, Renesas RPC HF and SH QSPI,
-S3C24xx, S3C6400, SiM3x, SiFive Freedom E, Stellaris, ST BlueNRG, STM32,
-STM32 QUAD/OCTO-SPI for Flash/FRAM/EEPROM, STMSMI, STR7x, STR9x, SWM050,
-TI CC13xx, TI CC26xx, TI CC32xx, TI MSP432, Winner Micro w600, Xilinx XCF,
-XMC1xxx, XMC4xxx.
-
-
-==================
-Installing OpenOCD
-==================
-
-A Note to OpenOCD Users
------------------------
-
-If you would rather be working "with" OpenOCD rather than "on" it, your
-operating system or JTAG interface supplier may provide binaries for
-you in a convenient-enough package.
-
-Such packages may be more stable than git mainline, where
-bleeding-edge development takes place. These "Packagers" produce
-binary releases of OpenOCD after the developers produces new "release"
-versions of the source code. Previous versions of OpenOCD cannot be
-used to diagnose problems with the current release, so users are
-encouraged to keep in contact with their distribution package
-maintainers or interface vendors to ensure suitable upgrades appear
-regularly.
-
-Users of these binary versions of OpenOCD must contact their Packager to
-ask for support or newer versions of the binaries; the OpenOCD
-developers do not support packages directly.
-
-A Note to OpenOCD Packagers
----------------------------
+## A Note to OpenOCD Packagers
 
 You are a PACKAGER of OpenOCD if you:
 
@@ -191,21 +121,107 @@ suggestions:
   particular hardware;
 - Use "ftdi" interface adapter driver for the FTDI-based devices.
 
+## OpenOCD Documentation
 
-================
-Building OpenOCD
-================
+In addition to the in-tree documentation, the latest manuals may be
+viewed online at the following URLs:
 
-The INSTALL file contains generic instructions for running 'configure'
+- OpenOCD User's Guide: <http://openocd.org/doc/html/index.html>
+
+- OpenOCD Developer's Manual: <http://openocd.org/doc/doxygen/html/index.html>
+
+These reflect the latest development versions, so the following section
+introduces how to build the complete documentation from the package.
+
+For more information, refer to these documents or contact the developers
+by subscribing to the OpenOCD developer mailing list: openocd-devel@lists.sourceforge.net
+
+### Building the OpenOCD Documentation
+
+By default the OpenOCD build process prepares documentation in the
+"Info format" and installs it the standard way, so that `info openocd`
+can access it.
+
+Additionally, the OpenOCD User's Guide can be produced in the
+following different formats:
+
+If `PDFVIEWER` is set, this creates and views the PDF User Guide.
+
+```sh
+make pdf && ${PDFVIEWER} doc/openocd.pdf
+```
+
+If `HTMLVIEWER` is set, this creates and views the HTML User Guide.
+
+```sh
+make html && ${HTMLVIEWER} doc/openocd.html/index.html
+```
+
+The OpenOCD Developer Manual contains information about the internal
+architecture and other details about the code:
+
+Note: make sure doxygen is installed, type doxygen --version
+
+```sh
+make doxygen && ${HTMLVIEWER} doxygen/index.html
+```
+
+## Supported hardware
+
+### JTAG adapters
+
+AM335x, ARM-JTAG-EW, ARM-USB-OCD, ARM-USB-TINY, AT91RM9200, axm0432, BCM2835,
+Bus Blaster, Buspirate, Cadence DPI, Cadence vdebug, Chameleon, CMSIS-DAP,
+Cortino, Cypress KitProg, DENX, Digilent JTAG-SMT2, DLC 5, DLP-USB1232H,
+embedded projects, Espressif USB JTAG Programmer,
+eStick, FlashLINK, FlossJTAG, Flyswatter, Flyswatter2,
+FTDI FT232R, Gateworks, Hoegl, ICDI, ICEBear, J-Link, JTAG VPI, JTAGkey,
+JTAGkey2, JTAG-lock-pick, KT-Link, Linux GPIOD, Lisa/L, LPC1768-Stick,
+Mellanox rshim, MiniModule, NGX, Nuvoton Nu-Link, Nu-Link2, NXHX, NXP IMX GPIO,
+OOCDLink, Opendous, OpenJTAG, Openmoko, OpenRD, OSBDM, Presto, Redbee,
+Remote Bitbang, RLink, SheevaPlug devkit, Stellaris evkits,
+ST-LINK (SWO tracing supported), STM32-PerformanceStick, STR9-comStick,
+sysfsgpio, Tigard, TI XDS110, TUMPA, Turtelizer, ULINK, USB-A9260, USB-Blaster,
+USB-JTAG, USBprog, VPACLink, VSLLink, Wiggler, XDS100v2, Xilinx XVC/PCIe,
+Xverve.
+
+### Debug targets
+
+ARM: AArch64, ARM11, ARM7, ARM9, Cortex-A/R (v7-A/R), Cortex-M (ARMv{6/7/8}-M),
+FA526, Feroceon/Dragonite, XScale.
+ARCv2, AVR32, DSP563xx, DSP5680xx, EnSilica eSi-RISC, EJTAG (MIPS32, MIPS64),
+ESP32, ESP32-S2, ESP32-S3, Intel Quark, LS102x-SAP, RISC-V, ST STM8,
+Xtensa.
+
+### Flash drivers
+
+ADUC702x, AT91SAM, AT91SAM9 (NAND), ATH79, ATmega128RFA1, Atmel SAM, AVR, CFI,
+DSP5680xx, EFM32, EM357, eSi-RISC, eSi-TSMC, EZR32HG, FM3, FM4, Freedom E SPI,
+GD32, i.MX31, Kinetis, LPC8xx/LPC1xxx/LPC2xxx/LPC541xx, LPC2900, LPC3180, LPC32xx,
+LPCSPIFI, Marvell QSPI, MAX32, Milandr, MXC, NIIET, nRF51, nRF52 , NuMicro,
+NUC910, Nuvoton NPCX, onsemi RSL10, Orion/Kirkwood, PIC32mx, PSoC4/5LP/6,
+Raspberry RP2040, Renesas RPC HF and SH QSPI,
+S3C24xx, S3C6400, SiM3x, SiFive Freedom E, Stellaris, ST BlueNRG, STM32,
+STM32 QUAD/OCTO-SPI for Flash/FRAM/EEPROM, STMSMI, STR7x, STR9x, SWM050,
+TI CC13xx, TI CC26xx, TI CC32xx, TI MSP432, Winner Micro w600, Xilinx XCF,
+XMC1xxx, XMC4xxx.
+
+## Building OpenOCD
+
+The INSTALL file contains generic instructions for running `configure`
 and compiling the OpenOCD source code. That file is provided by
 default for all GNU autotools packages. If you are not familiar with
 the GNU autotools, then you should read those instructions first.
 
+Note: if the INSTALL file is not present, it means you are using the
+source code from a development branch, not from an OpenOCD release.
+In this case, follow the instructions 'Compiling OpenOCD' below and
+the file will be created by the first command `./bootstrap`.
+
 The remainder of this document tries to provide some instructions for
 those looking for a quick-install.
 
-OpenOCD Dependencies
---------------------
+### OpenOCD Dependencies
 
 GCC or Clang is currently required to build OpenOCD. The developers
 have begun to enforce strict code warnings (-Wall, -Werror, -Wextra,
@@ -219,25 +235,113 @@ You'll also need:
 
 - make
 - libtool
-- pkg-config >= 0.23 (or compatible)
+- pkg-config >= 0.23 or pkgconf
+- libjim >= 0.79
 
-Additionally, for building from git:
+Additionally, for building from Git:
 
 - autoconf >= 2.69
 - automake >= 1.14
 - texinfo >= 5.0
 
-USB-based adapters depend on libusb-1.0. A compatible implementation, such as
-FreeBSD's, additionally needs the corresponding .pc files.
+Optional USB-based adapter drivers need libusb-1.0.
 
-USB-Blaster, ASIX Presto and OpenJTAG interface adapter
-drivers need:
-  - libftdi: http://www.intra2net.com/en/developer/libftdi/index.php
+Optional USB-Blaster, ASIX Presto and OpenJTAG interface adapter drivers need
+[libftdi](http://www.intra2net.com/en/developer/libftdi/index.php) library.
 
-CMSIS-DAP support needs HIDAPI library.
+Optional CMSIS-DAP adapter driver needs HIDAPI library.
 
-Permissions delegation
-----------------------
+Optional linuxgpiod adapter driver needs libgpiod library.
+
+Optional J-Link adapter driver needs libjaylink library.
+
+Optional ARM disassembly needs capstone library.
+
+Optional development script checkpatch needs:
+
+- perl
+- python
+- python-ply
+- pymarkdownlnt
+
+### Compiling OpenOCD
+
+To build OpenOCD, use the following sequence of commands:
+
+```sh
+./bootstrap
+./configure [options]
+make
+sudo make install
+```
+
+The `bootstrap` command is only necessary when building from the Git repository.
+The `configure` step generates the Makefiles required to build OpenOCD, usually
+with one or more options provided to it.
+The first 'make' step will build OpenOCD and place the final executable in './src/'.
+The final (optional) step, `make install`, places all of the files in the
+required location.
+
+To see the list of all the supported options, run `./configure --help`
+
+### Cross-compiling Options
+
+Cross-compiling is supported the standard autotools way, you just need
+to specify the cross-compiling target triplet in the --host option,
+e.g. for cross-building for Windows 32-bit with MinGW on Debian:
+
+```sh
+./configure --host=i686-w64-mingw32 [options]
+```
+
+To make pkg-config work nicely for cross-compiling, you might need an additional
+wrapper script as described at <https://autotools.io/pkgconfig/cross-compiling.html>.
+
+This is needed to tell pkg-config where to look for the target
+libraries that OpenOCD depends on. Alternatively, you can specify
+`*_CFLAGS` and `*_LIBS` environment variables directly, see `./configure
+--help` for the details.
+
+For a more or less complete script that does all this for you, see `contrib/cross-build.sh`.
+
+### Parallel Port Dongles
+
+If you want to access the parallel port using the PPDEV interface you
+have to specify both `--enable-parport` and `--enable-parport-ppdev`, since
+the later option is an option to the parport driver.
+
+The same is true for the `--enable-parport-giveio` option, you have to
+use both the `--enable-parport` and the `--enable-parport-giveio` option
+if you want to use giveio instead of ioperm parallel port access
+method.
+
+### Obtaining OpenOCD From Git
+
+You can download the current Git version with a Git client of your
+choice from the main repository: `git://git.code.sf.net/p/openocd/code`
+
+You may prefer to use a mirror:
+
+- <http://repo.or.cz/r/openocd.git>
+- git://repo.or.cz/openocd.git
+
+Using the Git command line client, you might use the following command
+to set up a local copy of the current repository (make sure there is no
+directory called "openocd" in the current directory):
+
+```sh
+git clone git://git.code.sf.net/p/openocd/code openocd
+```
+
+Then you can update that at your convenience using `git pull`.
+
+There is also a gitweb interface, which you can use either to browse the
+repository or to download arbitrary snapshots using HTTP: <http://repo.or.cz/w/openocd.git>.
+
+Snapshots are compressed tarballs of the source tree, about 1.3 MBytes
+each at this writing.
+
+## Permissions delegation
 
 Running OpenOCD with root/administrative permissions is strongly
 discouraged for security reasons.
@@ -253,90 +357,3 @@ For parallel port adapters on GNU/Linux and FreeBSD please change your
 For parport adapters on Windows you need to run install_giveio.bat
 (it's also possible to use "ioperm" with Cygwin instead) to give
 ordinary users permissions for accessing the "LPT" registers directly.
-
-Compiling OpenOCD
------------------
-
-To build OpenOCD, use the following sequence of commands:
-
-  ./bootstrap (when building from the git repository)
-  ./configure [options]
-  make
-  sudo make install
-
-The 'configure' step generates the Makefiles required to build
-OpenOCD, usually with one or more options provided to it. The first
-'make' step will build OpenOCD and place the final executable in
-'./src/'. The final (optional) step, ``make install'', places all of
-the files in the required location.
-
-To see the list of all the supported options, run
-  ./configure --help
-
-Cross-compiling Options
------------------------
-
-Cross-compiling is supported the standard autotools way, you just need
-to specify the cross-compiling target triplet in the --host option,
-e.g. for cross-building for Windows 32-bit with MinGW on Debian:
-
-  ./configure --host=i686-w64-mingw32 [options]
-
-To make pkg-config work nicely for cross-compiling, you might need an
-additional wrapper script as described at
-
-  https://autotools.io/pkgconfig/cross-compiling.html
-
-This is needed to tell pkg-config where to look for the target
-libraries that OpenOCD depends on. Alternatively, you can specify
-*_CFLAGS and *_LIBS environment variables directly, see "./configure
---help" for the details.
-
-For a more or less complete script that does all this for you, see
-
-  contrib/cross-build.sh
-
-Parallel Port Dongles
----------------------
-
-If you want to access the parallel port using the PPDEV interface you
-have to specify both --enable-parport AND --enable-parport-ppdev, since
-the later option is an option to the parport driver.
-
-The same is true for the --enable-parport-giveio option, you have to
-use both the --enable-parport AND the --enable-parport-giveio option
-if you want to use giveio instead of ioperm parallel port access
-method.
-
-
-==========================
-Obtaining OpenOCD From GIT
-==========================
-
-You can download the current GIT version with a GIT client of your
-choice from the main repository:
-
-   git://git.code.sf.net/p/openocd/code
-
-You may prefer to use a mirror:
-
-   http://repo.or.cz/r/openocd.git
-   git://repo.or.cz/openocd.git
-
-Using the GIT command line client, you might use the following command
-to set up a local copy of the current repository (make sure there is no
-directory called "openocd" in the current directory):
-
-   git clone git://git.code.sf.net/p/openocd/code openocd
-
-Then you can update that at your convenience using
-
-   git pull
-
-There is also a gitweb interface, which you can use either to browse
-the repository or to download arbitrary snapshots using HTTP:
-
-   http://repo.or.cz/w/openocd.git
-
-Snapshots are compressed tarballs of the source tree, about 1.3 MBytes
-each at this writing.

TODO

@@ -12,14 +12,14 @@ may have evolved an idea since it was added here.
 
 Feel free to send patches to add or clarify items on this list, too.
 
-@section thelisttcl TCL
+@section thelisttcl Tcl
 
-This section provides possible things to improve with OpenOCD's TCL support.
+This section provides possible things to improve with OpenOCD's Tcl support.
 
 - Fix problem with incorrect line numbers reported for a syntax
   error in a reset init event.
 
-- organize the TCL configurations:
+- organize the Tcl configurations:
   - provide more directory structure for boards/targets?
   - factor configurations into layers (encapsulation and re-use)
 
@@ -27,15 +27,15 @@ This section provides possible things to improve with OpenOCD's TCL support.
   parameters.  Currently variables assigned through one such parameter
   command/script are unset before the next one is invoked.
 
-- Isolate all TCL command support:
+- Isolate all Tcl command support:
   - Pure C CLI implementations using --disable-builtin-tcl.
     - Allow developers to build new dongles using OpenOCD's JTAG core.
     - At first, provide only low-level JTAG support; target layer and
       above rely heavily on scripting event mechanisms.
-  - Allow full TCL support? add --with-tcl=/path/to/installed/tcl
-  - Move TCL support out of foo.[ch] and into foo_tcl.[ch] (other ideas?)
+  - Allow full Tcl support? add --with-tcl=/path/to/installed/tcl
+  - Move Tcl support out of foo.[ch] and into foo_tcl.[ch] (other ideas?)
     - See src/jtag/core.c and src/jtag/tcl.c for an example.
-    - allow some of these TCL command modules to be dynamically loadable?
+    - allow some of these Tcl command modules to be dynamically loadable?
 
 @section thelistadapter Adapter
 
@@ -60,8 +60,6 @@ changes pending in gerrit.
   to replicate it in the drivers, apart in case the driver sets TRST
   independently
 - add .hla_ops to "adapter"
-- HLA is a API level (.hla_ops). Transport should simply be {jtag,swd},
-  not {hla_jtag,hla_swd}.
 
 @subsection thelistadapterjtagcore JTAG Core
 
@@ -77,7 +75,7 @@ directly in minidriver API for better embedded host performance.
 
 The following tasks have been suggested for adding new core JTAG support:
 
-- Improve autodetection of TAPs by supporting tcl escape procedures that
+- Improve autodetection of TAPs by supporting Tcl escape procedures that
   can configure discovered TAPs based on IDCODE value ... they could:
     - Remove guessing for irlen
     - Allow non-default irmask/ircapture values
@@ -135,7 +133,7 @@ TCP/IP packets handled by the server.
 - add BSDL support?
 
 A few possible options for the above:
-  -# Fake a TCL equivalent?
+  -# Fake a Tcl equivalent?
   -# Integrate an existing library?
   -# Write a new C implementation a la Jim?
 
@@ -202,8 +200,6 @@ https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html
 - MC1322x support (JW/DE?)
   - integrate and test support from JW (and DE?)
   - get working with a known good interface (i.e. not today's jlink)
-- AT91SAM92xx:
-  - improvements for unknown-board-atmel-at91sam9260.cfg (RD)
 - STR9x: (ZW)
   - improvements to str912.cfg to be more general purpose
 - AVR: (SQ)

bootstrap

@@ -3,8 +3,8 @@
 
 # Run the autotools bootstrap sequence to create the configure script
 
-# Abort execution on error
-set -e
+set -e  # Abort execution on error.
+set -u  # Abort if you reference an undefined variable.
 
 if which libtoolize > /dev/null; then
     libtoolize="libtoolize"
@@ -15,13 +15,23 @@ else
     exit 1
 fi
 
-if [ "$1" = "nosubmodule" ]; then
-    SKIP_SUBMODULE=1
-elif [ -n "$1" ]; then
-    echo "$0: Illegal argument $1"
-    echo "USAGE: $0 [nosubmodule]"
-    exit 1
-fi
+WITH_SUBMODULES=0
+
+case "$#" in
+    0) ;;
+    1) if [ "$1" = "with-submodules" ]; then
+           WITH_SUBMODULES=1
+       elif [ "$1" = "nosubmodule" ]; then
+           WITH_SUBMODULES=0
+       elif [ -n "$1" ]; then
+           echo "$0: Illegal argument $1" >&2
+           echo "USAGE: $0 [with-submodules]" >&2
+           exit 1
+       fi;;
+   *)  echo "$0: Wrong number of command-line arguments." >&2
+       echo "USAGE: $0 [with-submodules]" >&2
+       exit 1;;
+esac
 
 # bootstrap the autotools
 (
@@ -34,12 +44,12 @@ autoheader --warnings=all
 automake --warnings=all --gnu --add-missing --copy
 )
 
-if [ -n "$SKIP_SUBMODULE" ]; then
-    echo "Skipping submodule setup"
-else
+if [ "$WITH_SUBMODULES" -ne 0 ]; then
     echo "Setting up submodules"
-    git submodule init
-    git submodule update
+    git submodule sync
+    git submodule update --init
+else
+    echo "Skipping submodule setup"
 fi
 
 if [ -x src/jtag/drivers/libjaylink/autogen.sh ]; then

config_subdir.m4

@@ -7,6 +7,6 @@ AC_DEFUN([AX_CONFIG_SUBDIR_OPTION],
 AC_CONFIG_SUBDIRS([$1])
 
 m4_ifblank([$2], [rm -f $srcdir/$1/configure.gnu],
-[echo -e '#!/bin/sh\nexec "`dirname "'\$'0"`/configure" '"$2"' "'\$'@"' > "$srcdir/$1/configure.gnu"
+[printf '#!/bin/sh\nexec "`dirname "'\$'0"`/configure" '"$2"' "'\$'@"\n' > "$srcdir/$1/configure.gnu"
 ])
 ])

configure.ac

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 AC_PREREQ([2.69])
-AC_INIT([openocd], [0.12.0-rc1],
+AC_INIT([openocd], [0.12.0+dev],
   [OpenOCD Mailing List <openocd-devel@lists.sourceforge.net>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 AC_CONFIG_AUX_DIR([build-aux])
@@ -16,7 +16,7 @@ AS_IF([test "x$MAKEINFO" = "x"], [
 ])
 AC_SUBST([MAKEINFO])
 
-AM_INIT_AUTOMAKE([-Wall -Wno-portability dist-bzip2 dist-zip subdir-objects])
+AM_INIT_AUTOMAKE([foreign -Wall -Wno-portability dist-bzip2 dist-zip subdir-objects])
 
 AC_CONFIG_HEADERS([config.h])
 
@@ -24,7 +24,6 @@ AC_LANG([C])
 AC_PROG_CC
 # autoconf 2.70 obsoletes AC_PROG_CC_C99 and includes it in AC_PROG_CC
 m4_version_prereq([2.70],[],[AC_PROG_CC_C99])
-AM_PROG_CC_C_O
 AC_PROG_RANLIB
 
 # If macro PKG_PROG_PKG_CONFIG is not available, Autoconf generates a misleading error message,
@@ -52,15 +51,19 @@ AC_SEARCH_LIBS([openpty], [util])
 
 AC_CHECK_HEADERS([sys/socket.h])
 AC_CHECK_HEADERS([elf.h])
-AC_EGREP_HEADER(Elf64_Ehdr, [elf.h], [
-  AC_DEFINE([HAVE_ELF64], [1], [Define to 1 if the system has the type `Elf64_Ehdr'.])
-])
+
+AC_CHECK_TYPE([Elf64_Ehdr],
+	AC_DEFINE([HAVE_ELF64], [1], [Define to 1 if the system has the type 'Elf64_Ehdr'.]),
+	[], [[#include <elf.h>]])
+
 AC_CHECK_HEADERS([fcntl.h])
-AC_CHECK_HEADERS([malloc.h])
+AC_CHECK_HEADERS([linux/pci.h])
+AC_CHECK_HEADERS([linux/spi/spidev.h])
 AC_CHECK_HEADERS([netdb.h])
 AC_CHECK_HEADERS([poll.h])
 AC_CHECK_HEADERS([strings.h])
 AC_CHECK_HEADERS([sys/ioctl.h])
+AC_CHECK_HEADERS([sys/mman.h])
 AC_CHECK_HEADERS([sys/param.h])
 AC_CHECK_HEADERS([sys/select.h])
 AC_CHECK_HEADERS([sys/stat.h])
@@ -93,6 +96,8 @@ AC_CHECK_FUNCS([strnlen])
 AC_CHECK_FUNCS([gettimeofday])
 AC_CHECK_FUNCS([usleep])
 AC_CHECK_FUNCS([realpath])
+AC_CHECK_FUNCS([mallinfo])
+AC_CHECK_FUNCS([mallinfo2])
 
 # guess-rev.sh only exists in the repository, not in the released archives
 AC_MSG_CHECKING([whether to build a release])
@@ -104,37 +109,46 @@ AS_IF([test -x "$srcdir/guess-rev.sh"], [
 AC_MSG_RESULT([$build_release])
 
 # Adapter drivers
-# 1st column -- configure option
-# 2nd column -- description
-# 3rd column -- symbol used for both config.h and automake
+# 1st column -- Basename for the configure option generated with AC_ARG_ENABLE.
+#               For example, "buspirate" generates options "--enable-buspirate[=yes/no]"
+#               and "--disable-buspirate".
+# 2nd column -- Description for the configure option. For example, "Bus Pirate"
+#               generates "Enable building support for the Bus Pirate (default is auto)".
+# 3rd column -- Basename for the config.h and Automake symbols.
+#               For example, basename "BUS_PIRATE" generates "BUILD_BUS_PIRATE" with AC_DEFINE
+#               for config.h and "BUS_PIRATE" with AM_CONDITIONAL for Automake.
 m4_define([ADAPTER_ARG], [m4_argn([1], $1)])
 m4_define([ADAPTER_DESC], [m4_argn([2], $1)])
 m4_define([ADAPTER_SYM], [m4_argn([3], $1)])
+# AC_ARG_ENABLE uses prefix "enable_" to name the corresponding option variable.
 m4_define([ADAPTER_VAR], [enable_[]ADAPTER_ARG($1)])
 m4_define([ADAPTER_OPT], [m4_translit(ADAPTER_ARG($1), [_], [-])])
 
 m4_define([USB1_ADAPTERS],
 	[[[ftdi], [MPSSE mode of FTDI based devices], [FTDI]],
+	[[ftdi_cjtag], [cJTAG (OScan1, JScan3) tunneled thru MPSSE], [FTDI_CJTAG]],
+	[[ch347], [CH347 based devices], [CH347]],
 	[[stlink], [ST-Link Programmer], [HLADAPTER_STLINK]],
 	[[ti_icdi], [TI ICDI JTAG Programmer], [HLADAPTER_ICDI]],
 	[[ulink], [Keil ULINK JTAG Programmer], [ULINK]],
+	[[angie], [ANGIE Adapter], [ANGIE]],
 	[[usb_blaster_2], [Altera USB-Blaster II Compatible], [USB_BLASTER_2]],
 	[[ft232r], [Bitbang mode of FT232R based devices], [FT232R]],
 	[[vsllink], [Versaloon-Link JTAG Programmer], [VSLLINK]],
 	[[xds110], [TI XDS110 Debug Probe], [XDS110]],
-	[[cmsis_dap_v2], [CMSIS-DAP v2 Compliant Debugger], [CMSIS_DAP_USB]],
 	[[osbdm], [OSBDM (JTAG only) Programmer], [OSBDM]],
 	[[opendous], [eStick/opendous JTAG Programmer], [OPENDOUS]],
 	[[armjtagew], [Olimex ARM-JTAG-EW Programmer], [ARMJTAGEW]],
 	[[rlink], [Raisonance RLink JTAG Programmer], [RLINK]],
 	[[usbprog], [USBProg JTAG Programmer], [USBPROG]],
-	[[esp_usb_jtag], [Espressif JTAG Programmer], [ESP_USB_JTAG]]])
+	[[esp_usb_jtag], [Espressif JTAG Programmer], [ESP_USB_JTAG]],
+	[[cmsis_dap_v2], [CMSIS-DAP v2 compliant dongle (USB bulk)], [CMSIS_DAP_USB]]])
 
-m4_define([DEPRECATED_USB1_ADAPTERS],
-	[[[aice], [Andes JTAG Programmer (deprecated)], [AICE]]])
+# Please keep cmsis_dap_v2 the last in USB1_ADAPTERS
+# and cmsis_dap the first in HIDAPI_ADAPTERS
 
 m4_define([HIDAPI_ADAPTERS],
-	[[[cmsis_dap], [CMSIS-DAP Compliant Debugger], [CMSIS_DAP_HID]],
+	[[[cmsis_dap], [CMSIS-DAP v1 compliant dongle (HID)], [CMSIS_DAP_HID]],
 	[[nulink], [Nu-Link Programmer], [HLADAPTER_NULINK]]])
 
 m4_define([HIDAPI_USB1_ADAPTERS],
@@ -150,18 +164,65 @@ m4_define([LIBFTDI_USB1_ADAPTERS],
 m4_define([LIBGPIOD_ADAPTERS],
 	[[[linuxgpiod], [Linux GPIO bitbang through libgpiod], [LINUXGPIOD]]])
 
+m4_define([DMEM_ADAPTER],
+	[[[dmem], [CoreSight Direct Memory], [DMEM]]])
+
+m4_define([SYSFSGPIO_ADAPTER],
+	[[[sysfsgpio], [Linux GPIO bitbang through sysfs], [SYSFSGPIO]]])
+
+m4_define([REMOTE_BITBANG_ADAPTER],
+	[[[remote_bitbang], [Remote Bitbang driver], [REMOTE_BITBANG]]])
+
 m4_define([LIBJAYLINK_ADAPTERS],
 	[[[jlink], [SEGGER J-Link Programmer], [JLINK]]])
 
-m4_define([PCIE_ADAPTERS],
-	[[[xlnx_pcie_xvc], [Xilinx XVC/PCIe], [XLNX_PCIE_XVC]]])
+m4_define([XVC_ADAPTERS],
+	[[[xlnx_xvc], [Xilinx XVC PCIe and AXI drives], [XLNX_XVC]]])
 
 m4_define([SERIAL_PORT_ADAPTERS],
 	[[[buspirate], [Bus Pirate], [BUS_PIRATE]]])
 
+m4_define([PARALLEL_PORT_ADAPTER],
+	[[[parport], [PC Parallel Port], [PARPORT]]])
+
+m4_define([LINUXSPIDEV_ADAPTER],
+	[[[linuxspidev], [Linux spidev driver], [LINUXSPIDEV]]])
+m4_define([VDEBUG_ADAPTER],
+	[[[vdebug], [Cadence Virtual Debug Interface], [VDEBUG]]])
+
+m4_define([JTAG_DPI_ADAPTER],
+	[[[jtag_dpi], [JTAG DPI Adapter], [JTAG_DPI]]])
+
+m4_define([JTAG_VPI_ADAPTER],
+	[[[jtag_vpi], [JTAG VPI Adapter], [JTAG_VPI]]])
+
+m4_define([RSHIM_ADAPTER],
+	[[[rshim], [BlueField SoC via rshim], [RSHIM]]])
+
+m4_define([AMTJTAGACCEL_ADAPTER],
+	[[[amtjtagaccel], [Amontec JTAG-Accelerator driver], [AMTJTAGACCEL]]])
+
+m4_define([CMSIS_DAP_TCP_ADAPTER],
+	[[[cmsis_dap_tcp], [CMSIS-DAP v2 compliant dongle (TCP)], [CMSIS_DAP_TCP]]])
+
+m4_define([HOST_ARM_BITBANG_ADAPTERS],
+	[[[ep93xx], [Bitbanging on EP93xx-based SBCs], [EP93XX]],
+	[[at91rm9200], [Bitbanging on AT91RM9200-based SBCs], [AT91RM9200]]])
+
+m4_define([HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS],
+	[[[bcm2835gpio], [Bitbanging on BCM2835 (as found in Raspberry Pi)], [BCM2835GPIO]],
+	[[imx_gpio], [Bitbanging on NXP IMX processors], [IMX_GPIO]],
+	[[am335xgpio], [Bitbanging on AM335x (as found in Beaglebones)], [AM335XGPIO]]])
+
+m4_define([DUMMY_ADAPTER],
+	[[[dummy], [Dummy Adapter], [DUMMY]]])
+
 m4_define([OPTIONAL_LIBRARIES],
 	[[[capstone], [Use Capstone disassembly framework], []]])
 
+m4_define([COVERAGE],
+	[[[gcov], [Collect coverage using gcov], []]])
+
 AC_ARG_ENABLE([doxygen-html],
   AS_HELP_STRING([--disable-doxygen-html],
     [Disable building Doxygen manual as HTML.]),
@@ -190,66 +251,29 @@ AC_ARG_ENABLE([werror],
   AS_HELP_STRING([--disable-werror], [Do not treat warnings as errors]),
   [gcc_werror=$enableval], [gcc_werror=$gcc_warnings])
 
-# set default verbose options, overridden by following options
-debug_usb_io=no
-debug_usb_comms=no
+AC_ARG_ENABLE([gcov],
+  AS_HELP_STRING([--enable-gcov], [Enable runtime coverage collection via gcov]),
+  [enable_gcov=$enableval], [enable_gcov=no])
 
-AC_ARG_ENABLE([verbose],
-  AS_HELP_STRING([--enable-verbose],
-      [Enable verbose JTAG I/O messages (for debugging).]),
-  [
-  debug_usb_io=$enableval
-  debug_usb_comms=$enableval
-  ], [])
-
-AC_ARG_ENABLE([verbose_usb_io],
-  AS_HELP_STRING([--enable-verbose-usb-io],
-      [Enable verbose USB I/O messages (for debugging)]),
-  [debug_usb_io=$enableval], [])
-
-AC_ARG_ENABLE([verbose_usb_comms],
-  AS_HELP_STRING([--enable-verbose-usb-comms],
-      [Enable verbose USB communication messages (for debugging)]),
-  [debug_usb_comms=$enableval], [])
-
-AC_MSG_CHECKING([whether to enable verbose USB I/O messages]);
-AC_MSG_RESULT([$debug_usb_io])
-AS_IF([test "x$debug_usb_io" = "xyes"], [
-  AC_DEFINE([_DEBUG_USB_IO_],[1], [Print verbose USB I/O messages])
+AS_IF([test "x$enable_gcov" = "xyes"], [
+  AC_DEFINE([USE_GCOV], [1], [1 to enable coverage collection using gcov.])
+  dnl When collecting coverage, disable optimizations.
+  dnl This overrides the "-O2" that autoconf uses by default:
+  CFLAGS+=" -O0"
+], [
+  AC_DEFINE([USE_GCOV], [0], [0 to leave coverage collection disabled.])
 ])
 
-AC_MSG_CHECKING([whether to enable verbose USB communication messages]);
-AC_MSG_RESULT([$debug_usb_comms])
-AS_IF([test "x$debug_usb_comms" = "xyes"], [
-  AC_DEFINE([_DEBUG_USB_COMMS_],[1], [Print verbose USB communication messages])
-])
-
-debug_malloc=no
-AC_ARG_ENABLE([malloc_logging],
-  AS_HELP_STRING([--enable-malloc-logging],
-      [Include free space in logging messages (requires malloc.h).]),
-  [debug_malloc=$enableval], [])
-
-AC_MSG_CHECKING([whether to enable malloc free space logging]);
-AC_MSG_RESULT([$debug_malloc])
-AS_IF([test "x$debug_malloc" = "xyes"], [
-  AC_DEFINE([_DEBUG_FREE_SPACE_],[1], [Include malloc free space in logging])
-])
-
-AC_ARG_ENABLE([dummy],
-  AS_HELP_STRING([--enable-dummy], [Enable building the dummy port driver]),
-  [build_dummy=$enableval], [build_dummy=no])
-
-AC_ARG_ENABLE([rshim],
-  AS_HELP_STRING([--enable-rshim], [Enable building the rshim driver]),
-  [build_rshim=$enableval], [build_rshim=no])
-
 m4_define([AC_ARG_ADAPTERS], [
-  m4_foreach([adapter], [$1],
-	[AC_ARG_ENABLE(ADAPTER_OPT([adapter]),
-		AS_HELP_STRING([--enable-ADAPTER_OPT([adapter])],
-			[Enable building support for the ]ADAPTER_DESC([adapter])[ (default is $2)]),
-		[], [ADAPTER_VAR([adapter])=$2])
+  m4_foreach([adapter_driver], [$1],
+	[AC_ARG_ENABLE(ADAPTER_OPT([adapter_driver]),
+		AS_HELP_STRING([--enable-ADAPTER_OPT([adapter_driver])[[[=yes/no/auto]]]],
+			[Enable building support for the ]ADAPTER_DESC([adapter_driver])[ (default is $2)]),
+		[case "${enableval}" in
+			yes|no|auto) ;;
+			*) AC_MSG_ERROR([Option --enable-ADAPTER_OPT([adapter_driver]) has invalid value "${enableval}".]) ;;
+			esac],
+		[ADAPTER_VAR([adapter_driver])=$2])
   ])
 ])
 
@@ -258,17 +282,37 @@ AC_ARG_ADAPTERS([
   HIDAPI_ADAPTERS,
   HIDAPI_USB1_ADAPTERS,
   LIBFTDI_ADAPTERS,
-  LIBFTDI_USB1_ADAPTERS
+  LIBFTDI_USB1_ADAPTERS,
   LIBGPIOD_ADAPTERS,
+  DMEM_ADAPTER,
+  SYSFSGPIO_ADAPTER,
+  REMOTE_BITBANG_ADAPTER,
+  LINUXSPIDEV_ADAPTER,
   SERIAL_PORT_ADAPTERS,
-  LIBJAYLINK_ADAPTERS
+  DUMMY_ADAPTER,
+  VDEBUG_ADAPTER,
+  JTAG_DPI_ADAPTER,
+  JTAG_VPI_ADAPTER,
+  RSHIM_ADAPTER,
+  XVC_ADAPTERS,
+  LIBJAYLINK_ADAPTERS,
+  CMSIS_DAP_TCP_ADAPTER
   ],[auto])
 
-AC_ARG_ADAPTERS([DEPRECATED_USB1_ADAPTERS],[no])
+AC_ARG_ADAPTERS([
+  PARALLEL_PORT_ADAPTER,
+  AMTJTAGACCEL_ADAPTER
+  ],[no])
 
-AC_ARG_ENABLE([parport],
-  AS_HELP_STRING([--enable-parport], [Enable building the pc parallel port driver]),
-  [build_parport=$enableval], [build_parport=no])
+# The following adapters use bitbanging and can actually be built on all architectures,
+# which is useful to verify that they still build fine.
+# We could enable them automatically only on the architectures where they actually occur:
+# HOST_ARM_BITBANG_ADAPTERS:            when ${host_cpu} matches arm*
+# HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS: when ${host_cpu} matches arm*|aarch64
+# However, conditionally changing the meaning of 'auto' requires
+# a more flexible logic around.
+AC_ARG_ADAPTERS([HOST_ARM_BITBANG_ADAPTERS],[no])
+AC_ARG_ADAPTERS([HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS],[no])
 
 AC_ARG_ENABLE([parport_ppdev],
   AS_HELP_STRING([--disable-parport-ppdev],
@@ -277,121 +321,60 @@ AC_ARG_ENABLE([parport_ppdev],
 
 AC_ARG_ENABLE([parport_giveio],
     AS_HELP_STRING([--enable-parport-giveio],
-      [Enable use of giveio for parport (for CygWin only)]),
+      [Enable use of giveio for parport (deprecated, for CygWin only)]),
     [parport_use_giveio=$enableval], [parport_use_giveio=])
 
-AC_ARG_ENABLE([jtag_vpi],
-  AS_HELP_STRING([--enable-jtag_vpi], [Enable building support for JTAG VPI]),
-  [build_jtag_vpi=$enableval], [build_jtag_vpi=no])
-
-AC_ARG_ENABLE([vdebug],
-  AS_HELP_STRING([--enable-vdebug], [Enable building support for Cadence Virtual Debug Interface]),
-  [build_vdebug=$enableval], [build_vdebug=no])
-
-AC_ARG_ENABLE([jtag_dpi],
-  AS_HELP_STRING([--enable-jtag_dpi], [Enable building support for JTAG DPI]),
-  [build_jtag_dpi=$enableval], [build_jtag_dpi=no])
-
-AC_ARG_ENABLE([amtjtagaccel],
-  AS_HELP_STRING([--enable-amtjtagaccel], [Enable building the Amontec JTAG-Accelerator driver]),
-  [build_amtjtagaccel=$enableval], [build_amtjtagaccel=no])
-
-AS_CASE(["${host_cpu}"],
-  [arm*|aarch64], [
-    AC_ARG_ENABLE([bcm2835gpio],
-      AS_HELP_STRING([--enable-bcm2835gpio], [Enable building support for bitbanging on BCM2835 (as found in Raspberry Pi)]),
-      [build_bcm2835gpio=$enableval], [build_bcm2835gpio=no])
-    AC_ARG_ENABLE([imx_gpio],
-      AS_HELP_STRING([--enable-imx_gpio], [Enable building support for bitbanging on NXP IMX processors]),
-      [build_imx_gpio=$enableval], [build_imx_gpio=no])
-    AC_ARG_ENABLE([am335xgpio],
-      AS_HELP_STRING([--enable-am335xgpio], [Enable building support for bitbanging on AM335x (as found in Beaglebones)]),
-      [build_am335xgpio=$enableval], [build_am335xgpio=no])
-  ],
-  [
-    build_bcm2835gpio=no
-    build_imx_gpio=no
-    build_am335xgpio=no
-])
-
-AS_CASE(["${host_cpu}"],
-  [arm*], [
-    AC_ARG_ENABLE([ep93xx],
-      AS_HELP_STRING([--enable-ep93xx], [Enable building support for EP93xx based SBCs]),
-      [build_ep93xx=$enableval], [build_ep93xx=no])
-
-    AC_ARG_ENABLE([at91rm9200],
-      AS_HELP_STRING([--enable-at91rm9200], [Enable building support for AT91RM9200 based SBCs]),
-      [build_at91rm9200=$enableval], [build_at91rm9200=no])
-  ],
-  [
-    build_ep93xx=no
-    build_at91rm9200=no
-])
-
 AC_ARG_ENABLE([gw16012],
   AS_HELP_STRING([--enable-gw16012], [Enable building support for the Gateworks GW16012 JTAG Programmer]),
   [build_gw16012=$enableval], [build_gw16012=no])
 
-AC_ARG_ENABLE([sysfsgpio],
-  AS_HELP_STRING([--enable-sysfsgpio], [Enable building support for programming driven via sysfs gpios.]),
-  [build_sysfsgpio=$enableval], [build_sysfsgpio=no])
-
-AC_ARG_ENABLE([xlnx_pcie_xvc],
-  AS_HELP_STRING([--enable-xlnx-pcie-xvc], [Enable building support for Xilinx XVC/PCIe.]),
-  [build_xlnx_pcie_xvc=$enableval], [build_xlnx_pcie_xvc=no])
+can_build_rshim=no
 
 AS_CASE([$host_os],
-  [linux*], [],
+  [linux*], [
+    is_linux=yes
+    can_build_rshim=yes
+  ],
   [
-    AS_IF([test "x$build_sysfsgpio" = "xyes"], [
-      AC_MSG_ERROR([sysfsgpio is only available on linux])
-    ])
-
-    AS_IF([test "x$enable_linuxgpiod" = "xyes"], [
-      AC_MSG_ERROR([linuxgpiod is only available on linux])
-    ])
-
-    AS_IF([test "x$build_xlnx_pcie_xvc" = "xyes"], [
-      AC_MSG_ERROR([xlnx_pcie_xvc is only available on linux])
-    ])
-
-    AS_CASE([$host_os], [freebsd*], [],
+    AS_CASE([$host_os], [freebsd*], [
+      can_build_rshim=yes
+    ],
     [
-      AS_IF([test "x$build_rshim" = "xyes"], [
-        AC_MSG_ERROR([build_rshim is only available on linux or freebsd])
+      AS_IF([test "x$enable_rshim" = "xyes"], [
+        AC_MSG_ERROR([rshim is only available on linux or freebsd])
       ])
     ])
+
+    AS_IF([test "x$enable_dmem" = "xyes"], [
+      AC_MSG_ERROR([dmem is only available on linux])
+    ])
 ])
 
 AC_ARG_ENABLE([internal-jimtcl],
-  AS_HELP_STRING([--disable-internal-jimtcl], [Disable building internal jimtcl]),
-  [use_internal_jimtcl=$enableval], [use_internal_jimtcl=yes])
+  AS_HELP_STRING([--enable-internal-jimtcl], [Enable building internal jimtcl (deprecated)]),
+  [use_internal_jimtcl=$enableval], [use_internal_jimtcl=no])
 
 AC_ARG_ENABLE([jimtcl-maintainer],
   AS_HELP_STRING([--enable-jimtcl-maintainer], [Enable maintainer mode when building internal jimtcl]),
   [use_internal_jimtcl_maintainer=$enableval], [use_internal_jimtcl_maintainer=no])
 
 AC_ARG_ENABLE([internal-libjaylink],
-  AS_HELP_STRING([--disable-internal-libjaylink],
-  [Disable building internal libjaylink]),
-  [use_internal_libjaylink=$enableval], [use_internal_libjaylink=yes])
-
-AC_ARG_ENABLE([remote-bitbang],
-  AS_HELP_STRING([--enable-remote-bitbang], [Enable building support for the Remote Bitbang jtag driver]),
-  [build_remote_bitbang=$enableval], [build_remote_bitbang=no])
+  AS_HELP_STRING([--enable-internal-libjaylink],
+  [Enable building internal libjaylink]),
+  [use_internal_libjaylink=$enableval], [use_internal_libjaylink=no])
 
 AS_CASE(["${host_cpu}"],
   [i?86|x86*], [],
   [
     AS_IF([test "x$parport_use_ppdev" = "xno"], [
-      AC_MSG_WARN([--disable-parport-ppdev is not supported by the host CPU])
+      AC_MSG_ERROR([--disable-parport-ppdev is not supported by the host CPU])
     ])
-    parport_use_ppdev=yes
 ])
 
-AS_CASE([$host],
-  [*-cygwin*], [
+can_build_buspirate=yes
+
+AS_CASE([$host_os],
+  [cygwin*], [
     is_win32=yes
     parport_use_ppdev=no
 
@@ -406,12 +389,12 @@ AS_CASE([$host],
     ], [
       is_cygwin=yes
       # sys/io.h needed under cygwin for parport access
-      AS_IF([test "x$build_parport" = "xyes"], [
+      AS_IF([test "x$enable_parport" != "xno"], [
         AC_CHECK_HEADERS([sys/io.h],[],AC_MSG_ERROR([Please install the cygwin ioperm package]))
       ])
     ])
   ],
-  [*-mingw* | *-msys*], [
+  [mingw* | msys*], [
     is_mingw=yes
     is_win32=yes
     parport_use_ppdev=no
@@ -421,16 +404,16 @@ AS_CASE([$host],
     ])
     parport_use_giveio=yes
 
-    AS_IF([test "x$enable_buspirate" = "xyes"], [
-      AC_MSG_ERROR([buspirate currently not supported by MinGW32 hosts])
+    AS_IF([test "x$ADAPTER_VAR([buspirate])" = "xyes"], [
+      AC_MSG_ERROR([The Bus Pirate adapter is currently not supported by MinGW32 hosts.])
     ])
 
     # In case enable_buspirate=auto, make sure it will not be built.
-    enable_buspirate=no
+    can_build_buspirate=no
 
-    AC_SUBST([HOST_CPPFLAGS], [-D__USE_MINGW_ANSI_STDIO])
+    AC_SUBST([HOST_CPPFLAGS], ["-D__USE_MINGW_ANSI_STDIO -DFD_SETSIZE=128"])
   ],
-  [*darwin*], [
+  [darwin*], [
     is_darwin=yes
 
     AS_IF([test "x$parport_use_giveio" = "xyes"], [
@@ -469,59 +452,8 @@ AS_IF([test "x$is_darwin" = "xyes"], [
     AC_DEFINE([IS_DARWIN], [0], [0 if not building for Darwin.])
 ])
 
-AS_IF([test "x$build_parport" = "xyes"], [
+AS_IF([test "x$ADAPTER_VAR([dummy])" != "xno"], [
   build_bitbang=yes
-  AC_DEFINE([BUILD_PARPORT], [1], [1 if you want parport.])
-], [
-  AC_DEFINE([BUILD_PARPORT], [0], [0 if you don't want parport.])
-])
-
-AS_IF([test "x$build_rshim" = "xyes"], [
-  AC_DEFINE([BUILD_RSHIM], [1], [1 if you want to debug BlueField SoC via rshim.])
-], [
-  AC_DEFINE([BUILD_RSHIM], [0], [0 if you don't want to debug BlueField SoC via rshim.])
-])
-
-AS_IF([test "x$build_dummy" = "xyes"], [
-  build_bitbang=yes
-  AC_DEFINE([BUILD_DUMMY], [1], [1 if you want dummy driver.])
-], [
-  AC_DEFINE([BUILD_DUMMY], [0], [0 if you don't want dummy driver.])
-])
-
-AS_IF([test "x$build_ep93xx" = "xyes"], [
-  build_bitbang=yes
-  AC_DEFINE([BUILD_EP93XX], [1], [1 if you want ep93xx.])
-], [
-  AC_DEFINE([BUILD_EP93XX], [0], [0 if you don't want ep93xx.])
-])
-
-AS_IF([test "x$build_at91rm9200" = "xyes"], [
-  build_bitbang=yes
-  AC_DEFINE([BUILD_AT91RM9200], [1], [1 if you want at91rm9200.])
-], [
-  AC_DEFINE([BUILD_AT91RM9200], [0], [0 if you don't want at91rm9200.])
-])
-
-AS_IF([test "x$build_bcm2835gpio" = "xyes"], [
-  build_bitbang=yes
-  AC_DEFINE([BUILD_BCM2835GPIO], [1], [1 if you want bcm2835gpio.])
-], [
-  AC_DEFINE([BUILD_BCM2835GPIO], [0], [0 if you don't want bcm2835gpio.])
-])
-
-AS_IF([test "x$build_imx_gpio" = "xyes"], [
-  build_bitbang=yes
-  AC_DEFINE([BUILD_IMX_GPIO], [1], [1 if you want imx_gpio.])
-], [
-  AC_DEFINE([BUILD_IMX_GPIO], [0], [0 if you don't want imx_gpio.])
-])
-
-AS_IF([test "x$build_am335xgpio" = "xyes"], [
-  build_bitbang=yes
-  AC_DEFINE([BUILD_AM335XGPIO], [1], [1 if you want am335xgpio.])
-], [
-  AC_DEFINE([BUILD_AM335XGPIO], [0], [0 if you don't want am335xgpio.])
 ])
 
 AS_IF([test "x$parport_use_ppdev" = "xyes"], [
@@ -536,75 +468,32 @@ AS_IF([test "x$parport_use_giveio" = "xyes"], [
   AC_DEFINE([PARPORT_USE_GIVEIO], [0], [0 if you don't want parport to use giveio.])
 ])
 
-AS_IF([test "x$build_jtag_vpi" = "xyes"], [
-  AC_DEFINE([BUILD_JTAG_VPI], [1], [1 if you want JTAG VPI.])
-], [
-  AC_DEFINE([BUILD_JTAG_VPI], [0], [0 if you don't want JTAG VPI.])
-])
-
-AS_IF([test "x$build_vdebug" = "xyes"], [
-  AC_DEFINE([BUILD_VDEBUG], [1], [1 if you want Cadence vdebug interface.])
-], [
-  AC_DEFINE([BUILD_VDEBUG], [0], [0 if you don't want Cadence vdebug interface.])
-])
-
-AS_IF([test "x$build_jtag_dpi" = "xyes"], [
-  AC_DEFINE([BUILD_JTAG_DPI], [1], [1 if you want JTAG DPI.])
-], [
-  AC_DEFINE([BUILD_JTAG_DPI], [0], [0 if you don't want JTAG DPI.])
-])
-
-
-AS_IF([test "x$build_amtjtagaccel" = "xyes"], [
-  AC_DEFINE([BUILD_AMTJTAGACCEL], [1], [1 if you want the Amontec JTAG-Accelerator driver.])
-], [
-  AC_DEFINE([BUILD_AMTJTAGACCEL], [0], [0 if you don't want the Amontec JTAG-Accelerator driver.])
-])
-
 AS_IF([test "x$build_gw16012" = "xyes"], [
   AC_DEFINE([BUILD_GW16012], [1], [1 if you want the Gateworks GW16012 driver.])
 ], [
   AC_DEFINE([BUILD_GW16012], [0], [0 if you don't want the Gateworks GW16012 driver.])
 ])
 
-AS_IF([test "x$enable_buspirate" != "xno"], [
-  AC_DEFINE([BUILD_BUSPIRATE], [1], [1 if you want the Buspirate JTAG driver.])
-], [
-  AC_DEFINE([BUILD_BUSPIRATE], [0], [0 if you don't want the Buspirate JTAG driver.])
-])
-
 AS_IF([test "x$use_internal_jimtcl" = "xyes"], [
-  AS_IF([test -f "$srcdir/jimtcl/configure.ac"], [
+  AS_IF([test -f "$srcdir/jimtcl/configure"], [
     AS_IF([test "x$use_internal_jimtcl_maintainer" = "xyes"], [
-      jimtcl_config_options="--disable-install-jim --with-ext=json --maintainer"
+      jimtcl_config_options="--disable-install-jim --with-ext=json --minimal --disable-ssl --maintainer"
     ], [
-      jimtcl_config_options="--disable-install-jim --with-ext=json"
+      jimtcl_config_options="--disable-install-jim --with-ext=json --minimal --disable-ssl"
     ])
     AX_CONFIG_SUBDIR_OPTION([jimtcl], [$jimtcl_config_options])
   ], [
     AC_MSG_ERROR([jimtcl not found, run git submodule init and git submodule update.])
   ])
-])
-
-AS_IF([test "x$build_remote_bitbang" = "xyes"], [
-  build_bitbang=yes
-  AC_DEFINE([BUILD_REMOTE_BITBANG], [1], [1 if you want the Remote Bitbang JTAG driver.])
 ], [
-  AC_DEFINE([BUILD_REMOTE_BITBANG], [0], [0 if you don't want the Remote Bitbang JTAG driver.])
-])
-
-AS_IF([test "x$build_sysfsgpio" = "xyes"], [
-  build_bitbang=yes
-  AC_DEFINE([BUILD_SYSFSGPIO], [1], [1 if you want the SysfsGPIO driver.])
-], [
-  AC_DEFINE([BUILD_SYSFSGPIO], [0], [0 if you don't want SysfsGPIO driver.])
-])
-
-AS_IF([test "x$build_xlnx_pcie_xvc" = "xyes"], [
-  build_xlnx_pcie_xvc=yes
-  AC_DEFINE([BUILD_XLNX_PCIE_XVC], [1], [1 if you want the Xilinx XVC/PCIe driver.])
-], [
-  AC_DEFINE([BUILD_XLNX_PCIE_XVC], [0], [0 if you don't want Xilinx XVC/PCIe driver.])
+  PKG_CHECK_MODULES([JIMTCL], [jimtcl >= 0.79], [
+      have_jimtcl_pkg_config=yes
+    ], [
+      have_jimtcl_pkg_config=no
+      AC_CHECK_HEADER([jim.h], [], [
+        AC_MSG_ERROR([jimtcl is required but not found via pkg-config and system includes])
+      ])
+  ])
 ])
 
 PKG_CHECK_MODULES([LIBUSB1], [libusb-1.0], [
@@ -631,7 +520,6 @@ AS_IF([test "x$enable_capstone" != xno], [
 	PKG_CHECK_MODULES([CAPSTONE], [capstone], [
 		AC_DEFINE([HAVE_CAPSTONE], [1], [1 if you have Capstone disassembly framework.])
 	], [
-		AC_DEFINE([HAVE_CAPSTONE], [0], [0 if you don't have Capstone disassembly framework.])
 		if test "x$enable_capstone" != xauto; then
 			AC_MSG_ERROR([--with-capstone was given, but test for Capstone failed])
 		fi
@@ -656,43 +544,111 @@ PKG_CHECK_MODULES([LIBFTDI], [libftdi1], [
 	PKG_CHECK_MODULES([LIBFTDI], [libftdi], [use_libftdi=yes], [use_libftdi=no])
 ])
 
-PKG_CHECK_MODULES([LIBGPIOD], [libgpiod], [use_libgpiod=yes], [use_libgpiod=no])
+PKG_CHECK_MODULES([LIBGPIOD], [libgpiod >= 2.0] , [
+	use_libgpiod=yes
+], [
+	PKG_CHECK_MODULES([LIBGPIOD], [libgpiod], [
+		use_libgpiod=yes
+		AC_DEFINE([HAVE_LIBGPIOD_V1], [1], [define if libgpiod is version v1.x])
+
+		PKG_CHECK_EXISTS([libgpiod >= 1.5],
+			[AC_DEFINE([HAVE_LIBGPIOD1_FLAGS_BIAS], [1], [define if libgpiod v1 has line request flags bias])])
+	], [
+		use_libgpiod=no
+	])
+])
 
 PKG_CHECK_MODULES([LIBJAYLINK], [libjaylink >= 0.2],
 	[use_libjaylink=yes], [use_libjaylink=no])
 
+# Arg $1: An array of adapter triplets, used to derive option and variable names for each adapter.
+# Arg $2: Whether the adapters can be enabled, for example, because
+#         their prerequisites are installed in the system.
+# Arg $3: What prerequisites are missing, to be shown in an error message
+#         if an adapter was requested but cannot be enabled.
 m4_define([PROCESS_ADAPTERS], [
-  m4_foreach([adapter], [$1], [
+  m4_foreach([adapter_driver], [$1], [
 	AS_IF([test $2], [
-		AS_IF([test "x$ADAPTER_VAR([adapter])" != "xno"], [
-			AC_DEFINE([BUILD_]ADAPTER_SYM([adapter]), [1], [1 if you want the ]ADAPTER_DESC([adapter]).)
+		AS_IF([test "x$ADAPTER_VAR([adapter_driver])" != "xno"], [
+			AC_DEFINE([BUILD_]ADAPTER_SYM([adapter_driver]), [1],
+			          [1 if you want the ]ADAPTER_DESC([adapter_driver]).)
 		], [
-			AC_DEFINE([BUILD_]ADAPTER_SYM([adapter]), [0], [0 if you do not want the ]ADAPTER_DESC([adapter]).)
+			AC_DEFINE([BUILD_]ADAPTER_SYM([adapter_driver]), [0],
+			          [0 if you do not want the ]ADAPTER_DESC([adapter_driver]).)
 		])
 	], [
-		AS_IF([test "x$ADAPTER_VAR([adapter])" = "xyes"], [
-			AC_MSG_ERROR([$3 is required for the ADAPTER_DESC([adapter])])
+		AS_IF([test "x$ADAPTER_VAR([adapter_driver])" = "xyes"], [
+			AC_MSG_ERROR([$3 is required for [adapter_driver] "ADAPTER_DESC([adapter_driver])".])
 		])
-		ADAPTER_VAR([adapter])=no
-		AC_DEFINE([BUILD_]ADAPTER_SYM([adapter]), [0], [0 if you do not want the ]ADAPTER_DESC([adapter]).)
+		ADAPTER_VAR([adapter_driver])=no
+		AC_DEFINE([BUILD_]ADAPTER_SYM([adapter_driver]), [0],
+                  [0 if you do not want the ]ADAPTER_DESC([adapter_driver]).)
 	])
-	AM_CONDITIONAL(ADAPTER_SYM([adapter]), [test "x$ADAPTER_VAR([adapter])" != "xno"])
+	AM_CONDITIONAL(ADAPTER_SYM([adapter_driver]), [test "x$ADAPTER_VAR([adapter_driver])" != "xno"])
   ])
 ])
 
 PROCESS_ADAPTERS([USB1_ADAPTERS], ["x$use_libusb1" = "xyes"], [libusb-1.x])
-PROCESS_ADAPTERS([DEPRECATED_USB1_ADAPTERS], ["x$use_libusb1" = "xyes"], [libusb-1.x])
 PROCESS_ADAPTERS([HIDAPI_ADAPTERS], ["x$use_hidapi" = "xyes"], [hidapi])
 PROCESS_ADAPTERS([HIDAPI_USB1_ADAPTERS], ["x$use_hidapi" = "xyes" -a "x$use_libusb1" = "xyes"], [hidapi and libusb-1.x])
 PROCESS_ADAPTERS([LIBFTDI_ADAPTERS], ["x$use_libftdi" = "xyes"], [libftdi])
 PROCESS_ADAPTERS([LIBFTDI_USB1_ADAPTERS], ["x$use_libftdi" = "xyes" -a "x$use_libusb1" = "xyes"], [libftdi and libusb-1.x])
-PROCESS_ADAPTERS([LIBGPIOD_ADAPTERS], ["x$use_libgpiod" = "xyes"], [libgpiod])
+PROCESS_ADAPTERS([LIBGPIOD_ADAPTERS], ["x$use_libgpiod" = "xyes"], [Linux libgpiod])
+PROCESS_ADAPTERS([DMEM_ADAPTER], ["x$is_linux" = "xyes" -a "x$ac_cv_header_sys_mman_h" = "xyes"], [Linux /dev/mem])
+PROCESS_ADAPTERS([SYSFSGPIO_ADAPTER], ["x$is_linux" = "xyes"], [Linux sysfs])
+PROCESS_ADAPTERS([REMOTE_BITBANG_ADAPTER], [true], [unused])
+PROCESS_ADAPTERS([CMSIS_DAP_TCP_ADAPTER], [true], [unused])
 PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_internal_libjaylink" = "xyes" -o "x$use_libjaylink" = "xyes"], [libjaylink-0.2])
+PROCESS_ADAPTERS([XVC_ADAPTERS],
+        ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_pci_h" = "xyes" -a "x$ac_cv_header_sys_mman_h" = "xyes"],
+        [Linux build with headers linux/pci.h and sys/mman.h])
+PROCESS_ADAPTERS([SERIAL_PORT_ADAPTERS], ["x$can_build_buspirate" = "xyes"],
+                                         [internal error: validation should happen beforehand])
+PROCESS_ADAPTERS([PARALLEL_PORT_ADAPTER], [true], [unused])
+PROCESS_ADAPTERS([LINUXSPIDEV_ADAPTER], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_spi_spidev_h" = "xyes"],
+                                        [Linux spidev])
+PROCESS_ADAPTERS([VDEBUG_ADAPTER], [true], [unused])
+PROCESS_ADAPTERS([JTAG_DPI_ADAPTER], [true], [unused])
+PROCESS_ADAPTERS([JTAG_VPI_ADAPTER], [true], [unused])
+PROCESS_ADAPTERS([RSHIM_ADAPTER], ["x$can_build_rshim" = "xyes"],
+                                  [internal error: validation should happen beforehand])
+PROCESS_ADAPTERS([AMTJTAGACCEL_ADAPTER], [true], [unused])
+PROCESS_ADAPTERS([HOST_ARM_BITBANG_ADAPTERS], ["x$ac_cv_header_sys_mman_h" = "xyes"], [header sys/mman.h])
+PROCESS_ADAPTERS([HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS], ["x$ac_cv_header_sys_mman_h" = "xyes"], [header sys/mman.h])
+PROCESS_ADAPTERS([DUMMY_ADAPTER], [true], [unused])
 
 AS_IF([test "x$enable_linuxgpiod" != "xno"], [
   build_bitbang=yes
 ])
 
+AS_IF([test "x$enable_sysfsgpio" != "xno"], [
+  build_bitbang=yes
+])
+
+AS_IF([test "x$enable_remote_bitbang" != "xno"], [
+  build_bitbang=yes
+])
+
+AS_IF([test "x$enable_bcm2835gpio" != "xno"], [
+  build_bitbang=yes
+])
+
+AS_IF([test "x$enable_imx_gpio" != "xno"], [
+  build_bitbang=yes
+])
+
+AS_IF([test "x$enable_am335xgpio" != "xno"], [
+  build_bitbang=yes
+])
+
+AS_IF([test "x$enable_ep93xx" != "xno"], [
+  build_bitbang=yes
+])
+
+AS_IF([test "x$enable_at91rm9200" != "xno"], [
+  build_bitbang=yes
+])
+
 AS_IF([test "x$enable_stlink" != "xno" -o "x$enable_ti_icdi" != "xno" -o "x$enable_nulink" != "xno"], [
 	AC_DEFINE([BUILD_HLADAPTER], [1], [1 if you want the High Level JTAG driver.])
 	AM_CONDITIONAL([HLADAPTER], [true])
@@ -703,6 +659,8 @@ AS_IF([test "x$enable_stlink" != "xno" -o "x$enable_ti_icdi" != "xno" -o "x$enab
 AM_CONDITIONAL([HLADAPTER_STLINK], [test "x$enable_stlink" != "xno"])
 AM_CONDITIONAL([HLADAPTER_ICDI], [test "x$enable_ti_icdi" != "xno"])
 AM_CONDITIONAL([HLADAPTER_NULINK], [test "x$enable_nulink" != "xno"])
+AM_CONDITIONAL([CMSIS_DAP_CORE],
+   [test "x$enable_cmsis_dap" != "xno" -o "x$enable_cmsis_dap_v2" != "xno" -o "x$enable_cmsis_dap_tcp" != "xno"])
 
 AS_IF([test "x$enable_jlink" != "xno"], [
   AS_IF([test "x$use_internal_libjaylink" = "xyes"], [
@@ -710,7 +668,7 @@ AS_IF([test "x$enable_jlink" != "xno"], [
       AX_CONFIG_SUBDIR_OPTION([src/jtag/drivers/libjaylink],
 		[--enable-subproject-build])
     ], [
-      AC_MSG_ERROR([Internal libjaylink not found, run either 'git submodule init' and 'git submodule update' or disable internal libjaylink with --disable-internal-libjaylink.])
+      AC_MSG_ERROR([Internal libjaylink not found, run 'git submodule init' and 'git submodule update'.])
     ])
   ])
 ])
@@ -726,25 +684,10 @@ AS_IF([test "x$enable_esp_usb_jtag" != "xno"], [
 ])
 
 AM_CONDITIONAL([RELEASE], [test "x$build_release" = "xyes"])
-AM_CONDITIONAL([PARPORT], [test "x$build_parport" = "xyes"])
-AM_CONDITIONAL([DUMMY], [test "x$build_dummy" = "xyes"])
 AM_CONDITIONAL([GIVEIO], [test "x$parport_use_giveio" = "xyes"])
-AM_CONDITIONAL([EP93XX], [test "x$build_ep93xx" = "xyes"])
-AM_CONDITIONAL([AT91RM9200], [test "x$build_at91rm9200" = "xyes"])
-AM_CONDITIONAL([BCM2835GPIO], [test "x$build_bcm2835gpio" = "xyes"])
-AM_CONDITIONAL([IMX_GPIO], [test "x$build_imx_gpio" = "xyes"])
-AM_CONDITIONAL([AM335XGPIO], [test "x$build_am335xgpio" = "xyes"])
 AM_CONDITIONAL([BITBANG], [test "x$build_bitbang" = "xyes"])
-AM_CONDITIONAL([JTAG_VPI], [test "x$build_jtag_vpi" = "xyes"])
-AM_CONDITIONAL([VDEBUG], [test "x$build_vdebug" = "xyes"])
-AM_CONDITIONAL([JTAG_DPI], [test "x$build_jtag_dpi" = "xyes"])
 AM_CONDITIONAL([USB_BLASTER_DRIVER], [test "x$enable_usb_blaster" != "xno" -o "x$enable_usb_blaster_2" != "xno"])
-AM_CONDITIONAL([AMTJTAGACCEL], [test "x$build_amtjtagaccel" = "xyes"])
 AM_CONDITIONAL([GW16012], [test "x$build_gw16012" = "xyes"])
-AM_CONDITIONAL([REMOTE_BITBANG], [test "x$build_remote_bitbang" = "xyes"])
-AM_CONDITIONAL([BUSPIRATE], [test "x$enable_buspirate" != "xno"])
-AM_CONDITIONAL([SYSFSGPIO], [test "x$build_sysfsgpio" = "xyes"])
-AM_CONDITIONAL([XLNX_PCIE_XVC], [test "x$build_xlnx_pcie_xvc" = "xyes"])
 AM_CONDITIONAL([USE_LIBUSB1], [test "x$use_libusb1" = "xyes"])
 AM_CONDITIONAL([IS_CYGWIN], [test "x$is_cygwin" = "xyes"])
 AM_CONDITIONAL([IS_MINGW], [test "x$is_mingw" = "xyes"])
@@ -755,12 +698,15 @@ AM_CONDITIONAL([USE_LIBFTDI], [test "x$use_libftdi" = "xyes"])
 AM_CONDITIONAL([USE_LIBGPIOD], [test "x$use_libgpiod" = "xyes"])
 AM_CONDITIONAL([USE_HIDAPI], [test "x$use_hidapi" = "xyes"])
 AM_CONDITIONAL([USE_LIBJAYLINK], [test "x$use_libjaylink" = "xyes"])
-AM_CONDITIONAL([RSHIM], [test "x$build_rshim" = "xyes"])
 AM_CONDITIONAL([HAVE_CAPSTONE], [test "x$enable_capstone" != "xno"])
 
 AM_CONDITIONAL([INTERNAL_JIMTCL], [test "x$use_internal_jimtcl" = "xyes"])
+AM_CONDITIONAL([HAVE_JIMTCL_PKG_CONFIG], [test "x$have_jimtcl_pkg_config" = "xyes"])
 AM_CONDITIONAL([INTERNAL_LIBJAYLINK], [test "x$use_internal_libjaylink" = "xyes"])
 
+
+AM_CONDITIONAL([USE_GCOV], [test "x$enable_gcov" = "xyes"])
+
 # Look for environ alternatives.  Possibility #1: is environ in unistd.h or stdlib.h?
 AC_MSG_CHECKING([for environ in unistd.h and stdlib.h])
 AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[
@@ -798,6 +744,7 @@ AC_DEFINE([_GNU_SOURCE],[1],[Use GNU C library extensions (e.g. stdndup).])
 GCC_WARNINGS="-Wall -Wstrict-prototypes -Wformat-security -Wshadow"
 AS_IF([test "x${gcc_wextra}" = "xyes"], [
   GCC_WARNINGS="${GCC_WARNINGS} -Wextra -Wno-unused-parameter"
+  GCC_WARNINGS="${GCC_WARNINGS} -Wno-gnu-folding-constant"
   GCC_WARNINGS="${GCC_WARNINGS} -Wbad-function-cast"
   GCC_WARNINGS="${GCC_WARNINGS} -Wcast-align"
   GCC_WARNINGS="${GCC_WARNINGS} -Wredundant-decls"
@@ -816,23 +763,67 @@ AS_IF([test "x$gcc_warnings" = "xyes"], [
 AC_SUBST(EXTRA_DIST_NEWS, ["$(echo $srcdir/NEWS-*)"])
 
 AC_CONFIG_FILES([
-  Makefile
+  Makefile \
+  testing/Makefile \
+  testing/tcl_commands/Makefile
 ])
 AC_OUTPUT
 
+AS_IF([test "x$enable_jlink" != "xno"], [
+  AS_IF([test "x$use_internal_libjaylink" = "xyes"], [
+    AC_MSG_WARN([Using the internal libjaylink is deprecated and will not be possible in the future.])
+  ]])
+)
+
+AS_IF([test "x$use_internal_jimtcl" = "xyes"], [
+  AC_MSG_WARN([Using the internal jimtcl is deprecated and will not be possible in the future.])
+])
+
+AS_IF([test "x$enable_amtjtagaccel" != "xno"], [
+  echo
+  echo
+  AC_MSG_WARN([Amontec JTAG-Accelerator adapter is deprecated and support will be removed in the next release!])
+])
+AS_IF([test "x$build_gw16012" = "xyes"], [
+  echo
+  echo
+  AC_MSG_WARN([Gateworks GW16012 JTAG adapter is deprecated and support will be removed in the next release!])
+])
+
+AS_IF([test "x$parport_use_giveio" = "xyes" || test [ "x$enable_parport" != "xno" -a "x$parport_use_ppdev" = "xno"]], [
+  echo
+  echo
+  AC_MSG_WARN([Parallel port access with direct I/O is deprecated and support will be removed in the next release!])
+])
+
 echo
 echo
 echo OpenOCD configuration summary
-echo --------------------------------------------------
-m4_foreach([adapter], [USB1_ADAPTERS,
-	DEPRECATED_USB1_ADAPTERS,
+echo ---------------------------------------------------
+m4_foreach([adapter_driver], [USB1_ADAPTERS,
 	HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS,
 	LIBFTDI_USB1_ADAPTERS,
 	LIBGPIOD_ADAPTERS,
-	LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS, SERIAL_PORT_ADAPTERS,
-	OPTIONAL_LIBRARIES],
-	[s=m4_format(["%-40s"], ADAPTER_DESC([adapter]))
-	AS_CASE([$ADAPTER_VAR([adapter])],
+	DMEM_ADAPTER,
+	SYSFSGPIO_ADAPTER,
+	REMOTE_BITBANG_ADAPTER,
+	LIBJAYLINK_ADAPTERS, XVC_ADAPTERS,
+	SERIAL_PORT_ADAPTERS,
+	PARALLEL_PORT_ADAPTER,
+	LINUXSPIDEV_ADAPTER,
+	VDEBUG_ADAPTER,
+	JTAG_DPI_ADAPTER,
+	JTAG_VPI_ADAPTER,
+	RSHIM_ADAPTER,
+	AMTJTAGACCEL_ADAPTER,
+	HOST_ARM_BITBANG_ADAPTERS,
+	HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS,
+	CMSIS_DAP_TCP_ADAPTER,
+	DUMMY_ADAPTER,
+	OPTIONAL_LIBRARIES,
+	COVERAGE],
+	[s=m4_format(["%-49s"], ADAPTER_DESC([adapter_driver]))
+	AS_CASE([$ADAPTER_VAR([adapter_driver])],
 		[auto], [
 			echo "$s"yes '(auto)'
 		],
@@ -841,6 +832,11 @@ m4_foreach([adapter], [USB1_ADAPTERS,
 		],
 		[no], [
 			echo "$s"no
+		],
+		[
+			AC_MSG_ERROR(m4_normalize([
+				Error in [adapter_driver] "ADAPTER_ARG([adapter_driver])": Variable "ADAPTER_VAR([adapter_driver])"
+				has invalid value "$ADAPTER_VAR([adapter_driver])".]))
 	])
 ])
 echo

contrib/60-openocd.rules

@@ -29,6 +29,27 @@ ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6014", MODE="660", GROUP="plugdev",
 # Original FT231XQ VID:PID
 ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
+# Original FT2233HP VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6040", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT4233HP VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6041", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT2232HP VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6042", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT4232HP VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6043", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT233HP VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6044", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT232HP VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6045", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+# Original FT4232HA VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6048", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
 # DISTORTEC JTAG-lock-pick Tiny 2
 ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8220", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
@@ -99,6 +120,8 @@ ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374e", MODE="660", GROUP="plugdev",
 ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374f", MODE="660", GROUP="plugdev", TAG+="uaccess"
 ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3753", MODE="660", GROUP="plugdev", TAG+="uaccess"
 ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3754", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3755", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3757", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
 # Cypress SuperSpeed Explorer Kit
 ATTRS{idVendor}=="04b4", ATTRS{idProduct}=="0007", MODE="660", GROUP="plugdev", TAG+="uaccess"
@@ -167,6 +190,10 @@ ATTRS{idVendor}=="138e", ATTRS{idProduct}=="9000", MODE="660", GROUP="plugdev",
 # Debug Board for Neo1973
 ATTRS{idVendor}=="1457", ATTRS{idProduct}=="5118", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
+# Microchip RISC-V Debug
+ATTRS{idVendor}=="1514", ATTRS{idProduct}=="2008", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1514", ATTRS{idProduct}=="200a", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
 # OSBDM
 ATTRS{idVendor}=="15a2", ATTRS{idProduct}=="0042", MODE="660", GROUP="plugdev", TAG+="uaccess"
 ATTRS{idVendor}=="15a2", ATTRS{idProduct}=="0058", MODE="660", GROUP="plugdev", TAG+="uaccess"
@@ -193,6 +220,11 @@ ATTRS{idVendor}=="16c0", ATTRS{idProduct}=="06ad", MODE="660", GROUP="plugdev",
 # USBprog with OpenOCD firmware
 ATTRS{idVendor}=="1781", ATTRS{idProduct}=="0c63", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
+# WCH CH347T chip in mode 3
+ATTRS{idVendor}=="1a86", ATTRS{idProduct}=="55dd", MODE="660", GROUP="plugdev", TAG+="uaccess"
+# WCH CH347F chip
+ATTRS{idVendor}=="1a86", ATTRS{idProduct}=="55de", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
 # TI/Luminary Stellaris In-Circuit Debug Interface (ICDI) Board
 ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="00fd", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
@@ -222,6 +254,11 @@ ATTRS{idVendor}=="2aec", ATTRS{idProduct}=="1106", MODE="660", GROUP="plugdev",
 ATTRS{idVendor}=="303a", ATTRS{idProduct}=="1001", MODE="660", GROUP="plugdev", TAG+="uaccess"
 ATTRS{idVendor}=="303a", ATTRS{idProduct}=="1002", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
+# ANGIE USB-JTAG Adapter
+ATTRS{idVendor}=="584e", ATTRS{idProduct}=="414f", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="584e", ATTRS{idProduct}=="424e", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="584e", ATTRS{idProduct}=="4a55", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
 # Marvell Sheevaplug
 ATTRS{idVendor}=="9e88", ATTRS{idProduct}=="9e8f", MODE="660", GROUP="plugdev", TAG+="uaccess"
 

contrib/buildroot/openocd_be_defconfig

@@ -12,7 +12,6 @@ BR2_PACKAGE_OPENOCD_UBLASTER2=y
 BR2_PACKAGE_OPENOCD_JLINK=y
 BR2_PACKAGE_OPENOCD_OSDBM=y
 BR2_PACKAGE_OPENOCD_OPENDOUS=y
-BR2_PACKAGE_OPENOCD_AICE=y
 BR2_PACKAGE_OPENOCD_VSLLINK=y
 BR2_PACKAGE_OPENOCD_USBPROG=y
 BR2_PACKAGE_OPENOCD_RLINK=y

contrib/coresight-trace.txt

@@ -1,68 +0,0 @@
-+OpenOCD and CoreSight Tracing
-+
-Many recent ARM chips  (Using e..g. Cortex-M3 and
-Cortex-M4 cores) support CoreSight debug/trace.
-This note sketches an approach currently planned for those cores
-with OpenOCD.
-
- This tracing data can help debug and tune ARM software, but not
-all cores support tracing.  Some support more extensive tracing
-other cores with trace support +should be able to use the same
-approach and maybe some of the same analysis code.
-
-+the Cortex-M3 is assumed here to be the
-+core in use, for simplicity and to reflect current OpenOCD users.
-
-
-This note summarizes a software model to generate, collect, and
-analyze such trace data .  That is not fully implemented as of early
-January 2011, +and thus is not *yet* usable.
-+
-+
-+Some microcontroller cores support a low pin-count Single-wire trace,
-with a mode where +trace data is emitted (usually to a UART.  To use
-this mode, +SWD must be in use.
-+At this writing, OpenOCD SWD support is not yet complete either.
-
-(There are also multi-wire trace ports requiring more complex debug
-adapters than OpenOCD currently supports, and offering richer data.
-+
-+
-+* ENABLING involves activating  SWD and (single wire) trace.
-+
-+current expectations are that OpenOCD itself will handle enabling;
-activating single wire trace involves a debug adapter interaction, and
-collecting that trace data requires particular (re)wiring.
-+
-+* CONFIGURATION involves setting up ITM  and/or ETM modules to emit the
-+desired data from the Cortex core.  (This might include dumping
-+event counters printf-style messages; code profiling; and more.  Not all
-+cores offer the same trace capabilities.
-+
-+current expectations are that Tcl scripts will be used to configure these
-+modules for the desired tracing, by direct writes to registers.  In some
-+cases (as with RTOS event tracking and similar messaging, this might
-+be  augmented or replaced by user code running on the ARM core.
-+
-+COLLECTION involves reading that trace data, probably through UART, and
-+saving it in a useful format to analyse  For now, deferred analysis modes
-are assumed, not than real-time or interactive ones.
-+
-+
-+current expectations are to to dump data in text using contrib/itmdump.c
-+or derived tools, and to post-process it into reports.  Such reports might
-+include program messaging (such as application data streams via ITM, maybe
-+using printf type messaging; code coverage analysis or so forth.  Recent
-+versions of CMSIS software reserve some ITM codespace for RTOS  event
-tracing and include ITM messaging support.
-Clearly some of that data would be valuable for interactive debugging.
-+
-+Should someone get ambitious, GUI reports should be possible.  GNU tools
-+for simpler reports like gprof may be simpler to support at first.
-+In any case, OpenOCD is not currently GUI-oriented.  Accordingly, we now
-+expect any such graphics to come from postprocessing.
-
- measurements for RTOS event timings should also be easy to collect.
-+Examples include context and message switch times, as well as times
-for application interactions.
-+

contrib/cross-build.sh

@@ -41,12 +41,16 @@ WORK_DIR=$PWD
 : ${HIDAPI_SRC:=/path/to/hidapi}
 : ${LIBFTDI_SRC:=/path/to/libftdi}
 : ${CAPSTONE_SRC:=/path/to/capstone}
+: ${LIBJAYLINK_SRC:=/path/to/libjaylink}
+: ${JIMTCL_SRC:=/path/to/jimtcl}
 
 OPENOCD_SRC=`readlink -m $OPENOCD_SRC`
 LIBUSB1_SRC=`readlink -m $LIBUSB1_SRC`
 HIDAPI_SRC=`readlink -m $HIDAPI_SRC`
 LIBFTDI_SRC=`readlink -m $LIBFTDI_SRC`
 CAPSTONE_SRC=`readlink -m $CAPSTONE_SRC`
+LIBJAYLINK_SRC=`readlink -m $LIBJAYLINK_SRC`
+JIMTCL_SRC=`readlink -m $JIMTCL_SRC`
 
 HOST_TRIPLET=$1
 BUILD_DIR=$WORK_DIR/$HOST_TRIPLET-build
@@ -54,6 +58,8 @@ LIBUSB1_BUILD_DIR=$BUILD_DIR/libusb1
 HIDAPI_BUILD_DIR=$BUILD_DIR/hidapi
 LIBFTDI_BUILD_DIR=$BUILD_DIR/libftdi
 CAPSTONE_BUILD_DIR=$BUILD_DIR/capstone
+LIBJAYLINK_BUILD_DIR=$BUILD_DIR/libjaylink
+JIMTCL_BUILD_DIR=$BUILD_DIR/jimtcl
 OPENOCD_BUILD_DIR=$BUILD_DIR/openocd
 
 ## Root of host file tree
@@ -158,6 +164,28 @@ libdir=${exec_prefix}/lib \
 includedir=${prefix}/include/capstone\n\n;' $CAPSTONE_PC_FILE
 fi
 
+# libjaylink build & install into sysroot
+if [ -d $LIBJAYLINK_SRC ] ; then
+  mkdir -p $LIBJAYLINK_BUILD_DIR
+  cd $LIBJAYLINK_BUILD_DIR
+  $LIBJAYLINK_SRC/configure --build=`$LIBJAYLINK_SRC/config.guess` --host=$HOST_TRIPLET \
+    --with-sysroot=$SYSROOT --prefix=$PREFIX \
+    $LIBJAYLINK_CONFIG
+  make -j $MAKE_JOBS
+  make install DESTDIR=$SYSROOT
+fi
+
+# jimtcl build & install into sysroot
+if [ -d $JIMTCL_SRC ] ; then
+  mkdir -p $JIMTCL_BUILD_DIR
+  cd $JIMTCL_BUILD_DIR
+  $JIMTCL_SRC/configure --host=$HOST_TRIPLET --prefix=$PREFIX \
+    $JIMTCL_CONFIG
+  make -j $MAKE_JOBS
+  # Running "make" does not create this file for static builds on Windows but "make install" still expects it
+  touch $JIMTCL_BUILD_DIR/build-jim-ext
+  make install DESTDIR=$SYSROOT
+fi
 
 # OpenOCD build & install into sysroot
 mkdir -p $OPENOCD_BUILD_DIR

contrib/firmware/angie/c/Makefile

@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#****************************************************************************
+#   File : Makefile                                                         *
+#   Contents : Code for NanoXplore USB-JTAG ANGIE adapter hardware.         *
+#   Based on openULINK project by: Martin Schmoelzer.                       *
+#   Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.              *
+#   <aboudjelida@nanoxplore.com>                                            *
+#	<ahmederrachedbjld@gmail.com>											*
+# ***************************************************************************/
+
+# Define the name of tools.
+PREFIX =
+
+# Small Device C Compiler: http://sdcc.sourceforge.net/
+CC = $(PREFIX)sdcc
+
+# 8051 assembler, part of the SDCC software package.
+AS = $(PREFIX)sdas8051
+
+# SDCC produces quite messy Intel HEX files. This tool is be used to re-format
+# those files. It is not required for the firmware download functionality in
+# the OpenOCD driver, but the resulting file is smaller.
+PACKIHX = $(PREFIX)packihx
+
+# GNU binutils size. Used to print the size of the IHX file generated by SDCC.
+SIZE = size
+
+# Source and header directories.
+SRC_DIR     = src
+INCLUDE_DIR = include
+
+CODE_SIZE = 0x3C00
+XRAM_LOC  = 0x3C00
+XRAM_SIZE = 0x0400
+
+CFLAGS  = --std-sdcc99 --opt-code-size --model-small
+LDFLAGS = --code-loc 0x0000 --code-size $(CODE_SIZE) --xram-loc $(XRAM_LOC) \
+          --xram-size $(XRAM_SIZE) --iram-size 256 --model-small
+
+# list of base object files
+OBJECTS = main.rel usb.rel delay.rel USBJmpTb.rel gpif.rel i2c.rel serial.rel
+HEADERS = $(INCLUDE_DIR)/usb.h          \
+          $(INCLUDE_DIR)/delay.h        \
+          $(INCLUDE_DIR)/reg_ezusb.h    \
+          $(INCLUDE_DIR)/io.h           \
+          $(INCLUDE_DIR)/serial.h       \
+          $(INCLUDE_DIR)/fx2macros.h    \
+          $(INCLUDE_DIR)/msgtypes.h     \
+          $(INCLUDE_DIR)/i2c.h
+
+# Disable all built-in rules.
+.SUFFIXES:
+
+# Targets which are executed even when identically named file is present.
+.PHONY: all, clean
+
+all: angie_firmware.ihx
+	$(SIZE) angie_firmware.ihx
+
+angie_firmware.ihx: $(OBJECTS)
+	$(CC) -mmcs51 $(LDFLAGS) -o $@ $^
+
+# Rebuild every C module (there are only 8 of them) if any header changes.
+%.rel: $(SRC_DIR)/%.c $(HEADERS)
+	$(CC) -c $(CFLAGS) -mmcs51 -I$(INCLUDE_DIR) -o $@ $<
+
+%.rel: $(SRC_DIR)/%.a51
+	$(AS) -lsgo $@ $<
+
+clean:
+	rm -f *.asm *.lst *.rel *.rst *.sym *.ihx *.lk *.map *.mem
+
+bin: angie_firmware.ihx
+	makebin -p angie_firmware.ihx angie_firmware.bin
+
+hex: angie_firmware.ihx
+	$(PACKIHX) angie_firmware.ihx > fx2.hex

contrib/firmware/angie/c/README

@@ -0,0 +1,37 @@
+#SPDX-License-Identifier: GPL-2.0-or-later
+
+This is the ANGIE firmware for ANGIE USB-JTAG adapter.
+
+The main components of ANGIE adapter are:
+- Cypress EZ-USB FX2 microcontroller
+- Spartan-6 FPGA
+- SRAM memory chip
+- Pin headers for various JTAG pin assignments
+
+To compile the firmware, the SDCC compiler package is required. Most Linux
+distributions include SDCC in their official package repositories. The SDCC
+source code can be found at http://sdcc.sourceforge.net/
+
+Simply type "make bin" in the ANGIE directory to compile the firmware.
+"make clean" will remove all generated files except the BIN file
+required for downloading the firmware to ANGIE.
+
+Note that the EZ-USB FX2 microcontroller does not have on-chip flash,
+ANGIE include on-board EEPROM memory to store the firmware program of
+the FX2, but we are not going to use this method.
+
+Instead, upon initial connection of the ANGIE adapter to the host PC
+via USB, the EZ-USB FX2 core has enough intelligence to act as a
+stand-alone USB device, responding to USB control requests and allowing
+firmware download via a special VENDOR-type control request. Then, the
+EZ-USB microcontroller simulates a disconnect and re-connect to the USB bus.
+It may take up to two seconds for the host to recognize the newly connected
+device before OpenOCD can proceed to execute JTAG commands. This delay is
+only visible when OpenOCD first uses a blank (unconfigured) ANGIE device.
+
+Once the firmware downloaded, the FX2 microcontroller activate its GPIF mode,
+download the Spartan-6 FPGA's bitstream, program the FPGA rapidly, and switch
+back to default io mode.
+
+Once the user disconnects the ANGIE adapter, all its memory contents are lost
+and the firmware & bitstream download process has to be executed again.

contrib/firmware/angie/c/include/delay.h

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/****************************************************************
+    File : delay.h                                              *
+    Contents : Delays handling header file for NanoXplore       *
+    USB-JTAG ANGIE adapter hardware.                            *
+    Based on openULINK project code by: Martin Schmoelzer.      *
+    Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.  *
+    <aboudjelida@nanoxplore.com>                                *
+    <ahmederrachedbjld@gmail.com>                               *
+*****************************************************************/
+
+#ifndef __DELAY_H
+#define __DELAY_H
+
+#include <stdint.h>
+
+void syncdelay(uint8_t count);
+void delay_5us(void);
+void delay_1ms(void);
+void delay_us(uint16_t delay);
+void delay_ms(uint16_t delay);
+
+#ifndef _IFREQ
+#define _IFREQ 48000   /* IFCLK frequency in kHz */
+#endif
+
+/* CFREQ can be any one of: 48000, 24000, or 12000 */
+#ifndef _CFREQ
+#define _CFREQ 48000   /* CLKOUT frequency in kHz */
+#endif
+
+#if (_IFREQ < 5000)
+#error "_IFREQ too small!  Valid Range: 5000 to 48000..."
+#endif
+
+#if (_IFREQ > 48000)
+#error "_IFREQ too large!  Valid Range: 5000 to 48000..."
+#endif
+
+#if (_CFREQ != 48000)
+#if (_CFREQ != 24000)
+#if (_CFREQ != 12000)
+#error "_CFREQ invalid!  Valid values: 48000, 24000, 12000..."
+#endif
+#endif
+#endif
+
+/* Synchronization Delay formula: see TRM section 15-14 */
+#define _SCYCL (3 * (_CFREQ) + 5 * (_IFREQ) - 1) / (2 * (_IFREQ))
+#endif

contrib/firmware/angie/c/include/fx2macros.h

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: LGPL-2.1-or-later */
+
+/*
+ * This code was taken from the fx2lib project from this link:
+ * https://github.com/djmuhlestein/fx2lib
+ *
+ * Copyright (C) 2009 Ubixum, Inc.
+*/
+
+/*! \file
+ *  Macros for simple common tasks in fx2 firmware.
+ * */
+
+#ifndef FX2MACROS_H
+#define FX2MACROS_H
+
+#include "reg_ezusb.h"
+
+typedef enum {FALSE = 0, TRUE} BOOL_VALS;
+
+/**
+ * \brief Used for getting and setting the CPU clock speed.
+ **/
+typedef enum {CLK_12M = 0, CLK_24M, CLK_48M} CLK_SPD;
+
+/**
+ * \brief Evaluates to a CLK_SPD enum.
+ **/
+#define CPUFREQ (CLK_SPD)((CPUCS & bmclkspd) >> 3)
+
+#endif

contrib/firmware/angie/c/include/i2c.h

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/****************************************************************************
+	File : i2c.h                                                            *
+	Contents : i2c bit-bang library                                         *
+	Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.              *
+	<aboudjelida@nanoxplore.com>                                            *
+	<ahmederrachedbjld@gmail.com>											*
+*****************************************************************************/
+
+#ifndef __I2C_H
+#define __I2C_H
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+
+bool get_status(void);
+void start_cd(void);
+void repeated_start(void);
+void stop_cd(void);
+void clock_cd(void);
+void send_ack(void);
+void send_nack(void);
+bool get_ack(void);
+
+uint8_t get_address(uint8_t adr, uint8_t rdwr);
+
+void send_byte(uint8_t input);
+uint8_t receive_byte(void);
+#endif

contrib/firmware/angie/c/include/io.h

@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/****************************************************************************
+    File : io.h                                                             *
+    Contents : input/output declaration header file for NanoXplore          *
+    USB-JTAG ANGIE adapter hardware.                                        *
+    Based on openULINK project code by: Martin Schmoelzer.                  *
+    Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.              *
+    <aboudjelida@nanoxplore.com>                                            *
+	<ahmederrachedbjld@gmail.com>											*
+*****************************************************************************/
+
+#ifndef __IO_H
+#define __IO_H
+
+#include "reg_ezusb.h"
+
+/* PORT A */
+#define PIN_SDA_DIR     IOA0
+/* PA1 Not Connected */
+#define PIN_RDWR_B      IOA2
+#define PIN_SDA         IOA3
+#define PIN_SCL         IOA4
+#define PIN_PROGRAM_B   IOA5
+/* PA6 Not Connected */
+/* PA7 Not Connected */
+
+/* PORT B */
+/* PB0 Not Connected */
+/* PB1 Not Connected */
+/* PB2 Not Connected */
+/* PB3 Not Connected */
+/* PB4 Not Connected */
+/* PB5 Not Connected */
+/* PB6 Not Connected */
+/* PB7 Not Connected */
+
+/* PORT C */
+#define PIN_T0      IOC0
+#define PIN_T1      IOC1
+#define PIN_T2      IOC2
+#define PIN_T3      IOC3
+#define PIN_T4      IOC4
+/* PC5 Not Connected */
+/* PC6 Not Connected */
+/* PC7 Not Connected */
+
+/* PORT D */
+/* PD0 Not Connected */
+/* PD1 Not Connected */
+/* PD2 Not Connected */
+/* PD3 Not Connected */
+/* PD4 Not Connected */
+/* PD5 Not Connected */
+/* PD6 Not Connected */
+/* PD7 Not Connected */
+
+#endif

contrib/firmware/angie/c/include/msgtypes.h

@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/****************************************************************************
+    File : msgtypes.h                                                       *
+    Contents : Definition of the commands supported by NanoXplore           *
+    USB-JTAG ANGIE adapter hardware.                                        *
+    Based on openULINK project code by: Martin Schmoelzer.                  *
+    Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.              *
+    <aboudjelida@nanoxplore.com>                                            *
+	<ahmederrachedbjld@gmail.com>											*
+*****************************************************************************/
+
+/**
+ * @file
+ * Definition of the commands supported by the ANGIE firmware.
+ *
+ * Basically, two types of commands can be distinguished:
+ *  - Commands with fixed payload size
+ *  - Commands with variable payload size
+ *
+ * SCAN commands (in all variations) carry payloads of variable size, all
+ * other commands carry payloads of fixed size.
+ *
+ * In the case of SCAN commands, the payload size (n) is calculated by
+ * dividing the scan_size_bits variable by 8, rounding up the result.
+ *
+ * Offset zero always contains the command ID.
+ *
+ ****************************************************************************
+ * CMD_SCAN_IN, CMD_SLOW_SCAN_IN:                                           *
+ *                                                                          *
+ * OUT:                                                                     *
+ * offset 1: scan_size_bytes                                                *
+ * offset 2: bits_last_byte                                                 *
+ * offset 3: tms_count_start + tms_count_end                                *
+ * offset 4: tms_sequence_start                                             *
+ * offset 5: tms_sequence_end                                               *
+ *                                                                          *
+ * IN:                                                                      *
+ * offset 0..n: TDO data                                                    *
+ ****************************************************************************
+ * CMD_SCAN_OUT, CMD_SLOW_SCAN_OUT:                                         *
+ *                                                                          *
+ * OUT:                                                                     *
+ * offset 1: scan_size_bytes                                                *
+ * offset 2: bits_last_byte                                                 *
+ * offset 3: tms_count_start + tms_count_end                                *
+ * offset 4: tms_sequence_start                                             *
+ * offset 5: tms_sequence_end                                               *
+ * offset 6..x: TDI data                                                    *
+ ****************************************************************************
+ * CMD_SCAN_IO, CMD_SLOW_SCAN_IO:                                           *
+ *                                                                          *
+ * OUT:                                                                     *
+ * offset 1: scan_size_bytes                                                *
+ * offset 2: bits_last_byte                                                 *
+ * offset 3: tms_count_start + tms_count_end                                *
+ * offset 4: tms_sequence_start                                             *
+ * offset 5: tms_sequence_end                                               *
+ * offset 6..x: TDI data                                                    *
+ *                                                                          *
+ * IN:                                                                      *
+ * offset 0..n: TDO data                                                    *
+ ****************************************************************************
+ * CMD_CLOCK_TMS, CMD_SLOW_CLOCK_TMS:                                       *
+ *                                                                          *
+ * OUT:                                                                     *
+ * offset 1: tms_count                                                      *
+ * offset 2: tms_sequence                                                   *
+ ****************************************************************************
+ * CMD_CLOCK_TCK, CMD_SLOW_CLOCK_TCK:                                       *
+ *                                                                          *
+ * OUT:                                                                     *
+ * offset 1: low byte of tck_count                                          *
+ * offset 2: high byte of tck_count                                         *
+ ****************************************************************************
+ * CMD_CLOCK_SLEEP_US:                                                      *
+ *                                                                          *
+ * OUT:                                                                     *
+ * offset 1: low byte of sleep_us                                           *
+ * offset 2: high byte of sleep_us                                          *
+ ****************************************************************************
+ * CMD_CLOCK_SLEEP_MS:                                                      *
+ *                                                                          *
+ * OUT:                                                                     *
+ * offset 1: low byte of sleep_ms                                           *
+ * offset 2: high byte of sleep_ms                                          *
+ ****************************************************************************
+ * CMD_GET_SIGNALS:                                                         *
+ *                                                                          *
+ * IN:                                                                      *
+ * offset 0: current state of input signals                                 *
+ * offset 1: current state of output signals                                *
+ ****************************************************************************
+ * CMD_SET_SIGNALS:                                                         *
+ *                                                                          *
+ * OUT:                                                                     *
+ * offset 1: signals that should be de-asserted                             *
+ * offset 2: signals that should be asserted                                *
+ ****************************************************************************
+ * CMD_CONFIGURE_TCK_FREQ:                                                  *
+ *                                                                          *
+ * OUT:                                                                     *
+ * offset 1: delay value for scan_in function                               *
+ * offset 2: delay value for scan_out function                              *
+ * offset 3: delay value for scan_io function                               *
+ * offset 4: delay value for clock_tck function                             *
+ * offset 5: delay value for clock_tms function                             *
+ ****************************************************************************
+ * CMD_SET_LEDS:                                                            *
+ *                                                                          *
+ * OUT:                                                                     *
+ * offset 1: LED states:                                                    *
+ *           Bit 0: turn COM LED on                                         *
+ *           Bit 1: turn RUN LED on                                         *
+ *           Bit 2: turn COM LED off                                        *
+ *           Bit 3: turn RUN LED off                                        *
+ *           Bits 7..4: Reserved                                            *
+ ****************************************************************************
+ * CMD_TEST:                                                                *
+ *                                                                          *
+ * OUT:                                                                     *
+ * offset 1: unused dummy value                                             *
+ ****************************************************************************
+ */
+
+#ifndef __MSGTYPES_H
+#define __MSGTYPES_H
+
+/*
+ * Command IDs:
+ *
+ * Bits 7..6: Reserved, should always be zero
+ * Bits 5..0: Command ID. There are 62 usable IDs. Of this 63 available IDs,
+ *            the IDs 0x00..0x1F are commands with variable payload size,
+ *            the IDs 0x20..0x3F are commands with fixed payload size.
+ */
+
+#define CMD_ID_MASK             0x3F
+
+/* Commands with variable payload size */
+#define CMD_SCAN_IN             0x00
+#define CMD_SLOW_SCAN_IN        0x01
+#define CMD_SCAN_OUT            0x02
+#define CMD_SLOW_SCAN_OUT       0x03
+#define CMD_SCAN_IO             0x04
+#define CMD_SLOW_SCAN_IO        0x05
+
+/* Commands with fixed payload size */
+#define CMD_CLOCK_TMS           0x20
+#define CMD_SLOW_CLOCK_TMS      0x21
+#define CMD_CLOCK_TCK           0x22
+#define CMD_SLOW_CLOCK_TCK      0x23
+#define CMD_SLEEP_US            0x24
+#define CMD_SLEEP_MS            0x25
+#define CMD_GET_SIGNALS         0x26
+#define CMD_SET_SIGNALS         0x27
+#define CMD_CONFIGURE_TCK_FREQ  0x28
+#define CMD_SET_LEDS            0x29
+#define CMD_TEST                0x2A
+
+/* JTAG signal definition for jtag_get_signals() -- Input signals! */
+#define SIGNAL_TDO      1
+
+/* JTAG signal definition for jtag_get_signals() -- Output signals! */
+#define SIGNAL_TDI      8
+#define SIGNAL_TMS      2
+#define SIGNAL_TCK      4
+#define SIGNAL_TRST     1
+#define SIGNAL_SRST     32
+
+#endif

contrib/firmware/angie/c/include/reg_ezusb.h

@@ -0,0 +1,656 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/****************************************************************************
+    File : reg_ezusb.h                                                      *
+    Contents : FX2 microcontroller registers file for NanoXplore            *
+    USB-JTAG ANGIE adapter hardware.                                        *
+    Based on openULINK project code by: Martin Schmoelzer.                  *
+    Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.              *
+    <aboudjelida@nanoxplore.com>                                            *
+	<ahmederrachedbjld@gmail.com>											*
+*****************************************************************************/
+
+#ifndef REG_EZUSB_H
+#define REG_EZUSB_H
+
+/**
+ * @file
+ * All information in this file was taken from the EZ-USB FX2 Technical
+ * Reference Manual, Cypress Semiconductor, 3901 North First Street
+ * San Jose, CA 95134 (www.cypress.com).
+ *
+ * The EZ-USB Technical Reference Manual is called "EZ-USB FX2 TRM" hereafter.
+ */
+
+/* Compiler-specific definitions of SBIT, SFR, SFRX, ... macros */
+#include <mcs51/compiler.h>
+
+/* Bit vectors */
+#define bmbit0      0x01
+#define bmbit1      0x02
+#define bmbit2      0x04
+#define bmbit3      0x08
+#define bmbit4      0x10
+#define bmbit5      0x20
+#define bmbit6      0x40
+#define bmbit7      0x80
+
+/**************************************************************************
+ ************************ Special Function Registers **********************
+ ***************************************************************************/
+SFR(IOA,            0x80);
+SBIT(IOA0,          0x80, 0);
+SBIT(IOA1,          0x80, 1);
+SBIT(IOA2,          0x80, 2);
+SBIT(IOA3,          0x80, 3);
+SBIT(IOA4,          0x80, 4);
+SBIT(IOA5,          0x80, 5);
+SBIT(IOA6,          0x80, 6);
+SBIT(IOA7,          0x80, 7);
+
+SFR(SP,             0x81);
+SFR(DPL0,           0x82);
+SFR(DPH0,           0x83);
+SFR(DPL1,           0x84);
+SFR(DPL2,           0x85);
+
+SFR(DPS,            0x86);
+#define SEL         bmbit0
+/* Bit 1 read-only, always reads '0' */
+/* Bit 2 read-only, always reads '0' */
+/* Bit 3 read-only, always reads '0' */
+/* Bit 4 read-only, always reads '0' */
+/* Bit 5 read-only, always reads '0' */
+/* Bit 6 read-only, always reads '0' */
+/* Bit 7 read-only, always reads '0' */
+
+SFR(PCON,           0x87);
+#define IDLE        bmbit0
+#define STOP        bmbit1
+#define GF0         bmbit2
+#define GF1         bmbit3
+/* Bit 4 read-only, always reads '1' */
+/* Bit 5 read-only, always reads '1' */
+/* Bit 6 unused */
+#define SMOD0     bmbit7
+
+SFR(TCON,           0x88);
+SBIT(IT0,           0x88, 0);
+SBIT(IE0,           0x88, 1);
+SBIT(IT1,           0x88, 2);
+SBIT(IE1,           0x88, 3);
+SBIT(TR0,           0x88, 4);
+SBIT(TF0,           0x88, 5);
+SBIT(TR1,           0x88, 6);
+SBIT(TF1,           0x88, 7);
+
+SFR(TMOD,           0x89);
+SFR(TL0,            0x8A);
+SFR(TL1,            0x8B);
+SFR(TH0,            0x8C);
+SFR(TH1,            0x8D);
+
+SFR(CKCON,          0x8E);
+#define MD0         bmbit0
+#define MD1         bmbit1
+#define MD2         bmbit2
+#define T0M         bmbit3
+#define T1M         bmbit4
+#define T2M         bmbit5
+/* Bit 6 unused */
+/* Bit 7 unused */
+
+SFR(SPC_FNC,        0x8F);
+#define BMWRS       bmbit0
+/* Bit 1 read-only, always reads '0' */
+/* Bit 2 read-only, always reads '0' */
+/* Bit 3 read-only, always reads '0' */
+/* Bit 4 read-only, always reads '0' */
+/* Bit 5 read-only, always reads '0' */
+/* Bit 6 read-only, always reads '0' */
+/* Bit 7 read-only, always reads '0' */
+
+SFR(IOB,            0x90);
+SBIT(IOB0,          0x90, 0);
+SBIT(IOB1,          0x90, 1);
+SBIT(IOB2,          0x90, 2);
+SBIT(IOB3,          0x90, 3);
+SBIT(IOB4,          0x90, 4);
+SBIT(IOB5,          0x90, 5);
+SBIT(IOB6,          0x90, 6);
+SBIT(IOB7,          0x90, 7);
+
+SFR(EXIF,           0x91);
+SBIT(USBINT,        0x91, 4);
+SBIT(I2CINT,        0x91, 5);
+SBIT(IE4,           0x91, 6);
+SBIT(IE5,           0x91, 7);
+
+SFR(MPAGE,          0x92);
+SFR(SCON0,          0x98);
+SBIT(RI,            0x98, 0);
+SBIT(TI,            0x98, 1);
+SBIT(RB8,           0x98, 2);
+SBIT(TB8,           0x98, 3);
+SBIT(REN,           0x98, 4);
+SBIT(SM2,           0x98, 5);
+SBIT(SM1,           0x98, 6);
+SBIT(SM0,           0x98, 7);
+
+SFR(SBUF0,          0x99);
+SFR(AUTOPTRH1,      0x9A);
+SFR(AUTOPTRL1,      0x9B);
+SFR(AUTOPTRH2,      0x9D);
+SFR(AUTOPTRL2,      0x9E);
+
+#define AUTOPTR1H AUTOPTRH1 /* for backwards compatibility with examples */
+#define AUTOPTR1L AUTOPTRL1 /* for backwards compatibility with examples */
+#define APTR1H AUTOPTRH1 /* for backwards compatibility with examples */
+#define APTR1L AUTOPTRL1 /* for backwards compatibility with examples */
+
+SFR(IOC,            0xA0);
+SBIT(IOC0,          0xA0, 0);
+SBIT(IOC1,          0xA0, 1);
+SBIT(IOC2,          0xA0, 2);
+SBIT(IOC3,          0xA0, 3);
+SBIT(IOC4,          0xA0, 4);
+SBIT(IOC5,          0xA0, 5);
+SBIT(IOC6,          0xA0, 6);
+SBIT(IOC7,          0xA0, 7);
+
+SFR(INT2CLR,        0xA1);
+SFR(INT4CLR,        0xA2);
+SFR(IE,             0xA8);
+SBIT(EX0,           0xA8, 0);
+SBIT(ET0,           0xA8, 1);
+SBIT(EX1,           0xA8, 2);
+SBIT(ET1,           0xA8, 3);
+SBIT(ES0,           0xA8, 4);
+SBIT(ET2,           0xA8, 5);
+SBIT(ES1,           0xA8, 6);
+SBIT(EA,            0xA8, 7);
+
+SFR(EP2468STAT,     0xAA);
+#define EP8F        bmbit7
+#define EP8E        bmbit6
+#define EP6F        bmbit5
+#define EP6E        bmbit4
+#define EP4F        bmbit3
+#define EP4E        bmbit2
+#define EP2F        bmbit1
+#define EP2E        bmbit0
+
+SFR(EP24FIFOFLGS,   0xAB);
+SFR(EP68FIFOFLGS,   0xAC);
+SFR(AUTOPTRSETUP,   0xAF);
+SFR(IOD,            0xB0);
+SBIT(IOD0,          0xB0, 0);
+SBIT(IOD1,          0xB0, 1);
+SBIT(IOD2,          0xB0, 2);
+SBIT(IOD3,          0xB0, 3);
+SBIT(IOD4,          0xB0, 4);
+SBIT(IOD5,          0xB0, 5);
+SBIT(IOD6,          0xB0, 6);
+SBIT(IOD7,          0xB0, 7);
+
+SFR(IOE,            0xB1);
+SFR(OEA,            0xB2);
+SFR(OEB,            0xB3);
+SFR(OEC,            0xB4);
+SFR(OED,            0xB5);
+SFR(OEE,            0xB6);
+
+SFR(IP,             0xB8);
+SBIT(PX0,           0xB8, 0);
+SBIT(PT0,           0xB8, 1);
+SBIT(PX1,           0xB8, 2);
+SBIT(PT1,           0xB8, 3);
+SBIT(PS0,           0xB8, 4);
+SBIT(PT2,           0xB8, 5);
+SBIT(PS1,           0xB8, 6);
+/* Bit 7 read-only, always reads '1' */
+
+SFR(EP01STAT,       0xBA);
+SFR(GPIFTRIG,       0xBB);
+#define BMGPIFDONE  bmbit7
+#define BMGPIFREAD  bmbit2
+#define GPIF_EP2    0
+#define GPIF_EP4    1
+#define GPIF_EP6    2
+#define GPIF_EP8    3
+
+SFR(GPIFSGLDATH,    0xBD);
+SFR(GPIFSGLDATLX,   0xBE);
+SFR(GPIFSGLDATLNOX, 0xBF);
+
+SFR(SCON1,          0xC0);
+SBIT(RI_1,          0xC0, 0);
+SBIT(TI_1,          0xC0, 1);
+SBIT(RB8_1,         0xC0, 2);
+SBIT(TB8_1,         0xC0, 3);
+SBIT(REN_1,         0xC0, 4);
+SBIT(SM2_1,         0xC0, 5);
+SBIT(SM1_1,         0xC0, 6);
+SBIT(SM0_1,         0xC0, 7);
+
+SFR(SBUF1,          0xC1);
+SFR(T2CON,          0xC8);
+SBIT(CPRL2,         0xC8, 0);
+SBIT(C_T2,          0xC8, 1);
+SBIT(TR2,           0xC8, 2);
+SBIT(EXEN2,         0xC8, 3);
+SBIT(TCLK,          0xC8, 4);
+SBIT(RCLK,          0xC8, 5);
+SBIT(EXF2,          0xC8, 6);
+SBIT(TF2,           0xC8, 7);
+
+SFR(RCAP2L,         0xCA);
+SFR(RCAP2H,         0xCB);
+SFR(TL2,            0xCC);
+SFR(TH2,            0xCD);
+SFR(PSW,            0xD0);
+SBIT(P,             0xD0, 0);
+SBIT(F1,            0xD0, 1);
+SBIT(OV,            0xD0, 2);
+SBIT(RS0,           0xD0, 3);
+SBIT(RS1,           0xD0, 4);
+SBIT(F0,            0xD0, 5);
+SBIT(AC,            0xD0, 6);
+SBIT(CY,            0xD0, 7);
+
+SFR(EICON,          0xD8);
+/* Bit 0 read-only, always reads '0' */
+/* Bit 1 read-only, always reads '0' */
+/* Bit 2 read-only, always reads '0' */
+SBIT(INT6,          0xD8, 3);
+SBIT(RESI,          0xD8, 4);
+SBIT(ERESI,         0xD8, 5);
+/* Bit 6 read-only, always reads '1' */
+SBIT(SMOD1,         0xD8, 7);
+
+SFR(ACC,            0xE0);
+SFR(EIE,            0xE8);
+SBIT(EUSB,          0xE8, 0);
+SBIT(EI2C,          0xE8, 1);
+SBIT(EX4,           0xE8, 2);
+SBIT(EX5,           0xE8, 3);
+SBIT(EWDI,          0xE8, 4);
+/* Bit 5 read-only, always reads '1' */
+/* Bit 6 read-only, always reads '1' */
+/* Bit 7 read-only, always reads '1' */
+
+SFR(B,              0xF0);
+SFR(EIP,            0xF8);
+SBIT(PUSB,          0xF8, 0);
+SBIT(PI2C,          0xF8, 1);
+SBIT(PX4,           0xF8, 2);
+SBIT(PX5,           0xF8, 3);
+SBIT(PX6,           0xF8, 4);
+/* Bit 5 read-only, always reads '1' */
+/* Bit 6 read-only, always reads '1' */
+/* Bit 7 read-only, always reads '1' */
+
+/**************************************************************************
+ ***************************** XDATA Registers ****************************
+ ***************************************************************************/
+
+SFRX(GPIF_WAVE_DATA,         0xE400);
+SFRX(RES_WAVEDATA_END,       0xE480);
+
+/* General Configuration */
+SFRX(CPUCS,         0xE600);
+#define RES8051     bmbit0
+#define CLKOE       bmbit1
+#define BMCLKINV    bmbit2
+#define bmclkspd0   bmbit3
+#define bmclkspd1   bmbit4
+#define bmclkspd   (bmbit4 | bmbit3)
+#define BMPRTCSTB   bmbit5
+
+/* PCON register */
+#define BMSMOD0     bmbit7
+
+SFRX(IFCONFIG,        0xE601);
+#define BMIFCLKSRC    bmbit7
+#define BM3048MHZ     bmbit6
+#define BMIFCLKOE     bmbit5
+#define BMIFCLKPOL    bmbit4
+#define BMASYNC       bmbit3
+#define BMGSTATE      bmbit2
+#define BMIFCFG1      bmbit1
+#define BMIFCFG0      bmbit0
+#define BMIFCFGMASK   (BMIFCFG0 | BMIFCFG1)
+#define BMIFGPIF      BMIFCFG1
+
+SFRX(PINFLAGSAB,      0xE602);
+SFRX(PINFLAGSCD,      0xE603);
+SFRX(FIFORESET,       0xE604);
+#define BMNAKALL      bmbit7
+
+SFRX(BREAKPT,         0xE605);
+#define BMBREAK       bmbit3
+#define BMBPPULSE     bmbit2
+#define BMBPEN        bmbit1
+
+SFRX(BPADDRH,         0xE606);
+SFRX(BPADDRL,         0xE607);
+SFRX(UART230,         0xE608);
+SFRX(FIFOPINPOLAR,    0xE609);
+SFRX(REVID,           0xE60A);
+SFRX(REVCTL,          0xE60B);
+#define BMNOAUTOARM    bmbit1
+#define BMSKIPCOMMIT   bmbit0
+
+/* Endpoint Configuration */
+SFRX(EP1OUTCFG,       0xE610);
+SFRX(EP1INCFG,        0xE611);
+SFRX(EP2CFG,          0xE612);
+SFRX(EP4CFG,          0xE613);
+SFRX(EP6CFG,          0xE614);
+SFRX(EP8CFG,          0xE615);
+SFRX(EP2FIFOCFG,      0xE618);
+SFRX(EP4FIFOCFG,      0xE619);
+SFRX(EP6FIFOCFG,      0xE61A);
+SFRX(EP8FIFOCFG,      0xE61B);
+#define BMINFM        bmbit6
+#define BMOEP         bmbit5
+#define BMAUTOOUT     bmbit4
+#define BMAUTOIN      bmbit3
+#define BMZEROLENIN   bmbit2
+#define BMWORDWIDE    bmbit0
+
+SFRX(EP2AUTOINLENH,   0xE620);
+SFRX(EP2AUTOINLENL,   0xE621);
+SFRX(EP4AUTOINLENH,   0xE622);
+SFRX(EP4AUTOINLENL,   0xE623);
+SFRX(EP6AUTOINLENH,   0xE612);
+SFRX(EP6AUTOINLENL,   0xE613);
+SFRX(EP8AUTOINLENH,   0xE614);
+SFRX(EP8AUTOINLENL,   0xE615);
+SFRX(EP2FIFOPFH,      0xE630);
+SFRX(EP2FIFOPFL,      0xE631);
+SFRX(EP4FIFOPFH,      0xE632);
+SFRX(EP4FIFOPFL,      0xE633);
+SFRX(EP6FIFOPFH,      0xE634);
+SFRX(EP6FIFOPFL,      0xE635);
+SFRX(EP8FIFOPFH,      0xE636);
+SFRX(EP8FIFOPFL,      0xE637);
+SFRX(EP2ISOINPKTS,    0xE640);
+SFRX(EP4ISOINPKTS,    0xE641);
+SFRX(EP6ISOINPKTS,    0xE642);
+SFRX(EP8ISOINPKTS,    0xE643);
+SFRX(INPKTEND,        0xE648);
+SFRX(OUTPKTEND,       0xE649);
+
+/* Interrupts */
+SFRX(EP2FIFOIE,       0xE650);
+SFRX(EP2FIFOIRQ,      0xE651);
+SFRX(EP4FIFOIE,       0xE652);
+SFRX(EP4FIFOIRQ,      0xE653);
+SFRX(EP6FIFOIE,       0xE654);
+SFRX(EP6FIFOIRQ,      0xE655);
+SFRX(EP8FIFOIE,       0xE656);
+SFRX(EP8FIFOIRQ,      0xE657);
+SFRX(IBNIE,           0xE658);
+SFRX(IBNIRQ,          0xE659);
+#define EP0IBN        bmbit0
+#define EP1IBN        bmbit1
+#define EP2IBN        bmbit2
+#define EP4IBN        bmbit3
+#define EP6IBN        bmbit4
+#define EP8IBN        bmbit5
+
+SFRX(NAKIE,           0xE65A);
+SFRX(NAKIRQ,          0xE65B);
+#define EP8PING       bmbit7
+#define EP6PING       bmbit6
+#define EP4PING       bmbit5
+#define EP2PING       bmbit4
+#define EP1PING       bmbit3
+#define EP0PING       bmbit2
+#define IBN           bmbit0
+
+SFRX(USBIEN,          0xE65C);
+SFRX(USBIRQ,          0xE65D);
+#define SUDAVI        bmbit0
+#define SOFI          bmbit1
+#define SUTOKI        bmbit2
+#define SUSPI         bmbit3
+#define URESI         bmbit4
+#define HSGRANT       bmbit5
+#define EP0ACK        bmbit6
+
+SFRX(EPIE,            0xE65E);
+SFRX(EPIRQ,           0xE65F);
+SFRX(GPIFIE,          0xE660);
+SFRX(GPIFIRQ,         0xE661);
+SFRX(USBERRIE,        0xE662);
+SFRX(USBERRIRQ,       0xE663);
+SFRX(ERRCNTLIM,       0xE664);
+SFRX(CLRERRCNT,       0xE665);
+SFRX(INT2IVEC,        0xE666);
+#define I2V0          bmbit2
+#define I2V1          bmbit3
+#define I2V2          bmbit4
+#define I2V3          bmbit5
+#define I2V4          bmbit6
+
+SFRX(INT4IVEC,        0xE667);
+SFRX(INTSETUP,        0xE668);
+#define AV4EN         bmbit0
+#define INT4IN        bmbit1
+#define AV2EN         bmbit3
+
+/* Input/Output */
+SFRX(PORTACFG,        0xE670);
+#define BMINT0        bmbit0
+#define BMINT1        bmbit1
+#define BMFLAGD       bmbit7
+
+SFRX(PORTCCFG,        0xE671);
+#define BMGPIFA0      bmbit0
+#define BMGPIFA1      bmbit1
+#define BMGPIFA2      bmbit2
+#define BMGPIFA3      bmbit3
+#define BMGPIFA4      bmbit4
+#define BMGPIFA5      bmbit5
+#define BMGPIFA6      bmbit6
+#define BMGPIFA7      bmbit7
+
+SFRX(PORTECFG,        0xE672);
+#define BMT0OUT       bmbit0
+#define BMT1OUT       bmbit1
+#define BMT2OUT       bmbit2
+#define BMRXD0OUT     bmbit3
+#define BMRXD1OUT     bmbit4
+#define BMINT6        bmbit5
+#define BMT2EX        bmbit6
+#define BMGPIFA8      bmbit7
+
+SFRX(I2CS,            0xE678);
+#define BMDONE        bmbit0
+#define BMACK         bmbit1
+#define BMBERR        bmbit2
+#define BMID         (bmbit4 | bmbit3)
+#define BMLASTRD      bmbit5
+#define BMSTOP        bmbit6
+#define BMSTART       bmbit7
+
+SFRX(I2DAT,           0xE679);
+SFRX(I2CTL,           0xE67A);
+#define BMSTOPIE      bmbit1
+#define BM400KHZ      bmbit0
+
+SFRX(XAUTODAT1,       0xE67B);
+SFRX(XAUTODAT2,       0xE67C);
+#define EXTAUTODAT1   XAUTODAT1
+#define EXTAUTODAT2   XAUTODAT2
+
+/* USB Control */
+SFRX(USBCS,           0xE680);
+#define SIGRSUME      bmbit0
+#define RENUM         bmbit1
+#define NOSYNSOF      bmbit2
+#define DISCON        bmbit3
+#define HSM           bmbit7
+
+SFRX(SUSPEND,         0xE681);
+SFRX(WAKEUPCS,        0xE682);
+#define BMWU2         bmbit7
+#define BMWU          bmbit6
+#define BMWU2POL      bmbit5
+#define BMWUPOL       bmbit4
+#define BMDPEN        bmbit2
+#define BMWU2EN       bmbit1
+#define BMWUEN        bmbit0
+
+SFRX(TOGCTL,           0xE683);
+#define BMTOGCTLEPMASK bmbit3 | bmbit2 | bmbit1 | bmbit0
+#define BMRESETTOGGLE  bmbit5
+#define BMSETTOGGLE    bmbit6
+#define BMQUERYTOGGLE  bmbit7
+
+SFRX(USBFRAMEH,        0xE684);
+SFRX(USBFRAMEL,        0xE685);
+SFRX(MICROFRAME,       0xE686);
+SFRX(FNADDR,           0xE687);
+
+/* Endpoints */
+SFRX(EP0BCH,           0xE68A);
+SFRX(EP0BCL,           0xE68B);
+SFRX(EP1OUTBC,         0xE68D);
+SFRX(EP1INBC,          0xE68F);
+SFRX(EP2BCH,           0xE690);
+SFRX(EP2BCL,           0xE691);
+SFRX(EP4BCH,           0xE694);
+SFRX(EP4BCL,           0xE695);
+SFRX(EP6BCH,           0xE698);
+SFRX(EP6BCL,           0xE699);
+SFRX(EP8BCH,           0xE69C);
+SFRX(EP8BCL,           0xE69D);
+SFRX(EP0CS,            0xE6A0);
+#define HSNAK          bmbit7
+
+SFRX(EP1INCS,          0xE6A2);
+SFRX(EP1OUTCS,         0xE6A1);
+#define EPSTALL        bmbit0
+#define EPBSY          bmbit1
+
+SFRX(EP2CS,            0xE6A3);
+SFRX(EP4CS,            0xE6A4);
+SFRX(EP6CS,            0xE6A5);
+SFRX(EP8CS,            0xE6A6);
+#define BMEPEMPTY      bmbit2
+#define BMEPFULL       bmbit3
+#define BMNPAK        (bmbit6 | bmbit5 | bmbit4)
+
+SFRX(EP2FIFOFLGS,      0xE6A7);
+SFRX(EP4FIFOFLGS,      0xE6A8);
+SFRX(EP6FIFOFLGS,      0xE6A9);
+SFRX(EP8FIFOFLGS,      0xE6AA);
+SFRX(EP2FIFOBCH,       0xE6AB);
+SFRX(EP2FIFOBCL,       0xE6AC);
+SFRX(EP4FIFOBCH,       0xE6AD);
+SFRX(EP4FIFOBCL,       0xE6AE);
+SFRX(EP6FIFOBCH,       0xE6AF);
+SFRX(EP6FIFOBCL,       0xE6B0);
+SFRX(EP8FIFOBCH,       0xE6B1);
+SFRX(EP8FIFOBCL,       0xE6B2);
+SFRX(SUDPTRH,          0xE6B3);
+SFRX(SUDPTRL,          0xE6B4);
+
+SFRX(SUDPTRCTL,        0xE6B5);
+#define BMSDPAUTO      bmbit0
+
+SFRX(SETUPDAT[8],      0xE6B8);
+
+/* GPIF */
+SFRX(GPIFWFSELECT,     0xE6C0);
+SFRX(GPIFIDLECS,       0xE6C1);
+SFRX(GPIFIDLECTL,      0xE6C2);
+SFRX(GPIFCTLCFG,       0xE6C3);
+SFRX(GPIFADRH,         0xE6C4);
+SFRX(GPIFADRL,         0xE6C5);
+SFRX(GPIFTCB3,         0xE6CE);
+SFRX(GPIFTCB2,         0xE6CF);
+SFRX(GPIFTCB1,         0xE6D0);
+SFRX(GPIFTCB0,         0xE6D1);
+
+#define EP2GPIFTCH     GPIFTCB1   /* these are here for backwards compatibility */
+#define EP2GPIFTCL     GPIFTCB0
+#define EP4GPIFTCH     GPIFTCB1   /* these are here for backwards compatibility */
+#define EP4GPIFTCL     GPIFTCB0
+#define EP6GPIFTCH     GPIFTCB1   /* these are here for backwards compatibility */
+#define EP6GPIFTCL     GPIFTCB0
+#define EP8GPIFTCH     GPIFTCB1   /* these are here for backwards compatibility */
+#define EP8GPIFTCL     GPIFTCB0
+
+SFRX(EP2GPIFFLGSEL,    0xE6D2);
+SFRX(EP2GPIFPFSTOP,    0xE6D3);
+SFRX(EP2GPIFTRIG,      0xE6D4);
+SFRX(EP4GPIFFLGSEL,    0xE6DA);
+SFRX(EP4GPIFPFSTOP,    0xE6DB);
+SFRX(EP4GPIFTRIG,      0xE6DC);
+SFRX(EP6GPIFFLGSEL,    0xE6E2);
+SFRX(EP6GPIFPFSTOP,    0xE6E3);
+SFRX(EP6GPIFTRIG,      0xE6E4);
+SFRX(EP8GPIFFLGSEL,    0xE6EA);
+SFRX(EP8GPIFPFSTOP,    0xE6EB);
+SFRX(EP8GPIFTRIG,      0xE6EC);
+SFRX(XGPIFSGLDATH,     0xE6F0);
+SFRX(XGPIFSGLDATLX,    0xE6F1);
+SFRX(XGPIFSGLDATLNOX,  0xE6F2);
+SFRX(GPIFREADYCFG,     0xE6F3);
+SFRX(GPIFREADYSTAT,    0xE6F4);
+SFRX(GPIFABORT,        0xE6F5);
+
+// UDMA
+SFRX(FLOWSTATE,        0xE6C6);
+SFRX(FLOWLOGIC,        0xE6C7);
+SFRX(FLOWEQ0CTL,       0xE6C8);
+SFRX(FLOWEQ1CTL,       0xE6C9);
+SFRX(FLOWHOLDOFF,      0xE6CA);
+SFRX(FLOWSTB,          0xE6CB);
+SFRX(FLOWSTBEDGE,      0xE6CC);
+SFRX(FLOWSTBHPERIOD,   0xE6CD);
+SFRX(GPIFHOLDAMOUNT,   0xE60C);
+SFRX(UDMACRCH,         0xE67D);
+SFRX(UDMACRCL,         0xE67E);
+SFRX(UDMACRCQUAL,      0xE67F);
+
+/* Debug/Test
+ * The following registers are for Cypress's internal testing purposes only.
+ * These registers are not documented in the datasheet or the Technical Reference
+ * Manual as they were not designed for end user application usage
+ */
+SFRX(DBUG,             0xE6F8);
+SFRX(TESTCFG,          0xE6F9);
+SFRX(USBTEST,          0xE6FA);
+SFRX(CT1,              0xE6FB);
+SFRX(CT2,              0xE6FC);
+SFRX(CT3,              0xE6FD);
+SFRX(CT4,              0xE6FE);
+
+/* Endpoint Buffers */
+SFRX(EP0BUF[64],        0xE740);
+SFRX(EP1INBUF[64],      0xE7C0);
+SFRX(EP1OUTBUF[64],     0xE780);
+SFRX(EP2FIFOBUF[1024],   0xF000);
+SFRX(EP4FIFOBUF[1024],   0xF400);
+SFRX(EP6FIFOBUF[1024],   0xF800);
+SFRX(EP8FIFOBUF[1024],   0xFC00);
+
+/* Error Correction Code (ECC) Registers (FX2LP/FX1 only) */
+SFRX(ECCCFG,            0xE628);
+SFRX(ECCRESET,          0xE629);
+SFRX(ECC1B0,            0xE62A);
+SFRX(ECC1B1,            0xE62B);
+SFRX(ECC1B2,            0xE62C);
+SFRX(ECC2B0,            0xE62D);
+SFRX(ECC2B1,            0xE62E);
+SFRX(ECC2B2,            0xE62F);
+
+/* Feature Registers  (FX2LP/FX1 only) */
+SFRX(GPCR2,         0xE50D);
+#define BMFULLSPEEDONLY    bmbit4
+
+#endif

contrib/firmware/angie/c/include/serial.h

@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: LGPL-2.1-or-later */
+
+/**
+ * This code was taken from the fx2lib project from this link:
+ * https://github.com/djmuhlestein/fx2lib
+ *
+ * Copyright (C) 2009 Ubixum, Inc.
+ **/
+
+/** \file serial.h
+ * defines functions to print to a serial console with SIO0
+ **/
+
+#include "fx2macros.h"
+#include <stdint.h>
+/**
+ * This function inits sio0 to use T2CON (timer 2)
+ * See TRM 14.3.4.1 (Table 14-16)
+ * Certain baud rates have too high an error rate to work.  All baud rates are .16%
+ * except:
+ *
+ *          12MHZ      24MHZ
+ *   \li 57600  -6.99%
+ *   \li 38400  -2.34%     -2.34%
+ *   \li 19200  -2.34%
+ *
+ *   Possible Baud rates:
+ *    \li 2400
+ *    \li 4800
+ *    \li 9600
+ *    \li 19200
+ *    \li 28800
+ *    \li 38400
+ *    \li 57600
+ *
+ *    Any of these rates should work except 57600 at 12mhz.  -2.34% is pushing
+ *    most hardware specs for working.  All rates at 48mhz work at .16%
+ **/
+
+void sio0_init(uint32_t baud_rate) __critical; /* baud_rate max should be 57600 since int=2 bytes */
+
+/**
+ * putchar('\\n') or putchar('\\r') both transmit \\r\\n
+ * Just use one or the other. (This makes terminal echo easy)
+ **/
+int putchar(char c);
+int getchar(void);

contrib/firmware/angie/c/include/usb.h

@@ -0,0 +1,283 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/****************************************************************************
+	File : usb.h															*
+	Contents : usb communication handling header file for NanoXplore		*
+	USB-JTAG ANGIE adapter hardware.										*
+	Based on openULINK project code by: Martin Schmoelzer.					*
+	Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.				*
+	<aboudjelida@nanoxplore.com>											*
+	<ahmederrachedbjld@gmail.com>											*
+*****************************************************************************/
+
+#ifndef __USB_H
+#define __USB_H
+
+#include "reg_ezusb.h"
+#include <stdint.h>
+#include <stdbool.h>
+
+/* High and Low byte of a word (uint16_t) */
+#define HI8(word)   (uint8_t)(((uint16_t)(word) >> 8) & 0xff)
+#define LO8(word)   (uint8_t)((uint16_t)(word) & 0xff)
+
+/* Convenience functions */
+#define STALL_EP0()   (EP0CS |= EPSTALL)
+#define CLEAR_IRQ()   (USBINT = 0)
+
+/*********** USB descriptors. See USB 2.0 Spec **********/
+
+/* USB Descriptor Types. See USB 2.0 Spec */
+#define DESCRIPTOR_TYPE_DEVICE                      0x01
+#define DESCRIPTOR_TYPE_CONFIGURATION               0x02
+#define DESCRIPTOR_TYPE_STRING                      0x03
+#define DESCRIPTOR_TYPE_INTERFACE                   0x04
+#define DESCRIPTOR_TYPE_ENDPOINT                    0x05
+
+#define STR_DESCR(len, ...) { (len) * 2 + 2, DESCRIPTOR_TYPE_STRING, { __VA_ARGS__ } }
+
+/** USB Device Descriptor. See USB 2.0 Spec */
+struct usb_device_descriptor {
+	uint8_t blength;		/**< Size of this descriptor in bytes. */
+	uint8_t bdescriptortype;	/**< DEVICE Descriptor Type. */
+	uint16_t bcdusb;		/**< USB specification release number (BCD). */
+	uint8_t bdeviceclass;		/**< Class code. */
+	uint8_t bdevicesubclass;	/**< Subclass code. */
+	uint8_t bdeviceprotocol;	/**< Protocol code. */
+	uint8_t bmaxpacketsize0;	/**< Maximum packet size for EP0 (8, 16, 32, 64). */
+	uint16_t idvendor;		/**< USB Vendor ID. */
+	uint16_t idproduct;		/**< USB Product ID. */
+	uint16_t bcddevice;		/**< Device Release Number (BCD). */
+	uint8_t imanufacturer;		/**< Index of manufacturer string descriptor. */
+	uint8_t iproduct;		/**< Index of product string descriptor. */
+	uint8_t iserialnumber;		/**< Index of string descriptor containing serial #. */
+	uint8_t bnumconfigurations;	/**< Number of possible configurations. */
+};
+
+/** USB Configuration Descriptor. See USB 2.0 Spec */
+struct usb_config_descriptor {
+	uint8_t blength;		/**< Size of this descriptor in bytes. */
+	uint8_t bdescriptortype;	/**< CONFIGURATION descriptor type. */
+	uint16_t wtotallength;		/**< Combined total length of all descriptors. */
+	uint8_t bnuminterfaces;		/**< Number of interfaces in this configuration. */
+	uint8_t bconfigurationvalue;	/**< Value used to select this configuration. */
+	uint8_t iconfiguration;		/**< Index of configuration string descriptor. */
+	uint8_t bmattributes;		/**< Configuration characteristics. */
+	uint8_t maxpower;		/**< Maximum power consumption in 2 mA units. */
+};
+
+/** USB Interface association Descriptor. See USB 2.0 Spec */
+struct usb_interface_association_descriptor {
+	uint8_t  blength;
+	uint8_t  bdescriptortype;
+	uint8_t  bfirstinterface;
+	uint8_t  binterfacecount;
+	uint8_t  bfunctionclass;
+	uint8_t  bfunctionsubclass;
+	uint8_t  bfunctionprotocol;
+	uint8_t  ifunction;
+};
+
+/** USB Interface Descriptor. See USB 2.0 Spec */
+struct usb_interface_descriptor {
+	uint8_t blength;		/**< Size of this descriptor in bytes. */
+	uint8_t bdescriptortype;	/**< INTERFACE descriptor type. */
+	uint8_t binterfacenumber;	/**< Interface number. */
+	uint8_t balternatesetting;	/**< Value used to select alternate setting. */
+	uint8_t bnumendpoints;		/**< Number of endpoints used by this interface. */
+	uint8_t binterfaceclass;	/**< Class code. */
+	uint8_t binterfacesubclass;	/**< Subclass code. */
+	uint8_t binterfaceprotocol;	/**< Protocol code. */
+	uint8_t iinterface;		/**< Index of interface string descriptor. */
+};
+
+/** USB Endpoint Descriptor. See USB 2.0 Spec */
+struct usb_endpoint_descriptor {
+	uint8_t blength;		/**< Size of this descriptor in bytes. */
+	uint8_t bdescriptortype;	/**< ENDPOINT descriptor type. */
+	uint8_t bendpointaddress;	/**< Endpoint Address: IN/OUT + EP number. */
+	uint8_t bmattributes;		/**< Endpoint Attributes: BULK/INTR/ISO/CTRL. */
+	uint16_t wmaxpacketsize;	/**< Maximum packet size for this endpoint. */
+	uint8_t binterval;		/**< Polling interval (in ms) for this endpoint. */
+};
+
+/** USB Language Descriptor. See USB 2.0 Spec */
+struct usb_language_descriptor {
+	uint8_t blength;		/**< Size of this descriptor in bytes. */
+	uint8_t bdescriptortype;	/**< STRING descriptor type. */
+	uint16_t wlangid;		/**< LANGID codes. */
+};
+
+/** USB String Descriptor. See USB 2.0 Spec */
+struct usb_string_descriptor {
+	uint8_t blength;		/**< Size of this descriptor in bytes. */
+	uint8_t bdescriptortype;	/**< STRING descriptor type. */
+	uint16_t bstring[];		/**< UNICODE encoded string. */
+};
+
+/********************** USB Control Endpoint 0 related *********************/
+
+/** USB Control Setup Data. See USB 2.0 Spec */
+struct setup_data {
+	uint8_t bmrequesttype;		/**< Characteristics of a request. */
+	uint8_t brequest;		/**< Specific request. */
+	uint16_t wvalue;		/**< Field that varies according to request. */
+	uint16_t windex;		/**< Field that varies according to request. */
+	uint16_t wlength;		/**< Number of bytes to transfer in data stage. */
+};
+
+extern volatile __xdata __at 0xE6B8 struct setup_data setup_data;
+
+/*
+ * USB Request Types (bmRequestType): See USB 2.0 Spec
+ *
+ * Bit 7: Data transfer direction
+ *	0 = Host-to-device
+ *	1 = Device-to-host
+ * Bit 6...5: Type
+ *	0 = Standard
+ *	1 = Class
+ *	2 = Vendor
+ *	3 = Reserved
+ * Bit 4...0: Recipient
+ *	0 = Device
+ *	1 = Interface
+ *	2 = Endpoint
+ *	3 = Other
+ *	4...31 = Reserved
+ */
+
+#define USB_DIR_OUT         0x00
+#define USB_DIR_IN          0x80
+
+#define USB_REQ_TYPE_STANDARD   (0x00 << 5)
+#define USB_REQ_TYPE_CLASS      (0x01 << 5)
+#define USB_REQ_TYPE_VENDOR     (0x02 << 5)
+#define USB_REQ_TYPE_RESERVED   (0x03 << 5)
+
+#define USB_RECIP_DEVICE    0x00
+#define USB_RECIP_INTERFACE 0x01
+#define USB_RECIP_ENDPOINT  0x02
+#define USB_RECIP_OTHER     0x03
+
+/* Clear Interface Request */
+#define CF_DEVICE	(USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE)
+#define CF_INTERFACE (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_INTERFACE)
+#define CF_ENDPOINT  (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_ENDPOINT)
+
+/* Get Configuration Request */
+#define GC_DEVICE	(USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE)
+
+/* Get Descriptor Request */
+#define GD_DEVICE	(USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE)
+
+/* Get Interface Request */
+#define GI_INTERFACE (USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_INTERFACE)
+
+/* Get Status Request: See USB 1.1 spec, page 190 */
+#define GS_DEVICE	(USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE)
+#define GS_INTERFACE (USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_INTERFACE)
+#define GS_ENDPOINT  (USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_ENDPOINT)
+
+/* Set Address Request is handled by EZ-USB core */
+
+/* Set Configuration Request */
+#define SC_DEVICE	(USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE)
+
+/* Set Descriptor Request */
+#define SD_DEVICE	(USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE)
+
+/* Set Feature Request */
+#define SF_DEVICE	(USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_DEVICE)
+#define SF_INTERFACE (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_INTERFACE)
+#define SF_ENDPOINT  (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_ENDPOINT)
+
+/* Set Interface Request */
+#define SI_INTERFACE (USB_DIR_OUT | USB_REQ_TYPE_STANDARD | USB_RECIP_INTERFACE)
+
+/* Synch Frame Request */
+#define SY_ENDPOINT  (USB_DIR_IN | USB_REQ_TYPE_STANDARD | USB_RECIP_ENDPOINT)
+
+/* USB Requests (bRequest): See USB 2.0 Spec */
+#define GET_STATUS              0
+#define CLEAR_FEATURE           1
+/* Value '2' is reserved for future use */
+#define SET_FEATURE             3
+/* Value '4' is reserved for future use */
+#define SET_ADDRESS             5
+#define GET_DESCRIPTOR          6
+#define SET_DESCRIPTOR          7
+#define GET_CONFIGURATION       8
+#define SET_CONFIGURATION		9
+#define GET_INTERFACE           10
+#define SET_INTERFACE           11
+#define SYNCH_FRAME             12
+
+/* Standard Feature Selectors: See USB 2.0 Spec */
+#define DEVICE_REMOTE_WAKEUP    1
+#define ENDPOINT_HALT           0
+
+/************************** EZ-USB specific stuff **************************/
+/** USB Interrupts. See EZ-USB FX2-TRM, for details */
+enum usb_isr {
+	SUDAV_ISR = 13,
+	SOF_ISR,
+	SUTOK_ISR,
+	SUSPEND_ISR,
+	USBRESET_ISR,
+	HIGHSPEED_ISR,
+	EP0ACK_ISR,
+	STUB_ISR,
+	EP0IN_ISR,
+	EP0OUT_ISR,
+	EP1IN_ISR,
+	EP1OUT_ISR,
+	EP2_ISR,
+	EP4_ISR,
+	EP6_ISR,
+	EP8_ISR,
+	IBN_ISR,
+	EP0PINGNAK_ISR,
+	EP1PINGNAK_ISR,
+	EP2PINGNAK_ISR,
+	EP4PINGNAK_ISR,
+	EP6PINGNAK_ISR,
+	EP8PINGNAK_ISR,
+	ERRORLIMIT_ISR,
+	EP2PIDERROR_ISR,
+	EP4PIDERROR_ISR,
+	EP6PIDERROR_ISR,
+	EP8PIDERROR_ISR,
+	EP2PFLAG_ISR,
+	EP4PFLAG_ISR,
+	EP6PFLAG_ISR,
+	EP8PFLAG_ISR,
+	EP2EFLAG_ISR,
+	EP4EFLAG_ISR,
+	EP6EFLAG_ISR,
+	EP8EFLAG_ISR,
+	EP2FFLAG_ISR,
+	EP4FFLAG_ISR,
+	EP6FFLAG_ISR,
+	EP8FFLAG_ISR,
+	GPIFCOMPLETE_ISR,
+	GPIFWAVEFORM_ISR
+};
+
+/*************************** Function Prototypes ***************************/
+__xdata uint8_t *usb_get_endpoint_cs_reg(uint8_t ep);
+void usb_reset_data_toggle(uint8_t ep);
+bool usb_handle_get_status(void);
+bool usb_handle_clear_feature(void);
+bool usb_handle_set_feature(void);
+bool usb_handle_get_descriptor(void);
+void usb_handle_set_interface(void);
+void usb_handle_setup_data(void);
+bool usb_handle_vcommands(void);
+void set_gpif_cnt(uint32_t count);
+
+void i2c_recieve(void);
+void ep_init(void);
+void interrupt_init(void);
+void io_init(void);
+
+#endif

contrib/firmware/angie/c/src/USBJmpTb.a51

@@ -0,0 +1,125 @@
+; SPDX-License-Identifier: GPL-2.0-or-later
+;****************************************************************************
+;	File : USBJmpTb.a51														*
+;	Contents : Interruptions vector configuration.                    		*
+;	Based on openULINK project code by: Martin Schmoelzer.					*
+;	Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.				*
+;	<aboudjelida@nanoxplore.com>											*
+;	<ahmederrachedbjld@gmail.com>											*
+;****************************************************************************
+.module JUMPTABLE
+
+.globl USB_AutoVector
+.globl USB_Jump_Table
+
+.globl _sudav_isr, _sof_isr, _sutok_isr, _suspend_isr, _usbreset_isr, _highspeed_isr, _ep0ack_isr, _stub_isr, _ep0in_isr, _ep0out_isr, _ep1in_isr, _ep1out_isr, _ep2_isr, _ep4_isr, _ep6_isr, _ep8_isr, _ibn_isr
+.globl _ep0pingnak_isr, _ep1pingnak_isr, _ep2pingnak_isr, _ep4pingnak_isr, _ep6pingnak_isr, _ep8pingnak_isr, _errorlimit_isr, _stub_isr, _stub_isr, _stub_isr, _ep2piderror_isr, _ep4piderror_isr, _ep6piderror_isr, _ep8piderror_isr
+.globl _ep2pflag_isr, _ep4pflag_isr, _ep6pflag_isr, _ep8pflag_isr, _ep2eflag_isr, _ep4eflag_isr, _ep6eflag_isr, _ep8eflag_isr, _ep2fflag_isr, _ep4fflag_isr, _ep6fflag_isr, _ep8fflag_isr, _gpifcomplete_isr, _gpifwaveform_isr
+
+;--------------------------------------------------------------------------;
+; Interrupt Vectors                                                        ;
+;--------------------------------------------------------------------------;
+.area   USB_JV (ABS,OVR)   ; Absolute, Overlay
+.org    0x43               ; USB interrupt (INT2) jumps here
+USB_AutoVector = #. + 2
+    ljmp  USB_Jump_Table    ; Autovector will replace byte 45
+
+;--------------------------------------------------------------------------;
+; USB Jump Table                                                           ;
+;--------------------------------------------------------------------------;
+.area  USB_JT (ABS)        ; Absolute placement
+.org   0x0200              ; Place jump table at 0x0200
+
+USB_Jump_Table:            ; autovector jump table
+    ljmp  _sudav_isr       ; (00) Setup Data Available
+    .db 0
+    ljmp  _sof_isr         ; (04) Start of Frame
+    .db 0
+    ljmp  _sutok_isr       ; (08) Setup Data Loading
+    .db 0
+    ljmp  _suspend_isr     ; (0C) Global Suspend
+    .db 0
+    ljmp  _usbreset_isr    ; (10) USB Reset
+    .db 0
+    ljmp  _highspeed_isr   ; (14) Entered High Speed
+    .db 0
+    ljmp  _ep0ack_isr      ; (18) EP0ACK
+    .db 0
+    ljmp  _stub_isr        ; (1C) Reserved
+    .db 0
+    ljmp  _ep0in_isr       ; (20) EP0 In
+    .db 0
+    ljmp  _ep0out_isr      ; (24) EP0 Out
+    .db 0
+    ljmp  _ep1in_isr       ; (28) EP1 In
+    .db 0
+    ljmp  _ep1out_isr      ; (2C) EP1 Out
+    .db 0
+    ljmp  _ep2_isr         ; (30) EP2 In/Out
+    .db 0
+    ljmp  _ep4_isr         ; (34) EP4 In/Out
+    .db 0
+    ljmp  _ep6_isr         ; (38) EP6 In/Out
+    .db 0
+    ljmp  _ep8_isr         ; (3C) EP8 In/Out
+    .db 0
+    ljmp  _ibn_isr         ; (40) IBN
+    .db 0
+    ljmp  _stub_isr        ; (44) Reserved
+    .db 0
+    ljmp  _ep0pingnak_isr  ; (48) EP0 PING NAK
+    .db 0
+    ljmp  _ep1pingnak_isr  ; (4C) EP1 PING NAK
+    .db 0
+    ljmp  _ep2pingnak_isr  ; (50) EP2 PING NAK
+    .db 0
+    ljmp  _ep4pingnak_isr  ; (54) EP4 PING NAK
+    .db 0
+    ljmp  _ep6pingnak_isr  ; (58) EP6 PING NAK
+    .db 0
+    ljmp  _ep8pingnak_isr  ; (5C) EP8 PING NAK
+    .db 0
+    ljmp  _errorlimit_isr  ; (60) Error Limit
+    .db 0
+    ljmp  _stub_isr        ; (64) Reserved
+    .db 0
+    ljmp  _stub_isr        ; (68) Reserved
+    .db 0
+    ljmp  _stub_isr        ; (6C) Reserved
+    .db 0
+    ljmp  _ep2piderror_isr ; (70) EP2 ISO Pid Sequence Error
+    .db 0
+    ljmp  _ep4piderror_isr ; (74) EP4 ISO Pid Sequence Error
+    .db 0
+    ljmp  _ep6piderror_isr ; (78) EP6 ISO Pid Sequence Error
+    .db 0
+    ljmp  _ep8piderror_isr ; (7C) EP8 ISO Pid Sequence Error
+    .db 0
+    ljmp  _ep2pflag_isr    ; (80) EP2 Programmable Flag
+    .db 0
+    ljmp  _ep4pflag_isr    ; (84) EP4 Programmable Flag
+    .db 0
+    ljmp  _ep6pflag_isr    ; (88) EP6 Programmable Flag
+    .db 0
+    ljmp  _ep8pflag_isr    ; (8C) EP8 Programmable Flag
+    .db 0
+    ljmp  _ep2eflag_isr    ; (90) EP2 Empty Flag
+    .db 0
+    ljmp  _ep4eflag_isr    ; (94) EP4 Empty Flag
+    .db 0
+    ljmp  _ep6eflag_isr    ; (98) EP6 Empty Flag
+    .db 0
+    ljmp  _ep8eflag_isr    ; (9C) EP8 Empty Flag
+    .db 0
+    ljmp  _ep2fflag_isr    ; (A0) EP2 Full Flag
+    .db 0
+    ljmp  _ep4fflag_isr    ; (A4) EP4 Full Flag
+    .db 0
+    ljmp  _ep6fflag_isr    ; (A8) EP6 Full Flag
+    .db 0
+    ljmp  _ep8fflag_isr    ; (AC) EP8 Full Flag
+    .db 0
+    ljmp  _gpifcomplete_isr    ; (B0) GPIF Operation Complete
+    .db 0
+    ljmp  _gpifwaveform_isr    ; (B4) GPIF Waveform
+    .db 0

contrib/firmware/angie/c/src/delay.c

@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/****************************************************************************
+	File : delay.c															*
+	Contents : Delays handling fucntions code for NanoXplore				*
+	USB-JTAG ANGIE adapter hardware.										*
+	Based on openULINK project code by: Martin Schmoelzer.					*
+	Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.				*
+	<aboudjelida@nanoxplore.com>											*
+	<ahmederrachedbjld@gmail.com>											*
+*****************************************************************************/
+
+#include "delay.h"
+#include <mcs51/compiler.h>
+
+void syncdelay(uint8_t count)
+{
+	for (uint8_t i = 0; i < count; i++)
+		NOP();
+}
+
+void delay_5us(void)
+{
+	NOP();
+}
+
+void delay_1ms(void)
+{
+	uint16_t i;
+
+	for (i = 0; i < 598; i++)
+		;
+}
+
+void delay_us(uint16_t delay)
+{
+	uint16_t i;
+	uint16_t maxcount = (delay / 5);
+
+	for (i = 0; i < maxcount; i++)
+		delay_5us();
+}
+
+void delay_ms(uint16_t delay)
+{
+	uint16_t i;
+
+	for (i = 0; i < delay; i++)
+		delay_1ms();
+}

contrib/firmware/angie/c/src/gpif.c

@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+  This program configures the General Programmable Interface (GPIF) for FX2.
+  Please do not modify sections of text which are marked as "DO NOT EDIT ...".
+*/
+
+/* GPIF Program Code */
+
+#include "reg_ezusb.h"
+#include "delay.h"
+
+/****************************** GPIF PROGRAM CODE ********************************/
+/* DO NOT EDIT ... */
+const char wavedata[128] = {
+// Wave 0
+/* LenBr */ 0x01,     0x3F,     0x01,     0x01,     0x01,     0x01,     0x01,     0x07,
+/* Opcode*/ 0x02,     0x07,     0x02,     0x02,     0x02,     0x02,     0x02,     0x00,
+/* Output*/ 0x04,     0x07,     0x07,     0x07,     0x07,     0x07,     0x07,     0x07,
+/* LFun  */ 0x00,     0x09,     0x00,     0x00,     0x00,     0x00,     0x00,     0x3F,
+// Wave 1
+/* LenBr */ 0x01,     0x3F,     0x01,     0x01,     0x01,     0x01,     0x01,     0x07,
+/* Opcode*/ 0x02,     0x07,     0x02,     0x02,     0x02,     0x02,     0x02,     0x00,
+/* Output*/ 0x00,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,
+/* LFun  */ 0x00,     0x09,     0x00,     0x00,     0x00,     0x00,     0x00,     0x3F,
+// Wave 2
+/* LenBr */ 0x01,     0xBF,     0x01,     0x01,     0x01,     0x01,     0x01,     0x07,
+/* Opcode*/ 0x06,     0x05,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,
+/* Output*/ 0x00,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,
+/* LFun  */ 0x00,     0x09,     0x00,     0x00,     0x00,     0x00,     0x00,     0x3F,
+// Wave 3
+/* LenBr */ 0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x07,
+/* Opcode*/ 0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,
+/* Output*/ 0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,
+/* LFun  */ 0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x3F,
+};
+/* END DO NOT EDIT */
+
+/* DO NOT EDIT ... */
+const char flowstates[36] = {
+/* Wave 0 flowstates */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* Wave 1 flowstates */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* Wave 2 flowstates */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* Wave 3 flowstates */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+/* END DO NOT EDIT */
+
+/* DO NOT EDIT ... */
+const char initdata[7] = {
+/* Regs  */ 0xE0, 0x00, 0x00, 0x03, 0xEE, 0xF1, 0x00
+};
+/* END DO NOT EDIT */
+
+void gpif_init(void)
+{
+	uint8_t i;
+
+	IFCONFIG = 0xEE;
+
+	GPIFABORT = 0xFF;	/* abort any waveforms pending */
+	GPIFREADYCFG = initdata[0];
+	GPIFCTLCFG = initdata[1];
+	GPIFIDLECS = initdata[2];
+	GPIFIDLECTL = initdata[3];
+	GPIFWFSELECT = initdata[5];
+	GPIFREADYSTAT = initdata[6];
+
+	/* use dual autopointer feature... */
+	AUTOPTRSETUP = 0x07;
+
+	/* source */
+	AUTOPTRH1 = (uint8_t)(((uint16_t)(&wavedata) >> 8) & 0xff);
+	AUTOPTRL1 = (uint8_t)((uint16_t)(&wavedata) & 0xff);
+
+	/* destination */
+	AUTOPTRH2 = 0xE4;
+	AUTOPTRL2 = 0x00;
+
+	/* transfer */
+	for (i = 0x00; i < 128; i++)
+		EXTAUTODAT2 = EXTAUTODAT1;
+
+	/* GPIF address pins update when GPIFADRH/L written */
+	syncdelay(3);
+	GPIFADRH = 0x00;    /* bits[7:1] always 0 */
+	syncdelay(3);
+	GPIFADRL = 0x00;    /* point to PERIPHERAL address 0x0000 */
+
+	/* Configure GPIF flowstates registers for Wave 0 of wavedata */
+	FLOWSTATE = flowstates[0];
+	FLOWLOGIC = flowstates[1];
+	FLOWEQ0CTL = flowstates[2];
+	FLOWEQ1CTL = flowstates[3];
+	FLOWHOLDOFF = flowstates[4];
+	FLOWSTB = flowstates[5];
+	FLOWSTBEDGE = flowstates[6];
+	FLOWSTBHPERIOD = flowstates[7];
+}

contrib/firmware/angie/c/src/i2c.c

@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/****************************************************************************
+	File : i2c.cpp                                                          *
+	Contents : i2c bit-bang library                                         *
+	Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.              *
+	<aboudjelida@nanoxplore.com>                                            *
+	<ahmederrachedbjld@gmail.com>											*
+*****************************************************************************/
+
+#include "i2c.h"
+#include "io.h"
+#include "delay.h"
+#include "reg_ezusb.h"
+
+bool get_status(void)
+{
+	PIN_SDA_DIR = 1;
+	OEA = 0xF7;
+	delay_us(1);
+	bool sda_state = PIN_SDA;
+	PIN_T0 = sda_state;
+	delay_us(1);
+	OEA = 0xFF;
+	delay_us(1);
+	return sda_state;
+}
+
+void start_cd(void)
+{
+	PIN_SDA_DIR = 0;    // SP6 SDA: OUT
+	delay_us(10);
+	PIN_SDA = 0;
+	delay_us(1);
+	PIN_SCL = 0;
+	delay_us(1);
+}
+
+void repeated_start(void)
+{
+	PIN_SDA = 1;
+	delay_us(1);
+	PIN_SCL = 1;
+	delay_us(1);
+	PIN_SDA = 0;
+	delay_us(1);
+	PIN_SCL = 0;
+	delay_us(1);
+}
+
+void stop_cd(void)
+{
+	PIN_SDA = 0;
+	delay_us(1);
+	PIN_SCL = 1;
+	delay_us(1);
+	PIN_SDA = 1;
+	delay_us(1);
+	PIN_SDA_DIR = 1;    // SP6 SDA: IN
+	delay_us(1);
+}
+
+void clock_cd(void)
+{
+	PIN_SCL = 1;
+	delay_us(1);
+	PIN_SCL = 0;
+	delay_us(1);
+}
+
+void send_ack(void)
+{
+	PIN_SDA = 0;
+	delay_us(1);
+	PIN_SCL = 1;
+	delay_us(1);
+	PIN_SCL = 0;
+	delay_us(1);
+}
+
+void send_nack(void)
+{
+	PIN_SDA = 1;
+	delay_us(1);
+	PIN_SCL = 1;
+	delay_us(1);
+	PIN_SCL = 0;
+	delay_us(1);
+}
+
+bool get_ack(void)
+{
+	PIN_SDA_DIR = 1;    // SP6 SDA: IN
+	delay_us(1);
+	OEA = 0xF7;         // FX2 SDA: IN
+	PIN_SCL = 1;
+	delay_us(1);
+	bool ack = PIN_SDA;
+	PIN_SCL = 0;
+	delay_us(1);
+	OEA = 0xFF;         // FX2 SDA: OUT
+	PIN_SDA_DIR = 0;    // SP6 SDA: OUT
+	delay_us(1);
+	return ack;
+}
+
+/* here address(8 bits) = adr (7 bits) + type (1 bit) */
+uint8_t get_address(uint8_t adr, uint8_t rdwr)
+{
+	adr &= 0x7F;
+	adr = adr << 1;
+	adr |= (rdwr & 0x01);
+	return adr;
+}
+
+/* here send bit after bit and clocking scl with each bit */
+void send_byte(uint8_t input)
+{
+	for (uint8_t i = 0; i < 8; i++) {
+		if ((input & 0x80)) {
+			PIN_SDA = 1;
+			delay_us(1);
+			clock_cd();
+		} else {
+			PIN_SDA = 0;
+			delay_us(1);
+			clock_cd();
+		}
+	input = input << 1;
+	}
+}
+
+/* here receive bit after bit and clocking scl with each bit */
+
+uint8_t receive_byte(void)
+{
+	PIN_SDA_DIR = 1;    // SP6 SDA: IN
+	OEA = 0xF7;         // FX2 SDA: IN
+	uint8_t input = 0x00;
+	for (uint8_t i = 0; i < 8; i++) {
+		PIN_SCL = 1;
+		delay_us(1);
+		input = input << 1;
+		if (PIN_SDA == 1)
+			input |= 0x01;
+		else
+			input |= 0X00;
+
+		PIN_SCL = 0;
+		delay_us(1);
+	}
+	OEA = 0xFF;         // FX2 SDA: OUT
+	PIN_SDA_DIR = 0;    // SP6 SDA: OUT
+	return input;
+}

contrib/firmware/angie/c/src/main.c

@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/****************************************************************************
+	File : main.c															*
+	Contents : main code for NanoXplore USB-JTAG ANGIE adapter				*
+	hardware.																*
+	Based on openULINK project code by: Martin Schmoelzer.					*
+	Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.				*
+	<aboudjelida@nanoxplore.com>											*
+	<ahmederrachedbjld@gmail.com>											*
+*****************************************************************************/
+
+#include "usb.h"
+#include "serial.h"
+#include "delay.h"
+#include "reg_ezusb.h"
+#include <stdio.h>
+
+extern void sudav_isr(void)__interrupt	SUDAV_ISR;
+extern void sof_isr(void)__interrupt;
+extern void sutok_isr(void)__interrupt;
+extern void suspend_isr(void)__interrupt;
+extern void usbreset_isr(void)__interrupt;
+extern void highspeed_isr(void)__interrupt;
+extern void ep0ack_isr(void)__interrupt;
+extern void stub_isr(void)__interrupt;
+extern void ep0in_isr(void)__interrupt;
+extern void ep0out_isr(void)__interrupt;
+extern void ep1in_isr(void)__interrupt;
+extern void ep1out_isr(void)__interrupt;
+extern void ep2_isr(void)__interrupt;
+extern void ep4_isr(void)__interrupt;
+extern void ep6_isr(void)__interrupt;
+extern void ep8_isr(void)__interrupt;
+extern void ibn_isr(void)__interrupt;
+extern void ep0pingnak_isr(void)__interrupt;
+extern void ep1pingnak_isr(void)__interrupt;
+extern void ep2pingnak_isr(void)__interrupt;
+extern void ep4pingnak_isr(void)__interrupt;
+extern void ep6pingnak_isr(void)__interrupt;
+extern void ep8pingnak_isr(void)__interrupt;
+extern void errorlimit_isr(void)__interrupt;
+extern void ep2piderror_isr(void)__interrupt;
+extern void ep4piderror_isr(void)__interrupt;
+extern void ep6piderror_isr(void)__interrupt;
+extern void ep8piderror_isr(void)__interrupt;
+extern void ep2pflag_isr(void)__interrupt;
+extern void ep4pflag_isr(void)__interrupt;
+extern void ep6pflag_isr(void)__interrupt;
+extern void ep8pflag_isr(void)__interrupt;
+extern void ep2eflag_isr(void)__interrupt;
+extern void ep4eflag_isr(void)__interrupt;
+extern void ep6eflag_isr(void)__interrupt;
+extern void ep8eflag_isr(void)__interrupt;
+extern void ep2fflag_isr(void)__interrupt;
+extern void ep4fflag_isr(void)__interrupt;
+extern void ep6fflag_isr(void)__interrupt;
+extern void ep8fflag_isr(void)__interrupt;
+extern void gpifcomplete_isr(void)__interrupt;
+extern void gpifwaveform_isr(void)__interrupt;
+
+void gpif_init(void);
+
+int main(void)
+{
+	CPUCS = ((CPUCS & ~bmclkspd) | (CLK_48M << 3) | CLKOE);	/* required for sio0_init */
+	sio0_init(115200);	/* needed for printf */
+
+	ep_init();
+	gpif_init();
+	interrupt_init();
+	io_init();
+
+	/* Perform ReNumeration */
+	USBCS |= (DISCON | RENUM);
+	delay_ms(50);
+	USBCS &= ~DISCON;
+
+	/* stay here */
+	while (1)
+		;
+}

contrib/firmware/angie/c/src/serial.c

@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: LGPL-2.1-or-later
+
+/*
+ * This code was taken from the fx2lib project from this link:
+ * https://github.com/djmuhlestein/fx2lib
+ *
+ * Copyright (C) 2009 Ubixum, Inc.
+*/
+
+#include <reg_ezusb.h>
+#include <fx2macros.h>
+#include <serial.h>
+#include <stdint.h>
+/**
+ * using the comp port implies that timer 2 will be used as
+ * a baud rate generator.  (Don't use timer 2)
+ **/
+void sio0_init(uint32_t baud_rate) __critical
+{
+	uint16_t hl;     /* hl value for reload */
+	uint8_t mult;   /* multiplier for clock speed */
+	uint32_t tmp;   /* scratch for mult/divide */
+
+	mult = (CPUFREQ == CLK_12M) ? 1 : ((CPUFREQ == CLK_24M) ? 2 : 4);
+
+	/* set the clock rate */
+	/* use clock 2 */
+	RCLK = 1; TCLK = 1;
+	tmp = mult * 375000L * 2;
+	tmp /= baud_rate;
+	tmp += 1;
+	tmp /= 2;
+	hl = 0xFFFF - (uint16_t)tmp;
+	RCAP2H = (uint8_t)(((uint16_t)(hl) >> 8) & 0xff);
+
+	/* seems that the 24/48mhz calculations are always one less than suggested values */
+  /* trm table 14-16 */
+	RCAP2L = ((uint8_t)((uint16_t)(hl) & 0xff)) + (mult > 0 ? 1 : 0);
+
+  /* start the timer */
+	TR2 = 1;
+
+	/* set up the serial port	*/
+	SM0 = 0; SM1 = 1; /* serial mode 1 (asyncronous)	*/
+	SM2 = 0 ;       /* has to do with receiving */
+	REN = 1 ;       /* to enable receiving */
+	PCON |= 0x80;    /* SET SMOD0, baud rate doubler */
+	TI = 1;         /* we send initial byte */
+}
+
+int getchar(void)
+{
+	char c;
+	while (!RI)
+		;
+	c = SBUF0;
+	RI = 0;
+	return c;
+}
+
+void _transchar(char c)
+{
+	while (!TI)
+		; /* wait for TI=1 */
+	TI = 0;
+	SBUF0 = c;
+}
+
+int putchar (char c)
+{
+	if (c == '\n')
+		_transchar('\r'); /* transmit \r\n */
+	_transchar(c);
+	if (c == '\r')
+		_transchar('\n'); /* transmit \r\n */
+	return c;
+}

contrib/firmware/angie/c/src/usb.c

@@ -0,0 +1,857 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/****************************************************************************
+	File : usb.c															*
+	Contents : usb communication handling code for NanoXplore USB-JTAG		*
+	ANGIE adapter hardware.													*
+	Based on openULINK project code by: Martin Schmoelzer.					*
+	Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.				*
+	<aboudjelida@nanoxplore.com>											*
+	<ahmederrachedbjld@gmail.com>											*
+*****************************************************************************/
+
+#include "usb.h"
+#include "delay.h"
+#include "io.h"
+#include "reg_ezusb.h"
+#include "fx2macros.h"
+#include "serial.h"
+#include "i2c.h"
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+// #define PRINTF_DEBUG
+
+volatile __xdata __at 0xE6B8 struct setup_data setup_data;
+
+/* Define number of endpoints (except Control Endpoint 0) in a central place.
+ * Be sure to include the necessary endpoint descriptors!
+ */
+#define NUM_ENDPOINTS 2
+
+__code struct usb_device_descriptor device_descriptor = {
+	.blength =				sizeof(struct usb_device_descriptor),
+	.bdescriptortype =		DESCRIPTOR_TYPE_DEVICE,
+	.bcdusb =				0x0200,	    /* BCD: 02.00 (Version 2.0 USB spec) */
+	.bdeviceclass =			0xEF,
+	.bdevicesubclass =		0x02,
+	.bdeviceprotocol =		0x01,
+	.bmaxpacketsize0 =		64,
+	.idvendor =				0x584e,
+	.idproduct =			0x414f,
+	.bcddevice =			0x0000,
+	.imanufacturer =		1,
+	.iproduct =				2,
+	.iserialnumber =		3,
+	.bnumconfigurations =	1
+};
+
+/* WARNING: ALL config, interface and endpoint descriptors MUST be adjacent! */
+__code struct usb_config_descriptor config_descriptor = {
+	.blength =				sizeof(struct usb_config_descriptor),
+	.bdescriptortype =		DESCRIPTOR_TYPE_CONFIGURATION,
+	.wtotallength =			sizeof(struct usb_config_descriptor) +
+							2 * sizeof(struct usb_interface_descriptor) +
+							((NUM_ENDPOINTS * 2) * sizeof(struct usb_endpoint_descriptor)),
+	.bnuminterfaces =		2,
+	.bconfigurationvalue =	1,
+	.iconfiguration =		2,	/* String describing this configuration */
+	.bmattributes =			0x80,	/* Only MSB set according to USB spec */
+	.maxpower =				50	/* 100 mA */
+};
+
+__code struct usb_interface_descriptor interface_descriptor00 = {
+	.blength =				sizeof(struct usb_interface_descriptor),
+	.bdescriptortype =		DESCRIPTOR_TYPE_INTERFACE,
+	.binterfacenumber =		0,
+	.balternatesetting =	0,
+	.bnumendpoints =		NUM_ENDPOINTS,
+	.binterfaceclass =		0XFF,
+	.binterfacesubclass =	0x00,
+	.binterfaceprotocol =	0x00,
+	.iinterface =			0
+};
+
+__code struct usb_endpoint_descriptor bulk_ep2_endpoint_descriptor = {
+	.blength =				sizeof(struct usb_endpoint_descriptor),
+	.bdescriptortype =		0x05,
+	.bendpointaddress =		(2 | USB_DIR_OUT),
+	.bmattributes =			0x02,
+	.wmaxpacketsize =		512,
+	.binterval =			0
+};
+
+__code struct usb_endpoint_descriptor bulk_ep4_endpoint_descriptor = {
+	.blength =				sizeof(struct usb_endpoint_descriptor),
+	.bdescriptortype =		0x05,
+	.bendpointaddress =		(4 | USB_DIR_IN),
+	.bmattributes =			0x02,
+	.wmaxpacketsize =		512,
+	.binterval =			0
+};
+
+__code struct usb_interface_descriptor interface_descriptor01 = {
+	.blength =				sizeof(struct usb_interface_descriptor),
+	.bdescriptortype =		DESCRIPTOR_TYPE_INTERFACE,
+	.binterfacenumber =		1,
+	.balternatesetting =	0,
+	.bnumendpoints =		NUM_ENDPOINTS,
+	.binterfaceclass =		0x0A,
+	.binterfacesubclass =	0x00,
+	.binterfaceprotocol =	0x00,
+	.iinterface =			0
+};
+
+__code struct usb_endpoint_descriptor bulk_ep6_out_endpoint_descriptor = {
+	.blength =				sizeof(struct usb_endpoint_descriptor),
+	.bdescriptortype =		0x05,
+	.bendpointaddress =		(6 | USB_DIR_OUT),
+	.bmattributes =			0x02,
+	.wmaxpacketsize =		512,
+	.binterval =			0
+};
+
+__code struct usb_endpoint_descriptor bulk_ep8_in_endpoint_descriptor = {
+	.blength =				sizeof(struct usb_endpoint_descriptor),
+	.bdescriptortype =		0x05,
+	.bendpointaddress =		(8 | USB_DIR_IN),
+	.bmattributes =			0x02,
+	.wmaxpacketsize =		512,
+	.binterval =			0
+};
+__code struct usb_language_descriptor language_descriptor = {
+	.blength =				4,
+	.bdescriptortype =		DESCRIPTOR_TYPE_STRING,
+	.wlangid =				0x0409 /* US English */
+};
+
+__code struct usb_string_descriptor strmanufacturer =
+	STR_DESCR(16, 'N', 'a', 'n', 'o', 'X', 'p', 'l', 'o', 'r', 'e', ',', ' ', 'S', 'A', 'S', '.');
+
+__code struct usb_string_descriptor strproduct =
+	STR_DESCR(13, 'A', 'N', 'G', 'I', 'E', ' ', 'A', 'd', 'a', 'p', 't', 'e', 'r');
+
+__code struct usb_string_descriptor strserialnumber =
+	STR_DESCR(6, '0', '0', '0', '0', '0', '1');
+
+/* Table containing pointers to string descriptors */
+__code struct usb_string_descriptor *__code en_string_descriptors[3] = {
+	&strmanufacturer,
+	&strproduct,
+	&strserialnumber
+};
+void sudav_isr(void)__interrupt SUDAV_ISR
+{
+	EXIF &= ~0x10;  /* Clear USBINT: Main global interrupt */
+	USBIRQ = SUDAVI;
+	EP0CS |= HSNAK;
+	usb_handle_setup_data();
+}
+void sof_isr(void)__interrupt	SOF_ISR
+{
+}
+void sutok_isr(void)__interrupt	SUTOK_ISR
+{
+}
+void suspend_isr(void)__interrupt	SUSPEND_ISR
+{
+}
+void usbreset_isr(void)__interrupt	USBRESET_ISR
+{
+}
+void highspeed_isr(void)__interrupt	HIGHSPEED_ISR
+{
+}
+void ep0ack_isr(void)__interrupt	EP0ACK_ISR
+{
+}
+void stub_isr(void)__interrupt	STUB_ISR
+{
+}
+void ep0in_isr(void)__interrupt	EP0IN_ISR
+{
+}
+void ep0out_isr(void)__interrupt	EP0OUT_ISR
+{
+}
+void ep1in_isr(void)__interrupt	EP1IN_ISR
+{
+}
+void ep1out_isr(void)__interrupt	EP1OUT_ISR
+{
+}
+void ep2_isr(void)__interrupt	EP2_ISR
+{
+}
+void ep4_isr(void)__interrupt	EP4_ISR
+{
+}
+void ep6_isr(void)__interrupt	EP6_ISR
+{
+	REVCTL = 0;     /* REVCTL.0 and REVCTL.1 set to 0 */
+	i2c_recieve();  /* Execute I2C communication */
+	EXIF &= ~0x10;  /* Clear USBINT: Main global interrupt */
+	EPIRQ = 0x40;	/* Clear individual EP6OUT IRQ */
+}
+void ep8_isr(void)__interrupt	EP8_ISR
+{
+	EXIF &= ~0x10;		/* Clear USBINT: Main global interrupt */
+	EPIRQ = 0x80;		/* Clear individual EP8IN IRQ */
+}
+void ibn_isr(void)__interrupt	IBN_ISR
+{
+}
+void ep0pingnak_isr(void)__interrupt	EP0PINGNAK_ISR
+{
+}
+void ep1pingnak_isr(void)__interrupt	EP1PINGNAK_ISR
+{
+}
+void ep2pingnak_isr(void)__interrupt	EP2PINGNAK_ISR
+{
+}
+void ep4pingnak_isr(void)__interrupt	EP4PINGNAK_ISR
+{
+}
+void ep6pingnak_isr(void)__interrupt	EP6PINGNAK_ISR
+{
+}
+void ep8pingnak_isr(void)__interrupt	EP8PINGNAK_ISR
+{
+}
+void errorlimit_isr(void)__interrupt	ERRORLIMIT_ISR
+{
+}
+void ep2piderror_isr(void)__interrupt	EP2PIDERROR_ISR
+{
+}
+void ep4piderror_isr(void)__interrupt	EP4PIDERROR_ISR
+{
+}
+void ep6piderror_isr(void)__interrupt	EP6PIDERROR_ISR
+{
+}
+void ep8piderror_isr(void)__interrupt	EP8PIDERROR_ISR
+{
+}
+void ep2pflag_isr(void)__interrupt	EP2PFLAG_ISR
+{
+}
+void ep4pflag_isr(void)__interrupt	EP4PFLAG_ISR
+{
+}
+void ep6pflag_isr(void)__interrupt	EP6PFLAG_ISR
+{
+}
+void ep8pflag_isr(void)__interrupt	EP8PFLAG_ISR
+{
+}
+void ep2eflag_isr(void)__interrupt	EP2EFLAG_ISR
+{
+}
+void ep4eflag_isr(void)__interrupt	EP4EFLAG_ISR
+{
+}
+void ep6eflag_isr(void)__interrupt	EP6EFLAG_ISR
+{
+}
+void ep8eflag_isr(void)__interrupt	EP8EFLAG_ISR
+{
+}
+void ep2fflag_isr(void)__interrupt	EP2FFLAG_ISR
+{
+}
+void ep4fflag_isr(void)__interrupt	EP4FFLAG_ISR
+{
+}
+void ep6fflag_isr(void)__interrupt	EP6FFLAG_ISR
+{
+}
+void ep8fflag_isr(void)__interrupt	EP8FFLAG_ISR
+{
+}
+void gpifcomplete_isr(void)__interrupt	GPIFCOMPLETE_ISR
+{
+}
+void gpifwaveform_isr(void)__interrupt	GPIFWAVEFORM_ISR
+{
+}
+
+/**
+ * Return the control/status register for an endpoint
+ *
+ * @param ep endpoint address
+ * @return on success: pointer to Control & Status register for endpoint
+ *  specified in \a ep
+ * @return on failure: NULL
+ */
+__xdata uint8_t *usb_get_endpoint_cs_reg(uint8_t ep)
+{
+	/* Mask direction bit */
+	uint8_t ep_num = ep & ~0x80;
+
+	switch (ep_num) {
+	case 0:
+		return	&EP0CS;
+	case 1:
+		return	ep & 0x80 ? &EP1INCS : &EP1OUTCS;
+	case 2:
+		return	&EP2CS;
+	case 4:
+		return	&EP4CS;
+	case 6:
+		return	&EP6CS;
+	case 8:
+		return	&EP8CS;
+	default:
+		return	NULL;
+	}
+}
+
+void usb_reset_data_toggle(uint8_t ep)
+{
+	/* TOGCTL register:
+		+----+-----+-----+------+-----+-------+-------+-------+
+		| Q  |  S  |  R  |  IO  |  EP3  |  EP2  |  EP1  |  EP0  |
+		+----+-----+-----+------+-----+-------+-------+-------+
+
+		To reset data toggle bits, we have to write the endpoint direction (IN/OUT)
+		to the IO bit and the endpoint number to the EP2..EP0 bits. Then, in a
+		separate write cycle, the R bit needs to be set.
+	*/
+	TOGCTL = (((ep & 0x80) >> 3) + (ep & 0x0F));
+	TOGCTL |= BMRESETTOGGLE;
+}
+
+/**
+ * Handle CLEAR_FEATURE request.
+ *
+ * @return on success: true
+ * @return on failure: false
+ */
+bool usb_handle_clear_feature(void)
+{
+	__xdata uint8_t *ep_cs;
+
+	switch (setup_data.bmrequesttype) {
+	case CF_DEVICE:
+		/* Clear remote wakeup not supported: stall EP0 */
+		STALL_EP0();
+		break;
+	case CF_ENDPOINT:
+		if (setup_data.wvalue == 0) {
+			/* Unstall the endpoint specified in wIndex */
+			ep_cs = usb_get_endpoint_cs_reg(setup_data.windex);
+			if (!ep_cs)
+				return false;
+			*ep_cs &= ~EPSTALL;
+		} else {
+			/* Unsupported feature, stall EP0 */
+			STALL_EP0();
+		}
+		break;
+	default:
+		/* Vendor commands... */
+		break;
+	}
+	return true;
+}
+
+/**
+ * Handle SET_FEATURE request.
+ *
+ * @return on success: true
+ * @return on failure: false
+ */
+bool usb_handle_set_feature(void)
+{
+	__xdata uint8_t *ep_cs;
+
+	switch (setup_data.bmrequesttype) {
+	case SF_DEVICE:
+		if (setup_data.wvalue == 2)
+			return true;
+		break;
+	case SF_ENDPOINT:
+		if (setup_data.wvalue == 0) {
+			/* Stall the endpoint specified in wIndex */
+			ep_cs = usb_get_endpoint_cs_reg(setup_data.windex);
+			if (!ep_cs)
+				return false;
+			*ep_cs |= EPSTALL;
+		} else {
+			/* Unsupported endpoint feature */
+			return false;
+		}
+		break;
+	default:
+		/* Vendor commands... */
+		break;
+	}
+
+	return true;
+}
+
+/**
+ * Handle GET_DESCRIPTOR request.
+ *
+ * @return on success: true
+ * @return on failure: false
+ */
+bool usb_handle_get_descriptor(void)
+{
+	__xdata uint8_t descriptor_type;
+	__xdata uint8_t descriptor_index;
+
+	descriptor_type = (setup_data.wvalue & 0xff00) >> 8;
+	descriptor_index = setup_data.wvalue & 0x00ff;
+
+	switch (descriptor_type) {
+	case DESCRIPTOR_TYPE_DEVICE:
+		SUDPTRH = HI8(&device_descriptor);
+		SUDPTRL = LO8(&device_descriptor);
+		break;
+	case DESCRIPTOR_TYPE_CONFIGURATION:
+		SUDPTRH = HI8(&config_descriptor);
+		SUDPTRL = LO8(&config_descriptor);
+		break;
+	case DESCRIPTOR_TYPE_STRING:
+		if (setup_data.windex == 0) {
+			/* Supply language descriptor */
+			__xdata struct usb_language_descriptor temp_descriptor;
+			memcpy(&temp_descriptor, &language_descriptor, sizeof(language_descriptor));
+			SUDPTRH = HI8(&temp_descriptor);
+			SUDPTRL = LO8(&temp_descriptor);
+		} else if (setup_data.windex == 0x0409 /* US English */) {
+			/* Supply string descriptor */
+			__xdata uint8_t temp_descriptors[3];
+			memcpy(temp_descriptors, en_string_descriptors[descriptor_index - 1],
+				   ((struct usb_string_descriptor *)en_string_descriptors[descriptor_index - 1])->blength);
+			SUDPTRH = HI8(temp_descriptors);
+			SUDPTRL = LO8(temp_descriptors);
+		} else {
+			return false;
+		}
+		break;
+	default:
+		/* Unsupported descriptor type */
+		return false;
+	}
+	return true;
+}
+
+/**
+ * Handle SET_INTERFACE request.
+ */
+void usb_handle_set_interface(void)
+{
+	/* Reset Data Toggle */
+	usb_reset_data_toggle(USB_DIR_OUT | 2);
+	usb_reset_data_toggle(USB_DIR_IN  | 4);
+	usb_reset_data_toggle(USB_DIR_OUT | 6);
+	usb_reset_data_toggle(USB_DIR_IN  | 8);
+
+	/* Unstall all valid OUT endpoints, reset bytecounts */
+	EP2CS = 0;
+	EP4CS = 0;
+	EP6CS = 0;
+	EP8CS = 0;
+	syncdelay(3);
+	EP2BCH = 0;
+	EP2BCL = 0x80;
+	syncdelay(3);
+	EP4BCH = 0;
+	EP4BCL = 0x80;
+	syncdelay(3);
+	EP6BCH = 0;
+	EP6BCL = 0x80;
+	syncdelay(3);
+	EP8BCH = 0;
+	EP8BCL = 0x80;
+	syncdelay(3);
+}
+
+/* Initialize GPIF interface transfer count */
+void set_gpif_cnt(uint32_t count)
+{
+	GPIFTCB3 = (uint8_t)(((uint32_t)(count) >> 24) & 0x000000ff);
+	syncdelay(3);
+	GPIFTCB2 = (uint8_t)(((uint32_t)(count) >> 16) & 0x000000ff);
+	syncdelay(3);
+	GPIFTCB1 = (uint8_t)(((uint32_t)(count) >> 8) & 0x000000ff);
+	syncdelay(3);
+	GPIFTCB0 = (uint8_t)((uint32_t)(count) & 0x000000ff);
+}
+
+/*
+ * Vendor commands handling:
+*/
+#define VR_CFGOPEN		0xB0
+#define VR_DATAOUTOPEN	0xB2
+
+uint8_t	ix;
+uint8_t bcnt;
+uint8_t __xdata *eptr;
+uint16_t wcnt;
+uint32_t __xdata gcnt;
+bool usb_handle_vcommands(void)
+{
+	eptr = EP0BUF;						/* points to EP0BUF 64-byte register */
+	wcnt = setup_data.wlength;			/* total transfer count */
+
+	/* Clear EP0BUF for OUT requests */
+	if (setup_data.bmrequesttype & 0x80) {
+		bcnt = ((wcnt > 64) ? 64 : wcnt);
+		for (ix = 0; ix < bcnt; ix++)
+			eptr[ix] = 0;
+	}
+
+	switch (setup_data.brequest) {
+	case VR_CFGOPEN:
+		/* Clear bytecount / to allow new data in / to stops NAKing */
+		EP0BCH = 0;
+		EP0BCL = 0;
+		while (EP0CS & EPBSY)
+			; /* wait to finish transferring in EP0BUF, until not busy */
+		gcnt  = ((uint32_t)(eptr[0]) << 24) | ((uint32_t)(eptr[1]) << 16)
+		| ((uint32_t)(eptr[2]) << 8) | (uint32_t)(eptr[3]);
+		/* Angie board FPGA bitstream download */
+		switch ((setup_data.wvalue) & 0x00C0) {
+		case 0x00:
+			/* Apply RPGM- pulse */
+			PIN_PROGRAM_B = 0;
+			syncdelay(1);
+			/* Negate RPGM- pulse */
+			PIN_PROGRAM_B = 1;
+			/* FPGA init time < 10mS */
+			delay_ms(10);
+			/* Initialize GPIF interface transfer count */
+			set_gpif_cnt(gcnt);
+			PIN_RDWR_B = 0;
+			PIN_SDA = 0;
+			/* Trigger GPIF OUT transfer on EP2 */
+			GPIFTRIG = GPIF_EP2;
+			while (!(GPIFTRIG & BMGPIFDONE)) // poll GPIFTRIG.7 GPIF Done bit
+				;
+			PIN_SDA = 1;
+			PIN_RDWR_B = 1;
+			#ifdef PRINTF_DEBUG
+			printf("Program SP6 Done.\n");
+			#endif
+			/* Choose wich Waveform to use */
+			GPIFWFSELECT = 0xF6;
+			break;
+		default:
+			break;
+		}
+		break;
+	case VR_DATAOUTOPEN:
+		/* Clear bytecount / to allow new data in / to stops NAKing */
+		EP0BCH = 0;
+		EP0BCL = 0;
+		while (EP0CS & EPBSY)
+			; /* wait to finish transferring in EP0BUF, until not busy */
+		gcnt  = ((uint32_t)(eptr[0]) << 24) | ((uint32_t)(eptr[1]) << 16)
+		| ((uint32_t)(eptr[2]) << 8) | (uint32_t)(eptr[3]);
+		/* REVCTL.0 and REVCTL.1 set to 1 */
+		REVCTL = 0x3;
+		/* Angie board FPGA bitstream download */
+		PIN_RDWR_B = 0;
+		/* Initialize GPIF interface transfer count */
+		GPIFTCB3 = (uint8_t)(((uint32_t)(gcnt) >> 24) & 0x000000ff);
+		GPIFTCB2 = (uint8_t)(((uint32_t)(gcnt) >> 16) & 0x000000ff);
+		GPIFTCB1 = (uint8_t)(((uint32_t)(gcnt) >> 8) & 0x000000ff);
+		GPIFTCB0 = (uint8_t)((uint32_t)(gcnt) & 0x000000ff);
+		/* Trigger GPIF OUT transfer on EP2 */
+		GPIFTRIG = GPIF_EP2;
+		while (!(GPIFTRIG & BMGPIFDONE)) // poll GPIFTRIG.7 GPIF Done bit
+			;
+		PIN_RDWR_B = 1;
+		/* Initialize GPIF interface transfer count */
+		GPIFTCB3 = (uint8_t)(((uint32_t)(gcnt) >> 24) & 0x000000ff);
+		GPIFTCB2 = (uint8_t)(((uint32_t)(gcnt) >> 16) & 0x000000ff);
+		GPIFTCB1 = (uint8_t)(((uint32_t)(gcnt) >> 8) & 0x000000ff);
+		GPIFTCB0 = (uint8_t)((uint32_t)(gcnt) & 0x000000ff);
+		/* Initialize AUTOIN transfer count */
+		EP4AUTOINLENH = (uint8_t)(((uint32_t)(gcnt) >> 8) & 0x000000ff);
+		EP4AUTOINLENL = (uint8_t)((uint32_t)(gcnt) & 0x000000ff);
+		/* Trigger GPIF IN transfer on EP4 */
+		GPIFTRIG = BMGPIFREAD | GPIF_EP4;
+		while (!(GPIFTRIG & BMGPIFDONE)) // poll GPIFTRIG.7 GPIF Done bit
+			;
+		/* REVCTL.0 and REVCTL.1 set to 0 */
+		REVCTL = 0;
+		break;
+	default:
+		return true;	/* Error: unknown VR command */
+	}
+	return false;		/* no error; command handled OK */
+}
+
+/**
+ * Handle the arrival of a USB Control Setup Packet.
+ */
+void usb_handle_setup_data(void)
+{
+	switch (setup_data.brequest) {
+	case GET_STATUS:
+		EP0BUF[0] = 0;
+		EP0BUF[1] = 0;
+		/* Send response */
+		EP0BCH = 0;
+		EP0BCL = 2;
+		syncdelay(3);
+		break;
+	case CLEAR_FEATURE:
+		if (!usb_handle_clear_feature())
+			STALL_EP0();
+		break;
+	case 2: case 4:
+		/* Reserved values */
+		STALL_EP0();
+		break;
+	case SET_FEATURE:
+		if (!usb_handle_set_feature())
+			STALL_EP0();
+		break;
+	case SET_ADDRESS:
+		/* Handled by USB core */
+		break;
+	case SET_DESCRIPTOR:
+		/* Set Descriptor not supported. */
+		STALL_EP0();
+		break;
+	case GET_DESCRIPTOR:
+		if (!usb_handle_get_descriptor())
+			STALL_EP0();
+		break;
+	case GET_CONFIGURATION:
+		/* ANGIE has only one configuration, return its index */
+		EP0BUF[0] = config_descriptor.bconfigurationvalue;
+		EP0BCH = 0;
+		EP0BCL = 1;
+		syncdelay(3);
+		break;
+	case SET_CONFIGURATION:
+		/* ANGIE has only one configuration -> nothing to do */
+		break;
+	case GET_INTERFACE:
+		/* ANGIE only has one interface, return its number */
+		EP0BUF[0] = interface_descriptor00.binterfacenumber;
+		EP0BUF[1] = interface_descriptor01.binterfacenumber;
+		EP0BCH = 0;
+		EP0BCL = 2;
+		syncdelay(3);
+		break;
+	case SET_INTERFACE:
+		usb_handle_set_interface();
+		break;
+	case SYNCH_FRAME:
+		/* Isochronous endpoints not used -> nothing to do */
+		break;
+	default:
+		/* if not Vendor command, Stall EndPoint 0 */
+		if (usb_handle_vcommands())
+			STALL_EP0();
+		break;
+	}
+}
+
+/**
+ * Handle the initialization of endpoints.
+ */
+void ep_init(void)
+{
+	EP1INCFG = 0x00;  /* non VALID */
+	syncdelay(3);
+	EP1OUTCFG = 0x00;  /* non VALID */
+	syncdelay(3);
+
+	/* JTAG */
+	EP2CFG = 0xA2;  /* VALID | OUT | BULK | 512 Bytes | Double buffer */
+	syncdelay(3);
+	EP4CFG = 0xE2;  /* VALID | IN | BULK | 512 Bytes | Double buffer */
+	syncdelay(3);
+
+	/* I2C */
+	EP6CFG = 0xA2;  /* VALID | OUT | BULK | 512 Bytes | Double buffer */
+	syncdelay(3);
+	EP8CFG = 0xE2;  /* VALID | IN | BULK | 512 Bytes | Double buffer */
+	syncdelay(3);
+
+	/* arm EP6-OUT */
+	EP6BCL = 0x80;
+	syncdelay(3);
+	EP6BCL = 0x80;
+	syncdelay(3);
+
+	/* REVCTL.0 and REVCTL.1 set to 1 */
+	REVCTL = 0x3;
+	/* Arm both EP2 buffers to “prime the pump” */
+	OUTPKTEND = 0x82;
+	syncdelay(3);
+	OUTPKTEND = 0x82;
+	syncdelay(3);
+
+	/* Standard procedure to reset FIFOs */
+	FIFORESET = BMNAKALL;	/* NAK all transfers during the reset */
+	syncdelay(3);
+	FIFORESET = BMNAKALL | 0x02;		/* reset EP2 FIFO */
+	syncdelay(3);
+	FIFORESET = BMNAKALL | 0x04;		/* reset EP4 FIFO */
+	syncdelay(3);
+	FIFORESET = 0x00;		/* deactivate the NAK all */
+	syncdelay(3);
+
+	/* configure EP2 in AUTO mode with 8-bit interface */
+	EP2FIFOCFG = 0x00;
+	syncdelay(3);
+	EP2FIFOCFG = BMAUTOOUT;	/* 8-bit Auto OUT mode */
+	syncdelay(3);
+	EP4FIFOCFG = BMAUTOIN | BMZEROLENIN;	/* 8-bit Auto IN mode */
+	syncdelay(3);
+}
+
+void i2c_recieve(void)
+{
+	if (EP6FIFOBUF[0] == 1) {
+		uint8_t rdwr = EP6FIFOBUF[0];   //read: 1
+		uint8_t reg_byte_check = EP6FIFOBUF[1]; //register given: 1 else: 0
+		uint8_t count = EP6FIFOBUF[2];  //requested data count
+		uint8_t adr = EP6FIFOBUF[3];    //address
+		uint8_t address = get_address(adr, rdwr);   //address byte (read command)
+		uint8_t address_2 = get_address(adr, 0);   //address byte 2 (write command)
+
+		/* i2c bus state byte */
+		EP8FIFOBUF[0] = get_status();
+
+		/*  start:   */
+		start_cd();
+		/*  address:   */
+		send_byte(address_2);   //write
+		/*  ack:  */
+		uint8_t ack = get_ack();
+
+		/*   send data   */
+		for (int i = 0; i < reg_byte_check; i++) {
+			send_byte(EP6FIFOBUF[i + 4]);
+			/*  ack():  */
+			ack = get_ack();
+		}
+
+		/*  repeated start:  */
+		repeated_start();
+		/*  address:   */
+		send_byte(address);
+		/*  get ack:  */
+		ack = get_ack();
+
+		/*   receive data   */
+		for (int i = 1; i < count; i++) {
+			EP8FIFOBUF[i] = receive_byte();
+
+			/*  send ack: */
+			send_ack();
+		}
+
+		EP8FIFOBUF[count] = receive_byte();
+
+		/*  send Nack:  */
+		send_nack();
+
+		/*   stop   */
+		stop_cd();
+
+		EP8BCH = (count + 1) >> 8; //EP8
+		syncdelay(3);
+		EP8BCL = count + 1; //EP8
+
+		EP6BCL = 0x80; //EP6
+		syncdelay(3);
+		EP6BCL = 0x80; //EP6
+	} else {
+		uint8_t rdwr = EP6FIFOBUF[0];   //write: 0
+		uint8_t count = EP6FIFOBUF[1];  //data count
+		uint8_t adr = EP6FIFOBUF[2];    //address
+		uint8_t address = get_address(adr, rdwr);   //address byte (read command)
+		uint8_t ack_cnt = 0;
+
+		// i2c bus state byte
+		EP8FIFOBUF[0] = get_status();
+
+		/*  start():   */
+		start_cd();
+		/*  address:   */
+		send_byte(address);   //write
+		/*  ack():  */
+		if (!get_ack())
+			ack_cnt++;
+		/*   send data  */
+		for (int i = 0; i < count; i++) {
+			send_byte(EP6FIFOBUF[i + 3]);
+			/*  get ack:  */
+			if (!get_ack())
+				ack_cnt++;
+		}
+
+		/*   stop   */
+		stop_cd();
+
+		EP8FIFOBUF[1] = ack_cnt;
+
+		EP8BCH = 0; //EP8
+		syncdelay(3);
+		EP8BCL = 2; //EP8
+
+		EP6BCL = 0x80; //EP6
+		syncdelay(3);
+		EP6BCL = 0x80; //EP6
+	}
+}
+
+/**
+ * Interrupt initialization. Configures USB interrupts.
+ **/
+void interrupt_init(void)
+{
+	/* Enable USB interrupt (EIE register) */
+	EUSB = 1;
+	EICON |= 0x20;
+
+	/* Enable INT 2 & 4 Autovectoring */
+	INTSETUP |= (AV2EN | AV4EN);
+
+	/* Enable individual EP6&8 interrupts */
+	EPIE |= 0xC0;
+
+	/* Clear individual USB interrupt IRQ */
+	EPIRQ = 0xC0;
+
+	/* Enable SUDAV interrupt */
+	USBIEN |= SUDAVI;
+
+	/* Clear SUDAV interrupt */
+	USBIRQ = SUDAVI;
+
+	/* Enable Interrupts (Do not confuse this with
+	 * EA External Access pin, see ANGIE Schematic)
+	 */
+	EA = 1;
+}
+
+/**
+ * Handle the initialization of io ports.
+ */
+void io_init(void)
+{
+	/* PORT A */
+	PORTACFG = 0x0;	/* 0: normal ou 1: alternate function (each bit) */
+	OEA = 0xEF;
+	IOA = 0xFF;
+
+	/* PORT C */
+	PORTCCFG = 0x0;	/* 0: normal ou 1: alternate function (each bit) */
+	OEC = 0xFF;
+	IOC = 0xFF;
+}

contrib/firmware/angie/hdl/Makefile

@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2023 by NanoXplore, France - all rights reserved
+
+# Needed by timing test
+export PROJECT := angie_bitstream
+TARGET_PART := xc6slx9-2tqg144
+export TOPLEVEL := S609
+
+# Detects the ROOT dir from the .git marker
+sp :=
+sp +=
+_walk = $(if $1,$(wildcard /$(subst $(sp),/,$1)/$2) $(call _walk,$(wordlist 2,$(words $1),x $1),$2))
+_find = $(firstword $(call _walk,$(strip $(subst /, ,$1)),$2))
+_ROOT := $(patsubst %/.git,%,$(call _find,$(CURDIR),.git))
+
+SHELL := /bin/bash
+TOP_DIR := $(realpath $(_ROOT))
+HDL_DIR := $(CURDIR)
+SRC_DIR := $(HDL_DIR)/src
+TOOLS_DIR := $(TOP_DIR)/tools/build
+COMMON_DIR := $(TOP_DIR)/common/hdl
+COMMON_HDL_DIR := $(COMMON_DIR)/src
+COMMON_LIBS := $(COMMON_DIR)/libs
+HDL_BUILD_DIR := $(HDL_DIR)/build
+OUTPUT_DIR ?= $(HDL_BUILD_DIR)/output
+FINAL_OUTPUT_DIR := $(OUTPUT_DIR)/$(PROJECT)
+
+# Tools
+MKDIR := mkdir -p
+CP := cp -f
+
+HDL_SRC_PATH := $(addprefix $(COMMON_DIR)/ips/, $(HDL_IPS)) $(HDL_DIR)
+VHDSOURCE += $(foreach ip,$(HDL_SRC_PATH),$(wildcard $(ip)/src/*.vhd))
+VSOURCE += $(foreach ip,$(HDL_SRC_PATH),$(wildcard $(ip)/src/*.v))
+VSOURCE += $(foreach ip,$(HDL_SRC_PATH),$(wildcard $(ip)/src/*.vh))
+
+CONSTRAINTS ?= $(SRC_DIR)/$(PROJECT).ucf
+
+COMMON_OPTS := -intstyle xflow
+XST_OPTS :=
+NGDBUILD_OPTS :=
+MAP_OPTS := -mt 2
+PAR_OPTS := -mt 4
+BITGEN_OPTS := -g Binary:Yes
+
+XILINX_PLATFORM := lin64
+PATH := $(PATH):$(XILINX_HOME)/bin/$(XILINX_PLATFORM)
+
+RUN = @echo -ne "\n\n\e[1;33m======== $(1) ========\e[m\n\n"; \
+	cd $(HDL_BUILD_DIR) && $(XILINX_HOME)/bin/$(XILINX_PLATFORM)/$(1)
+
+compile: $(HDL_BUILD_DIR)/$(PROJECT).bin
+
+install: $(HDL_BUILD_DIR)/$(PROJECT).bin
+	$(MKDIR) $(FINAL_OUTPUT_DIR)
+	$(CP) $(HDL_BUILD_DIR)/$(PROJECT).bin $(FINAL_OUTPUT_DIR)
+
+clean:
+	rm -rf $(HDL_BUILD_DIR)
+
+$(HDL_BUILD_DIR)/$(PROJECT).bin: $(HDL_BUILD_DIR)/$(PROJECT).ncd
+	$(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \
+	-w $(PROJECT).ncd $(PROJECT).bit
+
+$(HDL_BUILD_DIR)/$(PROJECT).ncd: $(HDL_BUILD_DIR)/$(PROJECT).map.ncd
+	$(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \
+		-w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf
+
+$(HDL_BUILD_DIR)/$(PROJECT).map.ncd: $(HDL_BUILD_DIR)/$(PROJECT).ngd
+	$(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \
+		-p $(TARGET_PART) \
+		-w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf
+
+$(HDL_BUILD_DIR)/$(PROJECT).ngd: $(HDL_BUILD_DIR)/$(PROJECT).ngc
+	$(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \
+		-p $(TARGET_PART) -uc $(CONSTRAINTS) \
+		$(PROJECT).ngc $(PROJECT).ngd
+
+$(HDL_BUILD_DIR)/$(PROJECT).ngc: $(HDL_BUILD_DIR)/$(PROJECT).prj $(HDL_BUILD_DIR)/$(PROJECT).scr
+	$(call RUN,xst) $(COMMON_OPTS) -ifn $(PROJECT).scr
+
+$(HDL_BUILD_DIR)/$(PROJECT).scr: | $(HDL_BUILD_DIR)
+	@echo "Updating $@"
+	@mkdir -p $(HDL_BUILD_DIR)
+	@rm -f $@
+	@echo "run" \
+	    "-ifn $(PROJECT).prj" \
+	    "-ofn $(PROJECT).ngc" \
+	    "-ifmt mixed" \
+	    "$(XST_OPTS)" \
+	    "-top $(TOPLEVEL)" \
+	    "-ofmt NGC" \
+	    "-p $(TARGET_PART)" \
+	> $(HDL_BUILD_DIR)/$(PROJECT).scr
+
+$(HDL_BUILD_DIR)/$(PROJECT).prj: | $(HDL_BUILD_DIR)
+	@echo "Updating $@"
+	@rm -f $@
+	@$(foreach file,$(VSOURCE),echo "verilog work \"$(file)\"" >> $@;)
+	@$(foreach file,$(VHDSOURCE),echo "vhdl work \"$(file)\"" >> $@;)
+	@$(foreach lib,$(HDL_LIBS),$(foreach file,$(wildcard $(COMMON_LIBS)/$(lib)/src/*.vhd),echo "vhdl $(lib) \"$(file)\"" >> $@;))
+	@$(foreach lib,$(HDL_LIBS),$(foreach file,$(wildcard $(COMMON_LIBS)/$(lib)/src/*.v),echo "verilog $(lib) \"$(file)\"" >> $@;))
+	@$(foreach lib,$(HDL_LIBS),$(foreach file,$(wildcard $(COMMON_LIBS)/$(lib)/src/*.vh),echo "verilog $(lib) \"$(file)\"" >> $@;))
+
+$(HDL_BUILD_DIR):
+	$(MKDIR) $(HDL_BUILD_DIR)
+
+.PHONY: clean compile install
+

contrib/firmware/angie/hdl/README

@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2023 by NanoXplore, France - all rights reserved
+
+This is the source code of Nanoxplore USB-JTAG Adapter Angie's bitstream.
+This bitstream is for the "xc6slx9-2tqg144" Spartan-6 Xilinx FPGA.
+
+To generate this bitstream, you need to install Xilinx ISE Webpack 14.7
+You will need to give the ISE software path : export XILINX_HOME=path/to/ise/sw
+Please set the enviromnent first by executing the ". ./set_env.sh"
+
+All you have to do now is to write your vhd and constrains codes.
+
+One all is setup, you can use the make commands:
+    make compile : to compile your (.vhd & .ucf) files in the "src" directory
+    A directory named "build" will be created, which contains all the generated
+    files including the bitstream file.
+
+    make clean : to delete the build directory.

contrib/firmware/angie/hdl/set_env.sh

@@ -0,0 +1,14 @@
+#!/bin/bash
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2023 by NanoXplore, France - all rights reserved
+
+[ -z "${XILINX_HOME}" ] && export XILINX_HOME=/home/software/Xilinx/ISE/14.7/ISE_DS/ISE
+export PATH="$XILINX_HOME:$PATH"
+echo "SET XILINX_HOME to ${XILINX_HOME}"
+# This is needed for isim
+XILINX_HOME_BASE=${XILINX_HOME}/..
+for part in common EDK PlanAhead ISE
+do
+	el=${XILINX_HOME_BASE}/${part}
+	.  ${el}/.settings64.sh ${el}
+done

contrib/firmware/angie/hdl/src/angie_bitstream.ucf

@@ -0,0 +1,74 @@
+## SPDX-License-Identifier: BSD-3-Clause
+##--------------------------------------------------------------------------
+## Project Context: nanoXplore USB to JTAG/I2C Adapter Board, Spartan6
+## Design Name:     ANGIE USB to JTAG/I2C Adapter FPGA source code
+## Module Name:     angie_bitstream.ucf
+## Target Device:   XC6SLX9-2 TQ144
+## Tool versions:   ISE Webpack 13.2 -> 14.2
+## Author:          Ahmed BOUDJELIDA    nanoXplore SAS
+##--------------------------------------------------------------------------
+# WARNING: PullUps on JTAG inputs should be enabled after configuration
+# (bitgen option) since the pins are not connected.
+
+CONFIG VCCAUX = "3.3";
+
+# Timing
+# net IH24        period = 40; # Constrain at 25MHz
+# net IH40        period = 25; # Constrain at 40MHz
+# DCMs placement on Spartan6
+# INST S6MOD_CKMUL.H48_DCM    LOC = DCM0;
+
+# Clock 48MHz
+net IFCLK_I            LOC = 'P123' ;
+
+net GD_IO<0> 	     LOC = 'P48' ;
+net GD_IO<1>		 LOC = 'P43' ;
+net GD_IO<2>         LOC = 'P44' ;
+net GD_IO<3>		 LOC = 'P45' ;
+net GD_IO<4>         LOC = 'P46' ;
+net GD_IO<5>         LOC = 'P61' ;
+net GD_IO<6>         LOC = 'P62' ;
+net GD_IO<7>         LOC = 'P65' ;
+
+net PA2_I            LOC = 'P47' ;
+#net PA3_I            LOC = 'P64' ;
+net JPW_I            LOC = 'P14' ;
+
+net GCTL0_I          LOC = 'P70' ;
+#net GCTL1_I          LOC = 'P55' ;
+#net GCTL2_I          LOC = 'P67' ;
+net GRDY1_I          LOC = 'P118' ;
+
+#net SDA_IO		     LOC = 'P50' ;
+net SDA_IO		    LOC = 'P64' ; #PA3
+#net SCL_I           LOC = 'P51' ;
+net SCL_I           LOC = 'P39' ; #PA4 switch
+net SDA_DIR_I	    LOC = 'P66' ; #PA0 switch
+#net SCL_DIR_I	     LOC = 'P57' ;
+
+net SO_SDA_OUT_O	LOC = 'P140' ;
+net SO_SDA_IN_I	    LOC = 'P1' ;
+net SO_SCL_O	    LOC = 'P137' ;
+
+net SO_TRST_O	    LOC = 'P32' ;
+net SO_TMS_O	    LOC = 'P27' ;
+net SO_TCK_O        LOC = 'P30' ;
+net SO_TDI_O        LOC = 'P26' ;
+net SO_SRST_O       LOC = 'P12' ;
+net SI_TDO_I        LOC = 'P16' ;
+
+net ST_0_O	        LOC = 'P29' ;
+net ST_1_O	        LOC = 'P21' ;
+net ST_2_O	        LOC = 'P11' ;
+net ST_3_O	        LOC = 'P7' ;
+net ST_4_O	        LOC = 'P134' ;
+net ST_5_O	        LOC = 'P139' ;
+
+net FTP_O<0>	    LOC = 'P121' ;
+net FTP_O<1>	    LOC = 'P120' ;
+net FTP_O<2>	    LOC = 'P119' ;
+net FTP_O<3>	    LOC = 'P116' ;
+net FTP_O<4>	    LOC = 'P111' ;
+net FTP_O<5>	    LOC = 'P112' ;
+net FTP_O<6>	    LOC = 'P115' ;
+net FTP_O<7>	    LOC = 'P114' ;

contrib/firmware/angie/hdl/src/angie_bitstream.vhd

@@ -0,0 +1,415 @@
+-- SPDX-License-Identifier: BSD-3-Clause
+----------------------------------------------------------------------------
+-- Project Context: nanoXplore USB to JTAG/I2C Adapter Board, Spartan6
+-- Design Name:     ANGIE USB to JTAG/I2C Adapter FPGA source code
+-- Module Name:     angie_bitstream.vhd
+-- Target Device:   XC6SLX9-2 TQ144
+-- Tool versions:   ISE Webpack 13.2 -> 14.2
+-- Author:          Ahmed BOUDJELIDA    nanoXplore SAS
+----------------------------------------------------------------------------
+library work;
+use work.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity angie_bitstream is port(
+  SDA_IO : inout std_logic;
+  SDA_DIR_I : in std_logic;
+  SCL_I : in std_logic;
+
+  JPW_I : in std_logic;     --Devkit power
+
+  SO_SDA_OUT_O : out std_logic;
+  SO_SDA_IN_I : in std_logic;
+  SO_SCL_O : out std_logic;
+
+  ST_0_O : out std_logic;
+  ST_1_O : out std_logic;
+  ST_2_O : out std_logic;
+  ST_3_O : out std_logic;
+  ST_4_O : out std_logic;
+  ST_5_O : out std_logic;
+
+  SO_TRST_O : out std_logic;
+  SO_TMS_O : out std_logic;
+  SO_TCK_O : out std_logic;
+  SO_TDI_O : out std_logic;
+  SO_SRST_O : out std_logic;
+  SI_TDO_I : in std_logic;
+
+  PA2_I : in std_logic; -- GPIF IN
+
+  -- Clock 48MHz
+  IFCLK_I : in std_logic;
+
+  GCTL0_I : in std_logic;
+  GRDY1_I : out std_logic;
+  GD_IO : inout std_logic_vector(7 downto 0);
+  FTP_O : out std_logic_vector(15 downto 0)
+);
+end angie_bitstream;
+
+architecture A_angie_bitstream of angie_bitstream is
+----------------------------------------Fifo out (PC to devkit)
+signal rst_o, clk_wr_o, clk_rd_o : std_logic;
+signal write_en_o, read_en_o : std_logic;
+signal data_in_o, data_out_o : std_logic_vector(7 downto 0);
+signal empty_o, full_o : std_logic;
+
+----------------------------------------Fifo in (devkit to PC)
+signal rst_i, clk_wr_i, clk_rd_i : std_logic;
+signal write_en_i, read_en_i : std_logic;
+signal data_in_i, data_out_i : std_logic_vector(7 downto 0);
+signal empty_i, full_i : std_logic;
+
+signal wr_o, rd_i : std_logic;
+
+----------------------------------------MAE
+signal transit1, transit2 : std_logic;
+
+----------------------------------------DFF
+signal pa2_dff_clk, pa2_dff_rst, pa2_dff_d, pa2_dff_q : std_logic;
+signal trst_clk, trst_rst, trst_d, trst_q : std_logic;
+signal tms_clk, tms_rst, tms_d, tms_q : std_logic;
+signal tdi_clk, tdi_rst, tdi_d, tdi_q : std_logic;
+signal tdo_clk, tdo_rst, tdo_d, tdo_q : std_logic;
+
+----------------------------------------clk_div
+signal clk_div_in, clk_div_out, reset_clk_div : std_logic;
+signal clk_div2_in, clk_div2_out, reset_clk_div2 : std_logic;
+
+----------------------------------------MAE
+type State_Type is (IDLE, WRITE_OUT, WRITE_IN, DELAY, READ_IN);
+signal state, state2 : State_Type;
+signal reset_mae, reset_mae2 : std_logic;
+
+-- Add Component DFF
+component DFF
+    Port (
+        clk : in std_logic;
+        reset : in std_logic;
+        d : in std_logic;
+        q : out std_logic
+    );
+end component;
+
+-- Add Component Clk_div
+component clk_div
+Port (
+    clk_in : in std_logic;
+    reset : in std_logic;
+    clk_out : out std_logic
+);
+end component;
+
+-- Add component FIFO 64B
+component fifo_generator_v9_3
+PORT (
+    rst : IN STD_LOGIC;
+    wr_clk : IN STD_LOGIC;
+    rd_clk : IN STD_LOGIC;
+    din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    wr_en : IN STD_LOGIC;
+    rd_en : IN STD_LOGIC;
+    dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    full : OUT STD_LOGIC;
+    empty : OUT STD_LOGIC
+  );
+end component;
+
+signal state1_debug, state2_debug : std_logic;
+
+begin
+-------------------------------------------------------------I2C :
+SDA_IO <= not(SO_SDA_IN_I) when (SDA_DIR_I = '1') else 'Z';
+SO_SDA_OUT_O <= SDA_IO;
+ST_5_O <= SDA_DIR_I;
+
+SO_SCL_O <= SCL_I when (JPW_I = '1') else '0';
+ST_4_O <= '0';
+
+------------------------------------------------------------JTAG :
+-- Instantiate the Clk div by 10
+clk_div_inst : clk_div
+port map (
+    clk_in => clk_div_in,
+    reset => reset_clk_div,
+    clk_out => clk_div_out
+);
+-- Instantiate the Clk div by 10
+clk_div2_inst : clk_div
+port map (
+    clk_in => clk_div2_in,
+    reset => reset_clk_div2,
+    clk_out => clk_div2_out
+);
+
+-- Instantiate DFFs
+DFF_inst_PA2 : DFF
+port map (
+   clk => pa2_dff_clk,
+   reset => pa2_dff_rst,
+   d => pa2_dff_d,
+   q => pa2_dff_q
+);
+
+DFF_inst_TRST : DFF
+port map (
+   clk => trst_clk,
+   reset => trst_rst,
+   d => trst_d,
+   q => trst_q
+);
+
+DFF_inst_TMS : DFF
+port map (
+   clk => tms_clk,
+   reset => tms_rst,
+   d => tms_d,
+   q => tms_q
+);
+
+DFF_inst_TDI : DFF
+port map (
+   clk => tdi_clk,
+   reset => tdi_rst,
+   d => tdi_d,
+   q => tdi_q
+);
+
+DFF_inst_TDO : DFF
+port map (
+   clk => tdo_clk,
+   reset => tdo_rst,
+   d => tdo_d,
+   q => tdo_q
+);
+
+-- Instantiate the FIFO OUT
+U0 : fifo_generator_v9_3
+port map (
+    rst => rst_o,
+    wr_clk => clk_wr_o,
+    rd_clk => clk_rd_o,
+    din => data_in_o,
+    wr_en => write_en_o,
+    rd_en => read_en_o,
+    dout => data_out_o,
+    full => full_o,
+    empty => empty_o
+);
+-- Instantiate the FIFO IN
+U1 : fifo_generator_v9_3
+port map (
+    rst => rst_i,
+    wr_clk => clk_wr_i,
+    rd_clk => clk_rd_i,
+    din => data_in_i,
+    wr_en => write_en_i,
+    rd_en => read_en_i,
+    dout => data_out_i,
+    full => full_i,
+    empty => empty_i
+);
+
+--------------- clock dividers
+clk_div_in <= IFCLK_I;          -- 48Mhz
+clk_div2_in <= clk_div_out;     -- 24Mhz
+
+--------------- DFFs
+pa2_dff_clk <= IFCLK_I;
+trst_clk <= IFCLK_I;
+tms_clk <= IFCLK_I;
+tdi_clk <= IFCLK_I;
+tdo_clk <= IFCLK_I;
+
+--------------- FIFOs
+clk_wr_o <= IFCLK_I;
+clk_rd_o <= clk_div2_out;
+clk_wr_i <= clk_div2_out;
+clk_rd_i <= IFCLK_I;
+
+--------------------------- GPIF ready :
+GRDY1_I <= '1';
+
+-------------------------------PA2 DFF :
+pa2_dff_rst <= '0';
+pa2_dff_d <= PA2_I;
+
+-------------------- FX2<->Fifo Enable pins :
+write_en_o <= not(wr_o) and not(GCTL0_I);
+read_en_i <= not(rd_i) and not(GCTL0_I);
+
+---------------- FX2->Fifo Data :
+data_in_o <= GD_IO;
+
+------------ FIFO_OUT->Devkit :
+SO_TRST_O <= trst_q;
+trst_d <= data_out_o(4);
+SO_TMS_O <= tms_q;
+tms_d <= data_out_o(3);
+SO_TDI_O <= tdi_q;
+tdi_d <= data_out_o(1);
+------------
+SO_TCK_O <= data_out_o(0);
+
+-------------------- FIFO_OUT->FIFO_IN :
+--data_in_i <= data_out_o;
+
+-------------------- FIFO_IN<-Devkit :
+data_in_i(0) <= '0';
+data_in_i(1) <= '0';
+data_in_i(2) <= tdo_q;
+tdo_d <= not SI_TDO_I;
+data_in_i(3) <= '0';
+data_in_i(4) <= '0';
+data_in_i(5) <= '0';
+data_in_i(6) <= '0';
+data_in_i(7) <= '0';
+
+-------------------- FX2<-FIFO_IN :
+GD_IO <= data_out_i when (state = READ_IN) else "ZZZZZZZZ";
+
+state1_debug <= '1' when state = READ_IN else '0';
+state2_debug <= '1' when state2 = WRITE_IN else '0';
+
+--Points de test:
+FTP_O(0) <= IFCLK_I;
+FTP_O(1) <= GCTL0_I;
+FTP_O(2) <= GD_IO(0);
+FTP_O(3) <= GD_IO(1);
+FTP_O(4) <= JPW_I;
+FTP_O(5) <= PA2_I;
+FTP_O(6) <= empty_o;
+FTP_O(7) <= not SI_TDO_I;
+
+process(pa2_dff_d, pa2_dff_q)
+begin
+    if pa2_dff_d = '0' and pa2_dff_q = '1' then
+        reset_mae <= '1';   -- Reset State Machine
+        reset_mae2 <= '1';   -- Reset State Machine
+        rst_o <= '1';   -- Reset OUT
+        rst_i <= '1';   -- Reset IN
+        reset_clk_div <= '1';
+        reset_clk_div2 <= '1';
+        trst_rst <= '1';
+        tms_rst <= '1';
+        tdi_rst <= '1';
+        tdo_rst <= '1';
+    else
+        reset_mae <= '0';   -- No Reset State Machine
+        reset_mae2 <= '0';   -- Reset State Machine
+        rst_o <= '0';   -- No Reset OUT
+        rst_i <= '0';   -- No Reset IN
+        reset_clk_div <= '0';
+        reset_clk_div2 <= '0';
+        trst_rst <= '0';
+        tms_rst <= '0';
+        tdi_rst <= '0';
+        tdo_rst <= '0';
+    end if;
+end process;
+
+process(clk_div2_out, reset_mae2)
+begin
+    if reset_mae2 = '1' then
+        state2 <= IDLE;
+    elsif rising_edge(clk_div2_out) then
+        case state2 is
+            when IDLE =>
+                read_en_o <= '0';   -- Disable read OUT
+                write_en_i <= '0';   -- Disable write IN
+                transit2 <= '1';
+                if transit1 = '0' and PA2_I = '0' then
+                    state2 <= WRITE_IN;
+				else
+					state2 <= IDLE;
+                end if;
+
+            when WRITE_IN =>
+                read_en_o <= '1';    -- Enable read OUT
+                write_en_i <= '1';    -- Enable write IN
+                if PA2_I = '1' then
+                    state2 <= DELAY;  -- Change state to DELAY
+                else
+                    state2 <= WRITE_IN;  -- Stay in WRITE_IN state
+                end if;
+
+            when DELAY =>
+                transit2 <= '0'; -- Enable READ IN
+                if empty_o = '1' then
+						  read_en_o <= '0';    -- Disable read OUT
+						  write_en_i <= '0';    -- Disable write IN
+                    state2 <= IDLE; -- Change state to IDLE
+                else
+                    state2 <= DELAY;  -- Stay in READ_IN state
+                end if;
+
+            when others =>
+                state2 <= IDLE;
+        end case;
+    end if;
+end process;
+
+process(IFCLK_I, reset_mae)
+begin
+    if reset_mae = '1' then
+        state <= IDLE;
+    elsif rising_edge(IFCLK_I) then
+        case state is
+            when IDLE =>
+                wr_o <= '1';   -- Disable write OUT
+                rd_i <= '1';    -- Disable read IN
+                transit1 <= '1';
+                if PA2_I = '0' then
+                    state <= WRITE_OUT;    -- Change state to RESET
+                else
+                    state <= IDLE; -- Stay in IDLE state
+                end if;
+
+            when WRITE_OUT =>
+                wr_o <= '0';   -- Enable write OUT
+                if empty_o = '0' then
+                    transit1 <= '0'; -- Enable Rd OUT & Wr IN
+                    state <= DELAY; -- Change state to DELAY
+                else
+                    state <= WRITE_OUT;    -- Stay in WRITE_OUT state
+                end if;
+
+            when DELAY =>
+                if transit2 = '0' then
+                    wr_o <= '1';   -- Disable write OUT
+                    state <= READ_IN;
+                else
+                    state <= DELAY;
+                end if;
+
+            when READ_IN =>
+                rd_i <= '0';    -- Enable read IN
+                if empty_i = '1' then
+                    rd_i <= '1';    -- Enable read IN
+                    state <= IDLE; -- Change state to IDLE
+                else
+                    state <= READ_IN;  -- Stay in READ_IN state
+                end if;
+
+            when others =>
+                state <= IDLE;
+        end case;
+    end if;
+end process;
+
+-- OUT signals direction
+-- TRST, TMS, TCK and TDI : out
+ST_0_O <= '0';
+-- TDO : in
+ST_1_O <= '1';
+-- SRST : out
+ST_2_O <= '1';
+SO_SRST_O <= '0';
+-- MOD : in
+ST_3_O <= '1';
+
+end A_angie_bitstream;

contrib/firmware/angie/hdl/src/clk_div.vhd

@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+entity clk_div is
+    Port (
+        clk_in : in  std_logic;
+        reset : in std_logic;
+        clk_out : out std_logic
+    );
+end clk_div;
+
+architecture behavioral of clk_div is
+    -- Division factor N = 4, so we need a 2-bit counter (2^2 = 4)
+--    signal counter : unsigned(1 downto 0) := (others => '0');
+    signal tmp : std_logic;
+begin
+    process(clk_in, reset)
+    begin
+        if reset = '1' then
+--            counter <= (others => '0');
+            tmp <= '0';
+        elsif rising_edge(clk_in) then
+--            if counter = (2**2 - 1) then
+--                counter <= (others => '0');
+            tmp <= NOT tmp; -- Toggle the output clock
+--            else
+--                counter <= counter + 1;
+--            end if;
+        end if;
+    end process;
+    clk_out <= tmp;
+end behavioral;

contrib/firmware/angie/hdl/src/dff.vhd

@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_arith.ALL;
+use ieee.std_logic_unsigned.ALL;
+
+entity DFF is
+port (  clk : in std_logic;
+        reset : in std_logic;
+        d : in std_logic;
+        q : out std_logic);
+end DFF;
+
+architecture Behavioral of DFF is
+begin
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            q <= '1'; -- Reset output to 0
+        elsif rising_edge(clk) then
+            q <= d; -- Capture D at the rising edge of the clock
+        end if;
+    end process;
+end Behavioral;

contrib/itmdump.c

@@ -43,9 +43,9 @@ unsigned int dump_swit;
  * NOTE that this specific encoding could be space-optimized; and that
  * trace data streams could also be history-sensitive.
  */
-static void show_task(int port, unsigned data)
+static void show_task(int port, unsigned int data)
 {
-	unsigned code = data >> 16;
+	unsigned int code = data >> 16;
 	char buf[16];
 
 	if (dump_swit)
@@ -77,7 +77,7 @@ static void show_task(int port, unsigned data)
 
 static void show_reserved(FILE *f, char *label, int c)
 {
-	unsigned i;
+	unsigned int i;
 
 	if (dump_swit)
 		return;
@@ -96,9 +96,9 @@ static void show_reserved(FILE *f, char *label, int c)
 	printf("\n");
 }
 
-static bool read_varlen(FILE *f, int c, unsigned *value)
+static bool read_varlen(FILE *f, int c, unsigned int *value)
 {
-	unsigned size;
+	unsigned int size;
 	unsigned char buf[4];
 
 	*value = 0;
@@ -135,8 +135,8 @@ err:
 
 static void show_hard(FILE *f, int c)
 {
-	unsigned type = c >> 3;
-	unsigned value;
+	unsigned int type = c >> 3;
+	unsigned int value;
 	char *label;
 
 	if (dump_swit)
@@ -230,16 +230,16 @@ static void show_hard(FILE *f, int c)
  */
 struct {
 	int port;
-	void (*show)(int port, unsigned data);
+	void (*show)(int port, unsigned int data);
 } format[] = {
 	{ .port = 31,  .show = show_task, },
 };
 
 static void show_swit(FILE *f, int c)
 {
-	unsigned port = c >> 3;
-	unsigned value = 0;
-	unsigned i;
+	unsigned int port = c >> 3;
+	unsigned int value = 0;
+	unsigned int i;
 
 	if (port + 1 == dump_swit) {
 		if (!read_varlen(f, c, &value))
@@ -272,7 +272,7 @@ static void show_swit(FILE *f, int c)
 
 static void show_timestamp(FILE *f, int c)
 {
-	unsigned counter = 0;
+	unsigned int counter = 0;
 	char *label = "";
 	bool delayed = false;
 

contrib/list_example.c

@@ -12,7 +12,7 @@
 #include <assert.h>
 #include <helper/list.h>
 
-static LIST_HEAD(threads);
+static OOCD_LIST_HEAD(threads);
 
 struct thread {
 	int id;

contrib/loaders/flash/at91sam7x/main.c

@@ -70,23 +70,23 @@ int main (void)
 	for (;;) {
 		cmd = dcc_rd();
 		switch (cmd&OCL_CMD_MASK) {
-			case OCL_PROBE:
-				dcc_wr(OCL_CMD_DONE | flash_init());
-				dcc_wr(0x100000); /* base */
-				dcc_wr(flash_page_count*flash_page_size); /* size */
-				dcc_wr(1); /* num_sectors */
-				dcc_wr(4096 | ((unsigned long) flash_page_size << 16)); /* buflen and bufalign */
-				break;
-			case OCL_ERASE_ALL:
-				dcc_wr(OCL_CMD_DONE | flash_erase_all());
-				break;
-			case OCL_FLASH_BLOCK:
-				cmd_flash(cmd);
-				break;
-			default:
-				/* unknown command */
-				dcc_wr(OCL_CMD_ERR);
-				break;
+		case OCL_PROBE:
+			dcc_wr(OCL_CMD_DONE | flash_init());
+			dcc_wr(0x100000); /* base */
+			dcc_wr(flash_page_count * flash_page_size); /* size */
+			dcc_wr(1); /* num_sectors */
+			dcc_wr(4096 | ((unsigned long)flash_page_size << 16)); /* buflen and bufalign */
+			break;
+		case OCL_ERASE_ALL:
+			dcc_wr(OCL_CMD_DONE | flash_erase_all());
+			break;
+		case OCL_FLASH_BLOCK:
+			cmd_flash(cmd);
+			break;
+		default:
+			/* unknown command */
+			dcc_wr(OCL_CMD_ERR);
+			break;
 		}
 	}
 

contrib/loaders/flash/at91sam7x/samflash.c

@@ -22,38 +22,38 @@ int flash_init(void)
 	nvpsiz = (inr(DBGU_CIDR) >> 8)&0xf;
 
 	switch (nvpsiz) {
-		case 3:
-			/* AT91SAM7x32 */
-			flash_page_count = 256;
-			flash_page_size = 128;
-			flash_lock_pages = 256/8;
-			break;
-		case 5:
-			/* AT91SAM7x64 */
-			flash_page_count = 512;
-			flash_page_size = 128;
-			flash_lock_pages = 512/16;
-			break;
-		case 7:
-			/* AT91SAM7x128*/
-			flash_page_count = 512;
-			flash_page_size = 256;
-			flash_lock_pages = 512/8;
-			break;
-		case 9:
-			/* AT91SAM7x256 */
-			flash_page_count = 1024;
-			flash_page_size = 256;
-			flash_lock_pages = 1024/16;
-			break;
-		case 10:
-			/* AT91SAM7x512 */
-			flash_page_count = 2048;
-			flash_page_size = 256;
-			flash_lock_pages = 2048/32;
-			break;
-		default:
-			return FLASH_STAT_INITE;
+	case 3:
+		/* AT91SAM7x32 */
+		flash_page_count = 256;
+		flash_page_size = 128;
+		flash_lock_pages = 256 / 8;
+		break;
+	case 5:
+		/* AT91SAM7x64 */
+		flash_page_count = 512;
+		flash_page_size = 128;
+		flash_lock_pages = 512 / 16;
+		break;
+	case 7:
+		/* AT91SAM7x128*/
+		flash_page_count = 512;
+		flash_page_size = 256;
+		flash_lock_pages = 512 / 8;
+		break;
+	case 9:
+		/* AT91SAM7x256 */
+		flash_page_count = 1024;
+		flash_page_size = 256;
+		flash_lock_pages = 1024 / 16;
+		break;
+	case 10:
+		/* AT91SAM7x512 */
+		flash_page_count = 2048;
+		flash_page_size = 256;
+		flash_lock_pages = 2048 / 32;
+		break;
+	default:
+		return FLASH_STAT_INITE;
 	}
 	return FLASH_STAT_OK;
 }

contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c

@@ -52,7 +52,7 @@ static inline __attribute__((always_inline)) uint32_t flashWrite(uint32_t addres
 		/* Clear the IRQ flags */
 		*((volatile uint32_t *)(flash_regs_base + FLASH_REG_IRQRAW)) = 0x0000003F;
 		/* Load the flash address to write */
-		*((volatile uint32_t *)(flash_regs_base + FLASH_REG_ADDRESS)) = (uint16_t)((address + index - MFB_BOTTOM) >> 2);
+		*((volatile uint32_t *)(flash_regs_base + FLASH_REG_ADDRESS)) = (uint32_t)((address + index - MFB_BOTTOM) >> 2);
 		/* Prepare and load the data to flash */
 		*((volatile uint32_t *)(flash_regs_base + FLASH_REG_DATA0)) = flash_word[0];
 		*((volatile uint32_t *)(flash_regs_base + FLASH_REG_DATA1)) = flash_word[1];

contrib/loaders/flash/bluenrg-x/bluenrg-x_write.inc

@@ -1,17 +1,19 @@
 /* Autogenerated with ../../../../src/helper/bin2char.sh */
-0x05,0x93,0x43,0x68,0x14,0x9e,0x09,0x93,0x05,0x9b,0x05,0x00,0x07,0x91,0x06,0x92,
-0x01,0x24,0xb1,0x46,0x00,0x2b,0x68,0xd0,0x6a,0x68,0x2b,0x68,0x9a,0x42,0xfb,0xd0,
-0x2b,0x68,0x00,0x2b,0x61,0xd0,0x6a,0x68,0x2b,0x68,0x9a,0x42,0x5e,0xd9,0x6b,0x68,
-0x07,0x9a,0xd3,0x1a,0x0f,0x2b,0xef,0xdd,0x4a,0x46,0x00,0x21,0x03,0x93,0xd1,0x60,
-0x00,0x2b,0x42,0xd0,0x40,0x22,0x4a,0x44,0x90,0x46,0x44,0x22,0x4a,0x44,0x00,0x92,
-0x48,0x22,0x4a,0x44,0x93,0x46,0x4c,0x22,0x27,0x4f,0x4a,0x44,0xbc,0x46,0x4e,0x46,
-0x92,0x46,0x06,0x99,0x4b,0x46,0x61,0x44,0x08,0x00,0x00,0x99,0x18,0x36,0x6a,0x68,
-0x08,0x95,0x8c,0x46,0x55,0x46,0xda,0x46,0xb3,0x46,0x10,0x33,0x04,0x92,0x11,0x68,
-0x5e,0x46,0x00,0x91,0x51,0x68,0x97,0x68,0x01,0x91,0xd1,0x68,0x02,0x91,0x3f,0x21,
-0x19,0x60,0x81,0x03,0x09,0x0c,0x31,0x60,0x46,0x46,0x00,0x99,0x31,0x60,0x66,0x46,
-0x01,0x99,0x31,0x60,0x56,0x46,0x02,0x99,0x37,0x60,0x29,0x60,0xcc,0x26,0x49,0x46,
-0x0e,0x60,0x19,0x68,0x0c,0x42,0xfc,0xd0,0x04,0x99,0x03,0x9e,0x10,0x32,0x10,0x30,
-0x51,0x1a,0x8e,0x42,0xdb,0xd8,0x08,0x9d,0x6a,0x60,0x03,0x9a,0x06,0x9b,0x94,0x46,
-0x63,0x44,0x06,0x93,0x07,0x9a,0x6b,0x68,0x9a,0x42,0x01,0xd8,0x09,0x9b,0x6b,0x60,
-0x05,0x9b,0x03,0x9a,0x9b,0x1a,0x05,0x93,0x96,0xd1,0x00,0xbe,0x2b,0x68,0x6a,0x68,
-0x9b,0x1a,0x9f,0xd5,0x90,0xe7,0xc0,0x46,0x00,0x00,0xfc,0xef,
+0x16,0x9e,0x05,0x00,0x01,0x24,0xb1,0x46,0x06,0x93,0x43,0x68,0x08,0x91,0x07,0x92,
+0x09,0x93,0x06,0x9b,0x00,0x2b,0x6f,0xd0,0x6a,0x68,0x2b,0x68,0x9a,0x42,0xfb,0xd0,
+0x2b,0x68,0x00,0x2b,0x68,0xd0,0x6a,0x68,0x2b,0x68,0x9a,0x42,0x65,0xd9,0x6b,0x68,
+0x08,0x9a,0xd3,0x1a,0x0b,0x93,0x0b,0x9b,0x0f,0x2b,0xea,0xdd,0x4a,0x46,0x00,0x21,
+0x0b,0x9b,0xd1,0x60,0x04,0x93,0x00,0x2b,0x43,0xd0,0x31,0x4a,0x07,0x9b,0x94,0x46,
+0x40,0x22,0x4a,0x44,0x90,0x46,0x44,0x22,0x4a,0x44,0x63,0x44,0x94,0x46,0x48,0x22,
+0x4a,0x44,0x93,0x46,0x05,0x93,0x4c,0x22,0x4b,0x46,0x4a,0x44,0x10,0x33,0x4e,0x46,
+0x92,0x46,0x00,0x93,0x2b,0x00,0x18,0x36,0x6a,0x68,0x55,0x46,0xb2,0x46,0x5e,0x46,
+0x9b,0x46,0x10,0x68,0x57,0x68,0x01,0x90,0x3f,0x20,0x00,0x9b,0x02,0x97,0x97,0x68,
+0x03,0x97,0xd7,0x68,0x18,0x60,0x53,0x46,0x05,0x98,0x40,0x18,0x80,0x08,0x18,0x60,
+0x43,0x46,0x01,0x98,0x18,0x60,0x63,0x46,0x02,0x98,0x18,0x60,0x03,0x98,0x4b,0x46,
+0x30,0x60,0xcc,0x20,0x2f,0x60,0x18,0x60,0x00,0x9b,0x18,0x68,0x04,0x42,0xfc,0xd0,
+0x58,0x46,0x10,0x32,0x42,0x60,0x04,0x98,0x10,0x31,0x00,0x93,0x88,0x42,0xd8,0xd8,
+0x5d,0x46,0x07,0x9a,0x0b,0x9b,0x94,0x46,0x9c,0x44,0x63,0x46,0x08,0x9a,0x07,0x93,
+0x6b,0x68,0x93,0x42,0x01,0xd3,0x09,0x9b,0x6b,0x60,0x06,0x9a,0x0b,0x9b,0xd3,0x1a,
+0x06,0x93,0x06,0x9b,0x00,0x2b,0x8f,0xd1,0x00,0xbe,0x2b,0x68,0x6a,0x68,0x9b,0x1a,
+0x0b,0x93,0x0b,0x9b,0x00,0x2b,0x00,0xdb,0x95,0xe7,0x00,0x23,0x0b,0x93,0x92,0xe7,
+0x00,0x00,0xfc,0xef,

contrib/loaders/flash/cc26xx/cc26x0_algo.inc

@@ -1,249 +1,248 @@
 /* Autogenerated with ../../../../src/helper/bin2char.sh */
 0x08,0xb5,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0xdf,0xf8,0x1c,0xd0,0x07,0x48,
-0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xfa,0xdb,
-0x00,0xf0,0xa8,0xf9,0xfe,0xe7,0x00,0x00,0xf0,0x0e,0x00,0x20,0x54,0x13,0x00,0x20,
-0x98,0x13,0x00,0x20,0x08,0xb5,0x07,0x4b,0x07,0x48,0x03,0x33,0x1b,0x1a,0x06,0x2b,
-0x04,0xd9,0x06,0x4b,0x00,0x2b,0x01,0xd0,0x00,0xf0,0x5c,0xf8,0x08,0xbc,0x01,0xbc,
-0x00,0x47,0xc0,0x46,0x50,0x13,0x00,0x20,0x50,0x13,0x00,0x20,0x00,0x00,0x00,0x00,
-0x08,0x48,0x09,0x49,0x09,0x1a,0x89,0x10,0x08,0xb5,0xcb,0x0f,0x59,0x18,0x49,0x10,
-0x04,0xd0,0x06,0x4b,0x00,0x2b,0x01,0xd0,0x00,0xf0,0x44,0xf8,0x08,0xbc,0x01,0xbc,
-0x00,0x47,0xc0,0x46,0x50,0x13,0x00,0x20,0x50,0x13,0x00,0x20,0x00,0x00,0x00,0x00,
-0x10,0xb5,0x08,0x4c,0x23,0x78,0x00,0x2b,0x09,0xd1,0xff,0xf7,0xcb,0xff,0x06,0x4b,
+0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xff,0xf6,
+0xfa,0xaf,0x00,0xf0,0x71,0xf9,0xfe,0xe7,0xe0,0x0e,0x00,0x20,0x44,0x13,0x00,0x20,
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 0x00,0x2b,0x02,0xd0,0x05,0x48,0xaf,0xf3,0x00,0x80,0x01,0x23,0x23,0x70,0x10,0xbc,
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-0x0a,0x48,0x03,0x68,0x00,0x2b,0x04,0xd1,0xff,0xf7,0xc2,0xff,0x08,0xbc,0x01,0xbc,
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-0x15,0x00,0x00,0x0a,0xd1,0xf0,0x21,0xe3,0x03,0xd0,0xa0,0xe1,0x01,0xaa,0x4d,0xe2,
-0x0a,0x30,0xa0,0xe1,0xd7,0xf0,0x21,0xe3,0x03,0xd0,0xa0,0xe1,0x01,0x3a,0x43,0xe2,
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-0x03,0xd0,0xa0,0xe1,0x02,0x3a,0x43,0xe2,0xd3,0xf0,0x21,0xe3,0x03,0xd0,0xa0,0xe1,
-0x02,0x39,0x43,0xe2,0xff,0x30,0xc3,0xe3,0xff,0x3c,0xc3,0xe3,0x04,0x30,0x03,0xe5,
-0x00,0x20,0x53,0xe9,0xc0,0x20,0x82,0xe3,0x02,0xf0,0x21,0xe1,0x01,0xa8,0x43,0xe2,
-0x00,0x10,0xb0,0xe3,0x01,0xb0,0xa0,0xe1,0x01,0x70,0xa0,0xe1,0x5c,0x00,0x9f,0xe5,
-0x5c,0x20,0x9f,0xe5,0x00,0x20,0x52,0xe0,0x01,0x30,0x8f,0xe2,0x13,0xff,0x2f,0xe1,
-0x00,0xf0,0x42,0xfd,0x10,0x4b,0x00,0x2b,0x01,0xd0,0xfe,0x46,0x9f,0x46,0x0f,0x4b,
-0x00,0x2b,0x01,0xd0,0xfe,0x46,0x9f,0x46,0x00,0x20,0x00,0x21,0x04,0x00,0x0d,0x00,
-0x0d,0x48,0x00,0xf0,0x89,0xfc,0x00,0xf0,0xc3,0xfc,0x20,0x00,0x29,0x00,0x00,0xf0,
-0xd1,0xf8,0x00,0xf0,0x8b,0xfc,0x7b,0x46,0x18,0x47,0x00,0x00,0x11,0x00,0x00,0xef,
-0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x54,0x13,0x00,0x20,0x98,0x13,0x00,0x20,0x15,0x0b,0x00,0x20,0x70,0xb5,0x04,0x46,
-0x0e,0x46,0x15,0x46,0x00,0x21,0x28,0x22,0x00,0xf0,0x0e,0xfd,0x26,0x61,0x65,0x62,
-0x00,0x21,0x20,0x22,0x02,0x48,0x00,0xf0,0x07,0xfd,0x00,0x20,0x70,0xbd,0x00,0xbf,
-0x70,0x13,0x00,0x20,0x10,0xb5,0x01,0x20,0x00,0xf0,0xac,0xf9,0x04,0x46,0x28,0xb9,
-0x01,0x21,0x20,0x22,0x03,0x48,0x00,0xf0,0xf7,0xfc,0x01,0xe0,0x40,0xf2,0x01,0x14,
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+0x18,0x15,0x00,0x20,0xff,0xff,0xff,0xc5,0xff,0xff,0xff,0xff,0xc5,0xff,0xff,0xff,
+0xc5,0xc5,0xc5,0xff,0xc5,0xc5,0xc5,0xff,0x43,0x00,0x00,0x00,0x08,0x0f,0x00,0x20,
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+0x5c,0x12,0x00,0x20,0xc4,0x12,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x0f,0x00,0x20,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,0x0e,0x00,0x20,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -307,8 +306,9 @@
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x18,0x0f,0x00,0x20,0xc1,0x00,0x00,0x20,0x91,0x00,0x00,0x20,0x00,0x00,0x00,0x00,
-0x95,0x0d,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x08,0x0f,0x00,0x20,0x61,0x00,0x00,0x20,0x35,0x00,0x00,0x20,0x00,0x00,0x00,0x00,
+0x69,0x0c,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

contrib/loaders/flash/cc26xx/cc26x2_algo.inc

@@ -1,258 +1,257 @@
 /* Autogenerated with ../../../../src/helper/bin2char.sh */
 0x08,0xb5,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0xdf,0xf8,0x1c,0xd0,0x07,0x48,
-0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xfa,0xdb,
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+0x02,0x35,0xad,0x00,0x63,0x60,0x2f,0x51,0x00,0x20,0x03,0xb0,0x0c,0xbc,0x90,0x46,
+0x99,0x46,0xf0,0xbc,0x02,0xbc,0x08,0x47,0xab,0x00,0xe3,0x18,0x88,0x22,0x48,0x46,
+0x98,0x50,0xc4,0x20,0x40,0x00,0x22,0x18,0x10,0x68,0x01,0x21,0xa9,0x40,0x08,0x43,
+0x10,0x60,0x84,0x22,0x52,0x00,0x40,0x46,0x98,0x50,0x02,0x2e,0xdf,0xd1,0xc6,0x22,
+0x52,0x00,0xa3,0x18,0x18,0x68,0x01,0x43,0x19,0x60,0xd8,0xe7,0x1c,0x1c,0x4d,0x34,
+0xff,0x34,0x5c,0x51,0xb3,0xe7,0xc0,0x46,0x04,0x0f,0x00,0x20,0x00,0x00,0x00,0x00,
+0xf8,0xb5,0xc0,0x46,0xf8,0xbc,0x08,0xbc,0x9e,0x46,0x70,0x47,0xf8,0xb5,0xc0,0x46,
+0xf8,0xbc,0x08,0xbc,0x9e,0x46,0x70,0x47,0x00,0x00,0x00,0x00,0xc4,0xf1,0xff,0x7f,
+0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x84,0x15,0x00,0x20,0xff,0xff,0xff,0xc5,
+0xff,0xff,0xff,0xff,0xc5,0xff,0xff,0xff,0xc5,0xc5,0xc5,0xff,0xc5,0xc5,0xc5,0xff,
+0x43,0x00,0x00,0x00,0x10,0x0f,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xfc,0x11,0x00,0x20,0x64,0x12,0x00,0x20,0xcc,0x12,0x00,0x20,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x0f,0x00,0x20,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x0f,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0e,0x33,0xcd,0xab,0x34,0x12,0x6d,0xe6,
-0xec,0xde,0x05,0x00,0x0b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x0e,0x33,0xcd,0xab,0x34,0x12,0x6d,0xe6,0xec,0xde,0x05,0x00,0x0b,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -307,8 +306,9 @@
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x18,0x0f,0x00,0x20,0xc1,0x00,0x00,0x20,0x91,0x00,0x00,0x20,0x00,0x00,0x00,0x00,
-0x95,0x0d,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x0f,0x00,0x20,0x61,0x00,0x00,0x20,
+0x35,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x6d,0x0c,0x00,0x20,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

contrib/loaders/flash/cc26xx/flash.c

@@ -42,7 +42,7 @@ typedef uint32_t (*flash_sector_erase_pntr_t) (uint32_t);
 *
 ******************************************************************************/
 static void issue_fsm_command(flash_state_command_t command);
-static void enable_sectors_for_write(void);
+static void enable_sectors_for_write(uint32_t);
 static uint32_t scale_cycle_values(uint32_t specified_timing,
 	uint32_t scale_value);
 static void set_write_mode(void);
@@ -80,42 +80,51 @@ uint32_t flash_bank_erase(bool force_precondition)
 	uint32_t error_return;
 	uint32_t sector_address;
 	uint32_t reg_val;
+	uint32_t bank_no;
+	uint32_t top_bank_start_addr = (HWREG(FLASH_BASE + FLASH_O_FCFG_B1_START) &
+					FLASH_FCFG_B1_START_B1_START_ADDR_M)
+					>> FLASH_FCFG_B1_START_B1_START_ADDR_S;
 
-	/* Enable all sectors for erase. */
-	enable_sectors_for_write();
+	for (bank_no = 0; bank_no < flash_bank_count(); bank_no++) {
+		/* Enable all sectors for erase. */
+		enable_sectors_for_write(bank_no);
 
-	/* Clear the Status register. */
-	issue_fsm_command(FAPI_CLEAR_STATUS);
+		/* Clear the Status register. */
+		issue_fsm_command(FAPI_CLEAR_STATUS);
 
-	/* Enable erase of all sectors and enable precondition if required. */
-	reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE);
-	HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
-	HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000;
-	HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000;
-	if (force_precondition)
-		HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |=
-			FLASH_FSM_ST_MACHINE_DO_PRECOND;
-	HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
-
-	/* Issue the bank erase command to the FSM. */
-	issue_fsm_command(FAPI_ERASE_BANK);
-
-	/* Wait for erase to finish. */
-	while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY)
-		;
-
-	/* Update status. */
-	error_return = flash_check_fsm_for_error();
-
-	/* Disable sectors for erase. */
-	flash_disable_sectors_for_write();
-
-	/* Set configured precondition mode since it may have been forced on. */
-	if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) {
+		/* Enable erase of all sectors and enable precondition if required. */
+		reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE);
 		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
-		HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &=
-			~FLASH_FSM_ST_MACHINE_DO_PRECOND;
+		HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000;
+		HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000;
+		if (force_precondition)
+			HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |=
+				FLASH_FSM_ST_MACHINE_DO_PRECOND;
 		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+
+		// Write address to FADDR register.
+		HWREG(FLASH_BASE + FLASH_O_FADDR) = ADDR_OFFSET + (bank_no * top_bank_start_addr);
+
+		/* Issue the bank erase command to the FSM. */
+		issue_fsm_command(FAPI_ERASE_BANK);
+
+		/* Wait for erase to finish. */
+		while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY)
+			;
+
+		/* Update status. */
+		error_return = flash_check_fsm_for_error();
+
+		/* Set configured precondition mode since it may have been forced on. */
+		if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) {
+			HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+			HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &=
+				~FLASH_FSM_ST_MACHINE_DO_PRECOND;
+			HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+		}
+
+		if (error_return != FAPI_STATUS_SUCCESS)
+			break;
 	}
 
 	/* Program security data to default values in the customer configuration */
@@ -128,6 +137,9 @@ uint32_t flash_bank_erase(bool force_precondition)
 							CCFG_SIZE_SECURITY);
 	}
 
+	/* Disable sectors for erase. */
+	flash_disable_sectors_for_write();
+
 	/* Return status of operation. */
 	return error_return;
 }
@@ -161,23 +173,34 @@ uint32_t flash_program(uint8_t *data_buffer, uint32_t address, uint32_t count)
 ******************************************************************************/
 void flash_disable_sectors_for_write(void)
 {
+	uint32_t bank_no;
+
 	/* Configure flash back to read mode */
 	set_read_mode();
 
-	/* Disable Level 1 Protection. */
-	HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
+	for (bank_no = 0; bank_no < flash_bank_count(); bank_no++) {
 
-	/* Disable all sectors for erase and programming. */
-	HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000;
+		/* Select flash bank. */
+		HWREG(FLASH_BASE + FLASH_O_FMAC) = bank_no;
 
-	/* Enable Level 1 Protection. */
-	HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0;
+		/* Disable Level 1 Protection. */
+		HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
 
-	/* Protect sectors from sector erase. */
-	HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
-	HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF;
-	HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF;
-	HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+		/* Disable all sectors for erase and programming. */
+		HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000;
+
+		/* Enable Level 1 Protection. */
+		HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0;
+
+		/* Protect sectors from sector erase. */
+		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+		HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF;
+		HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF;
+		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+	}
+
+	// Select bank 0
+	HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x0;
 }
 
 /******************************************************************************
@@ -214,7 +237,7 @@ static void issue_fsm_command(flash_state_command_t command)
 * the FLASH_O_FSM_SECTOR1 register.
 *
 ******************************************************************************/
-static void enable_sectors_for_write(void)
+static void enable_sectors_for_write(uint32_t bank_no)
 {
 	/* Trim flash module for program/erase operation. */
 	trim_for_write();
@@ -223,7 +246,7 @@ static void enable_sectors_for_write(void)
 	set_write_mode();
 
 	/* Select flash bank. */
-	HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00;
+	HWREG(FLASH_BASE + FLASH_O_FMAC) = bank_no;
 
 	/* Disable Level 1 Protection. */
 	HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;

contrib/loaders/flash/cc26xx/flash.h

@@ -246,6 +246,46 @@ static inline uint32_t flash_check_fsm_for_ready(void)
 		return FAPI_STATUS_FSM_READY;
 }
 
+/******************************************************************************
+ *
+ * Get the number of banks
+ *
+ * This function returns the number of bank of the flash.
+ *
+ * Returns the number of banks
+ *
+ ******************************************************************************/
+static inline uint32_t flash_bank_count(void)
+{
+	uint32_t bank_count;
+
+	bank_count = (HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) &
+		FLASH_FCFG_BANK_MAIN_NUM_BANK_M) >>
+		FLASH_FCFG_BANK_MAIN_NUM_BANK_S;
+
+	return bank_count;
+}
+
+/******************************************************************************
+ *
+ * Get the size of the bank.
+ *
+ * This function returns the size of the main bank in number of bytes.
+ *
+ * Returns the flash size in number of bytes.
+ *
+ ******************************************************************************/
+static inline uint8_t flash_bank_width(void)
+{
+	uint8_t bank_width;
+
+	bank_width = (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) &
+		FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >>
+		FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3);
+
+	return bank_width;
+}
+
 /******************************************************************************
 *
 * Erase a flash sector.

contrib/loaders/flash/cc26xx/hw_regs.h

@@ -116,6 +116,10 @@
 /* FMC Sequential Pump Information */
 #define FLASH_O_FSEQPMP                                             0x000020A8
 
+#define FLASH_O_FADDR                                               0x00002110
+
+#define FLASH_O_FWPWRITE0                                           0x00002120
+
 /* FMC FSM Command */
 #define FLASH_O_FSM_CMD                                             0x0000220C
 
@@ -179,9 +183,14 @@
 /* FMC FSM Sector Erased  2 */
 #define FLASH_O_FSM_SECTOR2                                         0x000022C4
 
+#define FLASH_O_FCFG_BANK                                           0x00002400
+
 /* FMC Flash Bank 0 Starting Address */
 #define FLASH_O_FCFG_B0_START                                       0x00002410
 
+/* FMC Flash Bank 1 Starting Address */
+#define FLASH_O_FCFG_B1_START                                       0x00002414
+
 /* FMC Flash Bank 0 Sector Size 0 */
 #define FLASH_O_FCFG_B0_SSIZE0                                      0x00002430
 
@@ -1353,4 +1362,16 @@
 * 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR */
 #define AON_PMCTL_PWRCTL_EXT_REG_MODE                               0x00000002
 
+/* Field:   [3:0] MAIN_NUM_BANK */
+#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F
+#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0
+
+/* Field:  [23:0] B1_START_ADDR */
+#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF
+#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0
+
+/* Field:  [15:4] MAIN_BANK_WIDTH */
+#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0
+#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4
+
 #endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H */

contrib/loaders/flash/cc26xx/main.c

@@ -98,35 +98,32 @@ int main(void)
 
 		/* Perform requested task */
 		switch (g_cfg[g_curr_buf].cmd) {
-			case CMD_ERASE_ALL:
-				status = flashloader_erase_all();
-				break;
-			case CMD_PROGRAM:
-				status =
-					flashloader_program(
-						(uint8_t *)g_cfg[g_curr_buf].buf_addr,
-						g_cfg[g_curr_buf].dest, g_cfg[g_curr_buf].len);
-				break;
-			case CMD_ERASE_AND_PROGRAM:
-				status =
-					flashloader_erase_and_program(
-						(uint8_t *)g_cfg[g_curr_buf].buf_addr,
-						g_cfg[g_curr_buf].dest, g_cfg[g_curr_buf].len);
-				break;
-			case CMD_ERASE_AND_PROGRAM_WITH_RETAIN:
-				status =
-					flashloader_program_with_retain(
-						(uint8_t *)g_cfg[g_curr_buf].buf_addr,
-						g_cfg[g_curr_buf].dest, g_cfg[g_curr_buf].len);
-				break;
-			case CMD_ERASE_SECTORS:
-				status =
-					flashloader_erase_sectors(g_cfg[g_curr_buf].dest,
-						g_cfg[g_curr_buf].len);
-				break;
-			default:
-				status = STATUS_FAILED_UNKNOWN_COMMAND;
-				break;
+		case CMD_ERASE_ALL:
+			status = flashloader_erase_all();
+			break;
+		case CMD_PROGRAM:
+			status =
+				flashloader_program((uint8_t *)g_cfg[g_curr_buf].buf_addr,
+					g_cfg[g_curr_buf].dest, g_cfg[g_curr_buf].len);
+			break;
+		case CMD_ERASE_AND_PROGRAM:
+			status =
+				flashloader_erase_and_program((uint8_t *)g_cfg[g_curr_buf].buf_addr,
+					g_cfg[g_curr_buf].dest, g_cfg[g_curr_buf].len);
+			break;
+		case CMD_ERASE_AND_PROGRAM_WITH_RETAIN:
+			status =
+				flashloader_program_with_retain((uint8_t *)g_cfg[g_curr_buf].buf_addr,
+					g_cfg[g_curr_buf].dest, g_cfg[g_curr_buf].len);
+			break;
+		case CMD_ERASE_SECTORS:
+			status =
+				flashloader_erase_sectors(g_cfg[g_curr_buf].dest,
+					g_cfg[g_curr_buf].len);
+			break;
+		default:
+			status = STATUS_FAILED_UNKNOWN_COMMAND;
+			break;
 		}
 
 		restore_cache_state();

contrib/loaders/flash/dw-spi/Makefile

@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+TOOLCHAIN:=mipsel-linux-gnu-
+CC:=$(TOOLCHAIN)gcc
+OBJCOPY:=$(TOOLCHAIN)objcopy
+CFLAGS:=-O2 -Wall -Wextra -fpic -Wno-int-to-pointer-cast
+SRC=dw-spi.c
+OBJ=$(patsubst %.c, %.o,$(SRC))
+
+# sparx-iv
+ifeq ($(TOOLCHAIN),mipsel-linux-gnu-)
+	CFLAGS+= -march=24kec
+endif
+
+all: \
+	$(TOOLCHAIN)transaction.inc \
+	$(TOOLCHAIN)erase.inc \
+	$(TOOLCHAIN)check_fill.inc \
+	$(TOOLCHAIN)program.inc \
+	$(TOOLCHAIN)read.inc
+
+$(TOOLCHAIN)%.bin: $(OBJ)
+	$(OBJCOPY) --dump-section .$*=$@ $<
+
+%.inc: %.bin
+	xxd -i > $@ < $<
+
+.PHONY: clean
+clean:
+	rm -rf .ccls-cache
+	find . \( \
+	-iname "*.o" \
+	-o -iname "*.bin" \
+	-o -iname "*.inc" \
+	\) -delete

contrib/loaders/flash/dw-spi/dw-spi.c

@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/**
+ * @file
+ * Helper functions for DesignWare SPI Core driver.
+ * These helpers are loaded into CPU and execute Flash manipulation algorithms
+ * at full CPU speed. Due to inability to control nCS pin, this is the only way
+ * to communicate with Flash chips connected via DW SPI serial interface.
+ *
+ * In order to avoid using stack, all functions used in helpers are inlined.
+ * Software breakpoints are used to terminate helpers.
+ *
+ * Pushing byte to TX FIFO does not make byte immediately available in RX FIFO
+ * and nCS is only asserted when TX FIFO is not empty. General approach is to
+ * fill TX FIFO with as many bytes as possible, at the same time reading
+ * available bytes from RX FIFO.
+ *
+ * This file contains helper functions.
+ */
+
+#include "dw-spi.h"
+
+#include "../../../../src/flash/nor/dw-spi-helper.h"
+
+/**
+ * @brief Generic flash transaction.
+ *
+ * @param[in] arg: Function arguments.
+ */
+__attribute__((section(".transaction"))) void
+transaction(struct dw_spi_transaction *arg)
+{
+	register uint8_t *buffer_tx = (uint8_t *)arg->buffer;
+	register uint8_t *buffer_rx = buffer_tx;
+	register uint32_t size = arg->size;
+	register volatile uint8_t *status = (uint8_t *)arg->status_reg;
+	register volatile uint8_t *data = (uint8_t *)arg->data_reg;
+
+	wait_tx_finish(status);
+	flush_rx(status, data);
+
+	for (; size > 0; size--) {
+		send_u8(status, data, *buffer_tx++);
+		if (arg->read_flag && rx_available(status))
+			*buffer_rx++ = rcv_byte(data);
+	}
+
+	// Pushed all data to TX FIFO. Read bytes left in RX FIFO.
+	if (arg->read_flag) {
+		while (buffer_rx < buffer_tx) {
+			wait_rx_available(status);
+			*buffer_rx++ = rcv_byte(data);
+		}
+	}
+
+	RETURN;
+}
+
+/**
+ * @brief Check flash sectors are filled with pattern. Primary use for
+ * checking sector erase state.
+ *
+ * @param[in] arg: Function arguments.
+ */
+__attribute__((section(".check_fill"))) void
+check_fill(struct dw_spi_check_fill *arg)
+{
+	register uint32_t tx_size;
+	register uint32_t rx_size;
+	register uint32_t dummy_count;
+	register uint8_t filled;
+	register uint8_t *fill_status_array = (uint8_t *)arg->fill_status_array;
+	register volatile uint8_t *status = (uint8_t *)arg->status_reg;
+	register volatile uint8_t *data = (uint8_t *)arg->data_reg;
+
+	for (; arg->sector_count > 0; arg->sector_count--,
+								  arg->address += arg->sector_size,
+								  fill_status_array++) {
+		wait_tx_finish(status);
+		flush_rx(status, data);
+
+		/*
+		 * Command byte and address bytes make up for dummy_count number of
+		 * bytes, that must be skipped in RX FIFO before actual data arrives.
+		 */
+		send_u8(status, data, arg->read_cmd);
+		if (arg->four_byte_mode) {
+			dummy_count = 1 + 4; // Command byte + 4 address bytes
+			send_u32(status, data, arg->address);
+		} else {
+			dummy_count = 1 + 3; // Command byte + 3 address bytes
+			send_u24(status, data, arg->address);
+		}
+
+		for (tx_size = arg->sector_size, rx_size = arg->sector_size, filled = 1;
+			 tx_size > 0; tx_size--) {
+			send_u8(status, data, 0); // Dummy write to push out read data.
+			if (rx_available(status)) {
+				if (dummy_count > 0) {
+					// Read data not arrived yet.
+					rcv_byte(data);
+					dummy_count--;
+				} else {
+					if (rcv_byte(data) != arg->pattern) {
+						filled = 0;
+						break;
+					}
+					rx_size--;
+				}
+			}
+		}
+		if (filled) {
+			for (; rx_size > 0; rx_size--) {
+				wait_rx_available(status);
+				if (rcv_byte(data) != arg->pattern) {
+					filled = 0;
+					break;
+				}
+			}
+		}
+		*fill_status_array = filled;
+	}
+
+	RETURN;
+}
+
+/**
+ * @brief Erase flash sectors.
+ *
+ * @param[in] arg: Function arguments.
+ */
+__attribute__((section(".erase"))) void
+erase(struct dw_spi_erase *arg)
+{
+	register uint32_t address = arg->address;
+	register uint32_t count = arg->sector_count;
+	register volatile uint8_t *status = (uint8_t *)arg->status_reg;
+	register volatile uint8_t *data = (uint8_t *)arg->data_reg;
+
+	for (; count > 0; count--, address += arg->sector_size) {
+		write_enable(status, data, arg->write_enable_cmd);
+		wait_write_enable(status, data, arg->read_status_cmd,
+						  arg->write_enable_mask);
+
+		erase_sector(status, data, arg->erase_sector_cmd, address,
+					 arg->four_byte_mode);
+		wait_busy(status, data, arg->read_status_cmd, arg->busy_mask);
+	}
+
+	RETURN;
+}
+
+/**
+ * @brief Flash program.
+ *
+ * @param[in] arg: Function arguments.
+ */
+__attribute__((section(".program"))) void
+program(struct dw_spi_program *arg)
+{
+	register uint8_t *buffer = (uint8_t *)arg->buffer;
+	register uint32_t buffer_size = arg->buffer_size;
+	register volatile uint8_t *status = (uint8_t *)arg->status_reg;
+	register volatile uint8_t *data = (uint8_t *)arg->data_reg;
+	register uint32_t page_size;
+
+	while (buffer_size > 0) {
+		write_enable(status, data, arg->write_enable_cmd);
+		wait_write_enable(status, data, arg->read_status_cmd,
+						  arg->write_enable_mask);
+
+		wait_tx_finish(status);
+
+		send_u8(status, data, arg->program_cmd);
+		if (arg->four_byte_mode)
+			send_u32(status, data, arg->address);
+		else
+			send_u24(status, data, arg->address);
+
+		for (page_size = MIN(arg->page_size, buffer_size); page_size > 0;
+			 page_size--, buffer_size--) {
+			send_u8(status, data, *buffer++);
+		}
+		arg->address += arg->page_size;
+		wait_busy(status, data, arg->read_status_cmd, arg->busy_mask);
+	}
+
+	RETURN;
+}
+
+/**
+ * @brief Read data from flash.
+ *
+ * @param[in] arg: Function arguments.
+ */
+__attribute__((section(".read"))) void
+read(struct dw_spi_read *arg)
+{
+	register uint32_t tx_size = arg->buffer_size;
+	register uint32_t rx_size = arg->buffer_size;
+	register uint32_t dummy_count;
+	register uint8_t *buffer = (uint8_t *)arg->buffer;
+	register volatile uint8_t *status = (uint8_t *)arg->status_reg;
+	register volatile uint8_t *data = (uint8_t *)arg->data_reg;
+
+	wait_tx_finish(status);
+	flush_rx(status, data);
+
+	/*
+	 * Command byte and address bytes make up for dummy_count number of
+	 * bytes, that must be skipped in RX FIFO before actual data arrives.
+	 */
+	send_u8(status, data, arg->read_cmd);
+	if (arg->four_byte_mode) {
+		dummy_count = 1 + 4; // Command byte + 4 address bytes
+		send_u32(status, data, arg->address);
+	} else {
+		dummy_count = 1 + 3; // Command byte + 3 address bytes
+		send_u24(status, data, arg->address);
+	}
+
+	for (; tx_size > 0; tx_size--) {
+		send_u8(status, data, 0); // Dummy write to push out read data.
+		if (rx_available(status)) {
+			if (dummy_count > 0) {
+				rcv_byte(data);
+				dummy_count--;
+			} else {
+				*buffer++ = rcv_byte(data);
+				rx_size--;
+			}
+		}
+	}
+	while (rx_size > 0) {
+		wait_rx_available(status);
+		if (dummy_count > 0) {
+			// Read data not arrived yet.
+			rcv_byte(data);
+			dummy_count--;
+		} else {
+			*buffer++ = rcv_byte(data);
+			rx_size--;
+		}
+	}
+
+	RETURN;
+}

contrib/loaders/flash/dw-spi/dw-spi.h

@@ -0,0 +1,313 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/**
+ * @file
+ * Helper functions for DesignWare SPI Core driver.
+ * These helpers are loaded into CPU and execute Flash manipulation algorithms
+ * at full CPU speed. Due to inability to control nCS pin, this is the only way
+ * to communicate with Flash chips connected via DW SPI serial interface.
+ *
+ * In order to avoid using stack, all functions used in helpers are inlined.
+ * Software breakpoints are used to terminate helpers.
+ *
+ * This file contains functions, common to helpers.
+ */
+
+#ifndef _DW_SPI_H_
+#define _DW_SPI_H_
+
+#include <stdint.h>
+#include <sys/param.h>
+
+#include "../../../../src/helper/types.h"
+
+/**
+ * @brief SI busy status bit.
+ *
+ * Set when serial transfer is in progress, cleared when master is idle or
+ * disabled.
+ */
+#define DW_SPI_STATUS_BUSY 0x01
+
+/**
+ * @brief SI TX FIFO not full status bit.
+ *
+ * Set when TX FIFO has room for one or more data-word.
+ */
+#define DW_SPI_STATUS_TFNF 0x02
+
+/**
+ * @brief SI TX FIFO empty status bit.
+ */
+#define DW_SPI_STATUS_TFE 0x04
+
+/**
+ * @brief SI RX FIFO not empty status bit.
+ */
+#define DW_SPI_STATUS_RFNE 0x08
+
+/**
+ * @brief Return from helper function.
+ */
+#define RETURN            \
+	do {                  \
+		asm("sdbbp\n\t"); \
+		return;           \
+	} while (0)
+
+/**
+ * @brief Append byte to TX FIFO.
+ *
+ * For each transferred byte, DW SPI controller receives a byte into RX FIFO.
+ * Slave data are read by pushing dummy bytes to TX FIFO.
+ *
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] byte: Data to push.
+ */
+__attribute__((always_inline)) static inline void
+_send_byte(volatile uint8_t *dr, uint8_t byte)
+{
+	*dr = byte;
+}
+
+/**
+ * @brief Get byte from RX FIFO.
+ *
+ * Reading RX byte removes it from RX FIFO.
+ *
+ * @param[in] dr: Pointer to DR register.
+ * @return RX FIFO byte.
+ */
+__attribute__((always_inline)) static inline uint8_t
+rcv_byte(volatile uint8_t *dr)
+{
+	return *dr;
+}
+
+/**
+ * @brief Check transmission is currently in progress.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @retval 1: Transmission is in progress.
+ * @retval 0: Controller is idle or off.
+ */
+__attribute__((always_inline)) static inline int
+tx_in_progress(volatile uint8_t *sr)
+{
+	return (*sr ^ DW_SPI_STATUS_TFE) & (DW_SPI_STATUS_BUSY | DW_SPI_STATUS_TFE);
+}
+
+/**
+ * @brief Wait for controller to finish previous transaction.
+ *
+ * @param[in] sr: Pointer to SR register.
+ */
+__attribute__((always_inline)) static inline void
+wait_tx_finish(volatile uint8_t *sr)
+{
+	while (tx_in_progress(sr))
+		;
+}
+
+/**
+ * @brief Wait for room in TX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ */
+__attribute__((always_inline)) static inline void
+wait_tx_available(volatile uint8_t *sr)
+{
+	while (!(*sr & DW_SPI_STATUS_TFNF))
+		;
+}
+
+/**
+ * @brief Check for data available in RX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @retval 1: Data available.
+ * @retval 0: No data available.
+ */
+__attribute__((always_inline)) static inline int
+rx_available(volatile uint8_t *sr)
+{
+	return *sr & DW_SPI_STATUS_RFNE;
+}
+
+/**
+ * @brief Wait for data in RX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ */
+__attribute__((always_inline)) static inline void
+wait_rx_available(volatile uint8_t *sr)
+{
+	while (!rx_available(sr))
+		;
+}
+
+/**
+ * @brief Flush RX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ */
+__attribute__((always_inline)) static inline void
+flush_rx(volatile uint8_t *sr, volatile uint8_t *dr)
+{
+	while (*sr & DW_SPI_STATUS_RFNE)
+		*dr;
+}
+
+/**
+ * @brief Append variable number of bytes to TX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] word: Data to append.
+ * @param[in] bytes: Number of bytes to append.
+ */
+__attribute__((always_inline)) static inline void
+_send_bytes(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word,
+			int bytes)
+{
+	for (register int i = bytes - 1; i >= 0; i--) {
+		wait_tx_available(sr);
+		_send_byte(dr, (word >> (i * 8)) & 0xff);
+	}
+}
+
+/**
+ * @brief Append 8 bit value to TX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] word: Data to push.
+ */
+__attribute__((always_inline)) static inline void
+send_u8(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t byte)
+{
+	wait_tx_available(sr);
+	_send_byte(dr, byte);
+}
+
+/**
+ * @brief Append 24 bit value to TX FIFO.
+ *
+ * Used to send Flash addresses in 24 bit mode.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] word: Data to push.
+ */
+__attribute__((always_inline)) static inline void
+send_u24(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word)
+{
+	_send_bytes(sr, dr, word, 3);
+}
+
+/**
+ * @brief Append 32 bit value to TX FIFO.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] word: Data to push.
+ */
+__attribute__((always_inline)) static inline void
+send_u32(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word)
+{
+	_send_bytes(sr, dr, word, 4);
+}
+
+/**
+ * @brief Read chip status register.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] stat_cmd: Read status command.
+ * @return Chip status.
+ */
+__attribute__((always_inline)) static inline uint8_t
+read_status(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd)
+{
+	wait_tx_finish(sr);
+	flush_rx(sr, dr);
+	/*
+	 * Don't bother with wait_tx_available() as TX FIFO is empty
+	 * and we only send two bytes.
+	 */
+	_send_byte(dr, stat_cmd);
+	_send_byte(dr, 0); // Dummy write to push out read data.
+	wait_rx_available(sr);
+	rcv_byte(dr); // Dummy read to skip command byte.
+	wait_rx_available(sr);
+	return rcv_byte(dr);
+}
+
+/**
+ * @brief Enable Flash chip write.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] we_cmd: Write enable command.
+ */
+__attribute__((always_inline)) static inline void
+write_enable(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t we_cmd)
+{
+	wait_tx_finish(sr);
+	_send_byte(dr, we_cmd);
+}
+
+/**
+ * @brief Erase Flash sector.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] erase_cmd: Erase sector cmd.
+ * @param[in] address: Sector address.
+ * @param[in] four_byte_mode: Device is in 32 bit mode flag.
+ */
+__attribute__((always_inline)) static inline void
+erase_sector(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t erase_cmd,
+			 uint32_t address, uint8_t four_byte_mode)
+{
+	wait_tx_finish(sr);
+	_send_byte(dr, erase_cmd);
+	if (four_byte_mode)
+		send_u32(sr, dr, address);
+	else
+		send_u24(sr, dr, address);
+}
+
+/**
+ * @brief Wait for write enable flag.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] stat_cmd: Read status command.
+ * @param[in] we_mask: Write enable status mask.
+ */
+__attribute__((always_inline)) static inline void
+wait_write_enable(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd,
+				  uint8_t we_mask)
+{
+	while (!(read_status(sr, dr, stat_cmd) & we_mask))
+		;
+}
+
+/**
+ * @brief Wait while flash is busy.
+ *
+ * @param[in] sr: Pointer to SR register.
+ * @param[in] dr: Pointer to DR register.
+ * @param[in] stat_cmd: Read status command.
+ * @param[in] busy_mask: Flash busy mask.
+ */
+__attribute__((always_inline)) static inline void
+wait_busy(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd,
+		  uint8_t busy_mask)
+{
+	while (read_status(sr, dr, stat_cmd) & busy_mask)
+		;
+}
+
+#endif // _DW_SPI_H_

contrib/loaders/flash/dw-spi/mipsel-linux-gnu-check_fill.inc

@@ -0,0 +1,39 @@
+  0x0b, 0x00, 0x82, 0x88, 0x1f, 0x00, 0x8a, 0x88, 0x0f, 0x00, 0x83, 0x88,
+  0x17, 0x00, 0x86, 0x88, 0x08, 0x00, 0x82, 0x98, 0x1c, 0x00, 0x8a, 0x98,
+  0x0c, 0x00, 0x83, 0x98, 0x14, 0x00, 0x86, 0x98, 0x25, 0x38, 0x80, 0x00,
+  0x54, 0x00, 0x40, 0x10, 0xf8, 0xff, 0x09, 0x24, 0x00, 0x00, 0x64, 0x90,
+  0x05, 0x00, 0x84, 0x30, 0x04, 0x00, 0x84, 0x38, 0xfc, 0xff, 0x80, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30,
+  0x07, 0x00, 0x40, 0x50, 0x25, 0x00, 0xe5, 0x90, 0x00, 0x00, 0xc2, 0x90,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0xfc, 0xff, 0x40, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x25, 0x00, 0xe5, 0x90, 0x00, 0x00, 0x62, 0x90,
+  0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0xc5, 0xa0, 0x26, 0x00, 0xe2, 0x90, 0x45, 0x00, 0x40, 0x10,
+  0x03, 0x00, 0xe8, 0x88, 0x00, 0x00, 0xe8, 0x98, 0x18, 0x00, 0x05, 0x24,
+  0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10,
+  0x06, 0x10, 0xa8, 0x00, 0xff, 0x00, 0x42, 0x30, 0xf8, 0xff, 0xa5, 0x24,
+  0x00, 0x00, 0xc2, 0xa0, 0xf8, 0xff, 0xa9, 0x14, 0x05, 0x00, 0x0b, 0x24,
+  0x07, 0x00, 0xe8, 0x88, 0x04, 0x00, 0xe8, 0x98, 0x1e, 0x00, 0x00, 0x11,
+  0x25, 0x28, 0x00, 0x01, 0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30,
+  0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa0,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0x06, 0x00, 0x40, 0x50,
+  0xff, 0xff, 0xa5, 0x24, 0x00, 0x00, 0xc2, 0x90, 0x25, 0x00, 0x60, 0x51,
+  0x24, 0x00, 0xec, 0x90, 0xff, 0xff, 0x6b, 0x25, 0xff, 0xff, 0xa5, 0x24,
+  0xf1, 0xff, 0xa0, 0x14, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x51,
+  0x01, 0x00, 0x04, 0x24, 0x24, 0x00, 0xe5, 0x90, 0x00, 0x00, 0x62, 0x90,
+  0x08, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0xc2, 0x90, 0xff, 0x00, 0x42, 0x30, 0x04, 0x00, 0xa2, 0x14,
+  0xff, 0xff, 0x08, 0x25, 0xf7, 0xff, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x04, 0x24, 0x00, 0x00, 0x44, 0xa1, 0x0b, 0x00, 0xe2, 0x88,
+  0x01, 0x00, 0x4a, 0x25, 0x08, 0x00, 0xe2, 0x98, 0xff, 0xff, 0x42, 0x24,
+  0x0b, 0x00, 0xe2, 0xa8, 0x08, 0x00, 0xe2, 0xb8, 0x03, 0x00, 0xe4, 0x88,
+  0x07, 0x00, 0xe5, 0x88, 0x00, 0x00, 0xe4, 0x98, 0x04, 0x00, 0xe5, 0x98,
+  0x21, 0x20, 0x85, 0x00, 0x03, 0x00, 0xe4, 0xa8, 0xae, 0xff, 0x40, 0x14,
+  0x00, 0x00, 0xe4, 0xb8, 0x3f, 0x00, 0x00, 0x70, 0x08, 0x00, 0xe0, 0x03,
+  0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x42, 0x30, 0xed, 0xff, 0x82, 0x55,
+  0x00, 0x00, 0x44, 0xa1, 0xd9, 0xff, 0x00, 0x10, 0xff, 0xff, 0x08, 0x25,
+  0x00, 0x00, 0xe8, 0x98, 0x10, 0x00, 0x05, 0x24, 0x00, 0x00, 0x62, 0x90,
+  0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x06, 0x10, 0xa8, 0x00,
+  0xff, 0x00, 0x42, 0x30, 0xf8, 0xff, 0xa5, 0x24, 0x00, 0x00, 0xc2, 0xa0,
+  0xf8, 0xff, 0xa9, 0x14, 0x04, 0x00, 0x0b, 0x24, 0xbc, 0xff, 0x00, 0x10,
+  0x07, 0x00, 0xe8, 0x88

contrib/loaders/flash/dw-spi/mipsel-linux-gnu-erase.inc

@@ -0,0 +1,39 @@
+  0x0b, 0x00, 0x88, 0x88, 0x25, 0x28, 0x80, 0x00, 0x03, 0x00, 0x86, 0x88,
+  0x0f, 0x00, 0x82, 0x88, 0x17, 0x00, 0x84, 0x88, 0x08, 0x00, 0xa8, 0x98,
+  0x00, 0x00, 0xa6, 0x98, 0x0c, 0x00, 0xa2, 0x98, 0x5f, 0x00, 0x00, 0x11,
+  0x14, 0x00, 0xa4, 0x98, 0xf8, 0xff, 0x07, 0x24, 0x1d, 0x00, 0xa9, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38,
+  0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0xa0,
+  0x1c, 0x00, 0xaa, 0x90, 0x1f, 0x00, 0xa9, 0x90, 0x00, 0x00, 0x43, 0x90,
+  0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38, 0xfc, 0xff, 0x60, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30,
+  0x06, 0x00, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfc, 0xff, 0x60, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0xa0, 0x00, 0x00, 0x80, 0xa0,
+  0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, 0x00, 0x00, 0x43, 0x90,
+  0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x83, 0x90, 0x24, 0x18, 0x23, 0x01, 0xe4, 0xff, 0x60, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0xaa, 0x90, 0x21, 0x00, 0xa9, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38,
+  0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0xa0,
+  0x31, 0x00, 0x20, 0x11, 0x10, 0x00, 0x09, 0x24, 0x18, 0x00, 0x09, 0x24,
+  0x00, 0x00, 0x43, 0x90, 0x02, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10,
+  0x06, 0x18, 0x26, 0x01, 0xff, 0x00, 0x63, 0x30, 0xf8, 0xff, 0x29, 0x25,
+  0xf9, 0xff, 0x27, 0x15, 0x00, 0x00, 0x83, 0xa0, 0x1c, 0x00, 0xaa, 0x90,
+  0x20, 0x00, 0xa9, 0x90, 0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30,
+  0x04, 0x00, 0x63, 0x38, 0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0x06, 0x00, 0x60, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, 0x00, 0x00, 0x43, 0x90,
+  0x08, 0x00, 0x63, 0x30, 0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x8a, 0xa0, 0x00, 0x00, 0x80, 0xa0, 0x00, 0x00, 0x43, 0x90,
+  0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x83, 0x90, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30,
+  0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90,
+  0x24, 0x18, 0x23, 0x01, 0xe4, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00,
+  0x07, 0x00, 0xa3, 0x88, 0xff, 0xff, 0x08, 0x25, 0x04, 0x00, 0xa3, 0x98,
+  0xa4, 0xff, 0x00, 0x15, 0x21, 0x30, 0xc3, 0x00, 0x3f, 0x00, 0x00, 0x70,
+  0x08, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90,
+  0x02, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x06, 0x18, 0x26, 0x01,
+  0xff, 0x00, 0x63, 0x30, 0xf8, 0xff, 0x29, 0x25, 0xf9, 0xff, 0x27, 0x15,
+  0x00, 0x00, 0x83, 0xa0, 0xd1, 0xff, 0x00, 0x10, 0x1c, 0x00, 0xaa, 0x90

contrib/loaders/flash/dw-spi/mipsel-linux-gnu-program.inc

@@ -0,0 +1,51 @@
+  0x13, 0x00, 0x88, 0x88, 0x25, 0x30, 0x80, 0x00, 0x0b, 0x00, 0x85, 0x88,
+  0x17, 0x00, 0x82, 0x88, 0x1f, 0x00, 0x84, 0x88, 0x10, 0x00, 0xc8, 0x98,
+  0x08, 0x00, 0xc5, 0x98, 0x14, 0x00, 0xc2, 0x98, 0x1c, 0x00, 0xc4, 0x98,
+  0x78, 0x00, 0x00, 0x11, 0xf8, 0xff, 0x07, 0x24, 0x25, 0x00, 0xc9, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38,
+  0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0xa0,
+  0x24, 0x00, 0xca, 0x90, 0x27, 0x00, 0xc9, 0x90, 0x00, 0x00, 0x43, 0x90,
+  0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38, 0xfc, 0xff, 0x60, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30,
+  0x06, 0x00, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfc, 0xff, 0x60, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0xa0, 0x00, 0x00, 0x80, 0xa0,
+  0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, 0x00, 0x00, 0x43, 0x90,
+  0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x83, 0x90, 0x24, 0x18, 0x23, 0x01, 0xe4, 0xff, 0x60, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30,
+  0x04, 0x00, 0x63, 0x38, 0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00,
+  0x26, 0x00, 0xc9, 0x90, 0x00, 0x00, 0x43, 0x90, 0x02, 0x00, 0x63, 0x30,
+  0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0xa0,
+  0x29, 0x00, 0xc3, 0x90, 0x47, 0x00, 0x60, 0x10, 0x03, 0x00, 0xca, 0x88,
+  0x00, 0x00, 0xca, 0x98, 0x18, 0x00, 0x09, 0x24, 0x00, 0x00, 0x43, 0x90,
+  0x02, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10, 0x06, 0x18, 0x2a, 0x01,
+  0xff, 0x00, 0x63, 0x30, 0xf8, 0xff, 0x29, 0x25, 0x00, 0x00, 0x83, 0xa0,
+  0xf8, 0xff, 0x27, 0x15, 0x25, 0x58, 0x00, 0x01, 0x07, 0x00, 0xc3, 0x88,
+  0x04, 0x00, 0xc3, 0x98, 0x2b, 0x48, 0x03, 0x01, 0x0a, 0x58, 0x69, 0x00,
+  0x0d, 0x00, 0x60, 0x11, 0x21, 0x50, 0xab, 0x00, 0x00, 0x00, 0xa9, 0x90,
+  0x01, 0x00, 0xa5, 0x24, 0x00, 0x00, 0x43, 0x90, 0x02, 0x00, 0x63, 0x30,
+  0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0xa0,
+  0xf9, 0xff, 0xaa, 0x54, 0x00, 0x00, 0xa9, 0x90, 0x07, 0x00, 0xc3, 0x88,
+  0x23, 0x40, 0x0b, 0x01, 0x04, 0x00, 0xc3, 0x98, 0x03, 0x00, 0xc9, 0x88,
+  0x00, 0x00, 0xc9, 0x98, 0x21, 0x18, 0x23, 0x01, 0x03, 0x00, 0xc3, 0xa8,
+  0x00, 0x00, 0xc3, 0xb8, 0x24, 0x00, 0xca, 0x90, 0x28, 0x00, 0xc9, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x05, 0x00, 0x63, 0x30, 0x04, 0x00, 0x63, 0x38,
+  0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x90,
+  0x08, 0x00, 0x63, 0x30, 0x06, 0x00, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x83, 0x90, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30,
+  0xfc, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0xa0,
+  0x00, 0x00, 0x80, 0xa0, 0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30,
+  0xfd, 0xff, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90,
+  0x00, 0x00, 0x43, 0x90, 0x08, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x90, 0x24, 0x18, 0x23, 0x01,
+  0xe4, 0xff, 0x60, 0x14, 0x00, 0x00, 0x00, 0x00, 0x8b, 0xff, 0x00, 0x55,
+  0x25, 0x00, 0xc9, 0x90, 0x3f, 0x00, 0x00, 0x70, 0x08, 0x00, 0xe0, 0x03,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xca, 0x98, 0x10, 0x00, 0x09, 0x24,
+  0x00, 0x00, 0x43, 0x90, 0x02, 0x00, 0x63, 0x30, 0xfd, 0xff, 0x60, 0x10,
+  0x06, 0x18, 0x2a, 0x01, 0xff, 0x00, 0x63, 0x30, 0xf8, 0xff, 0x29, 0x25,
+  0x00, 0x00, 0x83, 0xa0, 0xf8, 0xff, 0x27, 0x15, 0x25, 0x58, 0x00, 0x01,
+  0x07, 0x00, 0xc3, 0x88, 0x04, 0x00, 0xc3, 0x98, 0x2b, 0x48, 0x03, 0x01,
+  0x0a, 0x58, 0x69, 0x00, 0xbb, 0xff, 0x60, 0x15, 0x21, 0x50, 0xab, 0x00,
+  0xc6, 0xff, 0x00, 0x10, 0x03, 0x00, 0xc9, 0x88

contrib/loaders/flash/dw-spi/mipsel-linux-gnu-read.inc

@@ -0,0 +1,33 @@
+  0x0f, 0x00, 0x87, 0x88, 0x07, 0x00, 0x88, 0x88, 0x13, 0x00, 0x83, 0x88,
+  0x1b, 0x00, 0x85, 0x88, 0x0c, 0x00, 0x87, 0x98, 0x04, 0x00, 0x88, 0x98,
+  0x10, 0x00, 0x83, 0x98, 0x18, 0x00, 0x85, 0x98, 0x00, 0x00, 0x62, 0x90,
+  0x05, 0x00, 0x42, 0x30, 0x04, 0x00, 0x42, 0x38, 0xfc, 0xff, 0x40, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30,
+  0x07, 0x00, 0x40, 0x50, 0x20, 0x00, 0x86, 0x90, 0x00, 0x00, 0xa2, 0x90,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0xfc, 0xff, 0x40, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x86, 0x90, 0x00, 0x00, 0x62, 0x90,
+  0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0xa6, 0xa0, 0x21, 0x00, 0x82, 0x90, 0x35, 0x00, 0x40, 0x10,
+  0x03, 0x00, 0x82, 0x88, 0x18, 0x00, 0x06, 0x24, 0xf8, 0xff, 0x09, 0x24,
+  0x00, 0x00, 0x82, 0x98, 0x25, 0x20, 0x40, 0x00, 0x00, 0x00, 0x62, 0x90,
+  0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10, 0x06, 0x10, 0xc4, 0x00,
+  0xff, 0x00, 0x42, 0x30, 0xf8, 0xff, 0xc6, 0x24, 0xf9, 0xff, 0xc9, 0x14,
+  0x00, 0x00, 0xa2, 0xa0, 0x05, 0x00, 0x06, 0x24, 0x23, 0x00, 0xe0, 0x10,
+  0x25, 0x20, 0xe0, 0x00, 0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30,
+  0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xa0,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0x06, 0x00, 0x40, 0x50,
+  0xff, 0xff, 0x84, 0x24, 0x00, 0x00, 0xa2, 0x90, 0x14, 0x00, 0xc0, 0x50,
+  0x00, 0x00, 0x02, 0xa1, 0xff, 0xff, 0xc6, 0x24, 0xff, 0xff, 0x84, 0x24,
+  0xf1, 0xff, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0xe0, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30,
+  0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa2, 0x90,
+  0x03, 0x00, 0xc0, 0x50, 0xff, 0xff, 0xe7, 0x24, 0xf8, 0xff, 0x00, 0x10,
+  0xff, 0xff, 0xc6, 0x24, 0x06, 0x00, 0xe0, 0x10, 0x00, 0x00, 0x02, 0xa1,
+  0xf4, 0xff, 0x00, 0x10, 0x01, 0x00, 0x08, 0x25, 0xff, 0xff, 0xe7, 0x24,
+  0xec, 0xff, 0x00, 0x10, 0x01, 0x00, 0x08, 0x25, 0x3f, 0x00, 0x00, 0x70,
+  0x08, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x06, 0x24,
+  0xf8, 0xff, 0x09, 0x24, 0x00, 0x00, 0x82, 0x98, 0x25, 0x20, 0x40, 0x00,
+  0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10,
+  0x06, 0x10, 0xc4, 0x00, 0xff, 0x00, 0x42, 0x30, 0xf8, 0xff, 0xc6, 0x24,
+  0xf9, 0xff, 0xc9, 0x14, 0x00, 0x00, 0xa2, 0xa0, 0xcc, 0xff, 0x00, 0x10,
+  0x04, 0x00, 0x06, 0x24

contrib/loaders/flash/dw-spi/mipsel-linux-gnu-transaction.inc

@@ -0,0 +1,21 @@
+  0x03, 0x00, 0x85, 0x88, 0x0b, 0x00, 0x88, 0x88, 0x0f, 0x00, 0x83, 0x88,
+  0x17, 0x00, 0x86, 0x88, 0x00, 0x00, 0x85, 0x98, 0x08, 0x00, 0x88, 0x98,
+  0x0c, 0x00, 0x83, 0x98, 0x14, 0x00, 0x86, 0x98, 0x00, 0x00, 0x62, 0x90,
+  0x05, 0x00, 0x42, 0x30, 0x04, 0x00, 0x42, 0x38, 0xfc, 0xff, 0x40, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30,
+  0x06, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x90,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0xfc, 0xff, 0x40, 0x14,
+  0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00,
+  0x25, 0x38, 0xa0, 0x00, 0x21, 0x40, 0x05, 0x01, 0x00, 0x00, 0xa9, 0x90,
+  0x01, 0x00, 0xa5, 0x24, 0x00, 0x00, 0x62, 0x90, 0x02, 0x00, 0x42, 0x30,
+  0xfd, 0xff, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc9, 0xa0,
+  0x1c, 0x00, 0x82, 0x90, 0x08, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0x04, 0x00, 0x40, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x90, 0x01, 0x00, 0xe7, 0x24,
+  0xff, 0xff, 0xe2, 0xa0, 0xef, 0xff, 0xa8, 0x54, 0x00, 0x00, 0xa9, 0x90,
+  0x1c, 0x00, 0x82, 0x90, 0x0c, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x2b, 0x10, 0xe8, 0x00, 0x09, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x62, 0x90, 0x08, 0x00, 0x42, 0x30, 0xfd, 0xff, 0x40, 0x10,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x90, 0x01, 0x00, 0xe7, 0x24,
+  0xf9, 0xff, 0x07, 0x15, 0xff, 0xff, 0xe2, 0xa0, 0x3f, 0x00, 0x00, 0x70,
+  0x08, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00

contrib/loaders/flash/fespi/riscv_fespi.c

@@ -103,7 +103,7 @@ static void fespi_disable_hw_mode(volatile uint32_t *ctrl_base);
 static void fespi_enable_hw_mode(volatile uint32_t *ctrl_base);
 static int fespi_wip(volatile uint32_t *ctrl_base);
 static int fespi_write_buffer(volatile uint32_t *ctrl_base,
-		const uint8_t *buffer, unsigned offset, unsigned len,
+		const uint8_t *buffer, unsigned int offset, unsigned int len,
 		uint32_t flash_info);
 
 /* Can set bits 3:0 in result. */
@@ -113,7 +113,7 @@ static int fespi_write_buffer(volatile uint32_t *ctrl_base,
  *               after pprog_cmd
  */
 int flash_fespi(volatile uint32_t *ctrl_base, uint32_t page_size,
-		const uint8_t *buffer, unsigned offset, uint32_t count,
+		const uint8_t *buffer, unsigned int offset, uint32_t count,
 		uint32_t flash_info)
 {
 	int result;
@@ -163,12 +163,12 @@ err:
 	return result;
 }
 
-static uint32_t fespi_read_reg(volatile uint32_t *ctrl_base, unsigned address)
+static uint32_t fespi_read_reg(volatile uint32_t *ctrl_base, unsigned int address)
 {
 	return ctrl_base[address / 4];
 }
 
-static void fespi_write_reg(volatile uint32_t *ctrl_base, unsigned address, uint32_t value)
+static void fespi_write_reg(volatile uint32_t *ctrl_base, unsigned int address, uint32_t value)
 {
 	ctrl_base[address / 4] = value;
 }
@@ -188,7 +188,7 @@ static void fespi_enable_hw_mode(volatile uint32_t *ctrl_base)
 /* Can set bits 7:4 in result. */
 static int fespi_txwm_wait(volatile uint32_t *ctrl_base)
 {
-	unsigned timeout = TIMEOUT;
+	unsigned int timeout = TIMEOUT;
 
 	while (timeout--) {
 		uint32_t ip = fespi_read_reg(ctrl_base, FESPI_REG_IP);
@@ -209,7 +209,7 @@ static void fespi_set_dir(volatile uint32_t *ctrl_base, bool dir)
 /* Can set bits 11:8 in result. */
 static int fespi_tx(volatile uint32_t *ctrl_base, uint8_t in)
 {
-	unsigned timeout = TIMEOUT;
+	unsigned int timeout = TIMEOUT;
 
 	while (timeout--) {
 		uint32_t txfifo = fespi_read_reg(ctrl_base, FESPI_REG_TXFIFO);
@@ -224,7 +224,7 @@ static int fespi_tx(volatile uint32_t *ctrl_base, uint8_t in)
 /* Can set bits 15:12 in result. */
 static int fespi_rx(volatile uint32_t *ctrl_base, uint8_t *out)
 {
-	unsigned timeout = TIMEOUT;
+	unsigned int timeout = TIMEOUT;
 
 	while (timeout--) {
 		uint32_t value = fespi_read_reg(ctrl_base, FESPI_REG_RXFIFO);
@@ -252,7 +252,7 @@ static int fespi_wip(volatile uint32_t *ctrl_base)
 	if (result != ERROR_OK)
 		return result | ERROR_STACK(0x20000);
 
-	unsigned timeout = TIMEOUT;
+	unsigned int timeout = TIMEOUT;
 	while (timeout--) {
 		result = fespi_tx(ctrl_base, 0);
 		if (result != ERROR_OK)
@@ -273,7 +273,7 @@ static int fespi_wip(volatile uint32_t *ctrl_base)
 
 /* Can set bits 23:20 in result. */
 static int fespi_write_buffer(volatile uint32_t *ctrl_base,
-		const uint8_t *buffer, unsigned offset, unsigned len,
+		const uint8_t *buffer, unsigned int offset, unsigned int len,
 		uint32_t flash_info)
 {
 	int result = fespi_tx(ctrl_base, SPIFLASH_WRITE_ENABLE);
@@ -304,7 +304,7 @@ static int fespi_write_buffer(volatile uint32_t *ctrl_base,
 	if (result != ERROR_OK)
 		return result | ERROR_STACK(0x600000);
 
-	for (unsigned i = 0; i < len; i++) {
+	for (unsigned int i = 0; i < len; i++) {
 		result = fespi_tx(ctrl_base, buffer[i]);
 		if (result != ERROR_OK)
 			return result | ERROR_STACK(0x700000);

contrib/loaders/flash/hpmicro/Makefile

@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2023 HPMicro
+#
+BIN2C = ../../../../src/helper/bin2char.sh
+
+
+PROJECT=hpm_xpi_flash
+CROSS_COMPILE ?= riscv32-unknown-elf-
+CC=$(CROSS_COMPILE)gcc
+AS=$(CROSS_COMPILE)gcc
+OBJCOPY=$(CROSS_COMPILE)objcopy
+OBJDUMP=$(CROSS_COMPILE)objdump
+LD=$(CROSS_COMPILE)ld
+LDSCRIPT=linker.ld
+
+OPT=-O3
+
+ASFLAGS=
+CFLAGS=$(OPT) -fomit-frame-pointer -Wall
+LDFLAGS=-nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map -static -Wl,--gc-sections
+OBJS=$(ASRC:.S=.o) $(SRC:.c=.o)
+
+SRC=openocd_flash_algo.c
+ASRC=func_table.S
+
+all: $(OBJS) $(PROJECT).elf $(PROJECT).bin $(PROJECT).lst $(PROJECT).inc
+
+%o: %c
+	@$(CC) -c $(CFLAGS) -I . $< -o $@
+
+%o: %S
+	@$(AS) -c $(ASFLAGS) -I . $< -o $@
+
+%elf: $(OBJS)
+	@$(CC) $(OBJS) $(LDFLAGS) -o $@
+
+%lst: %elf
+	@$(OBJDUMP) -h -S $< > $@
+
+%bin: %elf
+	@$(OBJCOPY) -Obinary $< $@
+
+%inc: %bin
+	$(BIN2C) < $< > $@
+
+clean:
+	@-rm -f *.o *.elf *.lst *.bin *.inc
+
+.PHONY:	all clean
+
+.INTERMEDIATE: $(patsubst %.S,%.o,$(SRCS)) $(patsubst %.S,%.elf,$(SRCS)) $(patsubst %.S,%.bin,$(SRCS))

contrib/loaders/flash/hpmicro/README

@@ -0,0 +1,7 @@
+The loader relies on the romapi provided by HPMicro devices.
+
+- hpm_common.h and all the hpm_romapi_*.c/h are reused from hpm_sdk
+(v1.9.0 https://github.com/hpmicro/hpm_sdk/releases).
+
+Due to different coding rules, these source code needs to be updated
+accordingly to pass the coding rule check for openocd.

contrib/loaders/flash/hpmicro/func_table.S

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 HPMicro
+ */
+  .section .func_table, "ax"
+  .global _init
+_init:
+  jal flash_init
+  ebreak
+  jal flash_erase
+  ebreak
+  jal flash_program
+  ebreak
+  jal flash_read
+  ebreak
+  jal flash_get_info
+  ebreak
+  jal flash_erase_chip
+  ebreak
+  jal flash_deinit
+  ebreak

contrib/loaders/flash/hpmicro/hpm_common.h

@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ */
+
+#ifndef _HPM_COMMON_H
+#define _HPM_COMMON_H
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+/**
+ *
+ * @brief COMMON driver APIs
+ * @defgroup common_interface COMMON driver APIs
+ * @{
+ *
+ */
+
+#define __R volatile const /* Define "read-only" permission */
+#define __RW volatile      /* Define "read-write" permission */
+#define __W volatile       /* Define "write-only" permission */
+
+#ifndef __I
+#define __I __R
+#endif
+
+#ifndef __IO
+#define __IO __RW
+#endif
+
+#ifndef __O
+#define __O __W
+#endif
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(a)   (sizeof(a) / sizeof((a)[0]))
+#endif
+
+#define HPM_BITSMASK(val, offset) ((uint32_t)(val) << (offset))
+#define IS_HPM_BITMASK_SET(val, mask) (((uint32_t)(val) & (uint32_t)(mask)) != 0U)
+#define IS_HPM_BIT_SET(val, offset) (((uint32_t)(val) & (1UL << (offset))) != 0U)
+#define IS_HPM_BITMASK_CLR(val, mask) (((uint32_t)(val) & (uint32_t)(mask)) == 0U)
+#define IS_HPM_BIT_CLR(val, offset) (((uint32_t)(val) & (1UL << (offset))) == 0U)
+
+#define HPM_BREAK_IF(cond)  do {if (cond) break; } while (0)
+#define HPM_CONTINUE_IF(cond) do {if (cond) continue; } while (0)
+
+#define HPM_CHECK_RET(x)               \
+	do {                               \
+		stat = (x);                    \
+		if (status_success != stat) { \
+			return stat;               \
+		}                              \
+	} while (false)
+
+#define SIZE_1KB (1024UL)
+#define SIZE_1MB (1048576UL)
+
+typedef uint32_t hpm_stat_t;
+
+/* @brief Enum definition for the Status group
+ * Rule:
+ *  [Group] 0-999 for the SoC driver and the corresponding components
+ *       1000 or above for the application status group
+ *  [Code]  Valid value: 0-999
+ *
+ */
+#define MAKE_STATUS(group, code) ((uint32_t)(group) * 1000U + (uint32_t)(code))
+/* @brief System status group definitions */
+enum {
+	status_group_common = 0,
+	status_group_uart = 1,
+	status_group_i2c = 2,
+	status_group_spi = 3,
+	status_group_usb = 4,
+	status_group_i2s = 5,
+	status_group_xpi = 6,
+	status_group_l1c,
+	status_group_dma,
+	status_group_femc,
+	status_group_sdp,
+	status_group_xpi_nor,
+	status_group_otp,
+	status_group_lcdc,
+	status_group_mbx,
+	status_group_rng,
+	status_group_pdma,
+	status_group_wdg,
+	status_group_pmic_sec,
+	status_group_can,
+	status_group_sdxc,
+	status_group_pcfg,
+	status_group_clk,
+	status_group_pllctl,
+	status_group_pllctlv2,
+	status_group_ffa,
+	status_group_mcan,
+
+	status_group_middleware_start = 500,
+	status_group_sdmmc = status_group_middleware_start,
+	status_group_audio_codec,
+	status_group_dma_manager,
+};
+
+/* @brief Common status code definitions */
+enum {
+	status_success = MAKE_STATUS(status_group_common, 0),
+	status_fail = MAKE_STATUS(status_group_common, 1),
+	status_invalid_argument = MAKE_STATUS(status_group_common, 2),
+	status_timeout = MAKE_STATUS(status_group_common, 3),
+};
+
+#if defined(__GNUC__)
+
+/* alway_inline */
+#define ATTR_ALWAYS_INLINE __attribute__((always_inline))
+
+/* weak */
+#define ATTR_WEAK __attribute__((weak))
+
+/* alignment */
+#define ATTR_ALIGN(alignment) __attribute__((aligned(alignment)))
+
+/* place var_declare at section_name, e.x. PLACE_AT(".target_section", var); */
+#define ATTR_PLACE_AT(section_name) __attribute__((section(section_name)))
+
+#define ATTR_PLACE_AT_WITH_ALIGNMENT(section_name, alignment) \
+ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment)
+
+#define ATTR_PLACE_AT_NONCACHEABLE ATTR_PLACE_AT(".noncacheable.bss")
+#define ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(alignment) \
+	ATTR_PLACE_AT_NONCACHEABLE ATTR_ALIGN(alignment)
+
+#define ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_PLACE_AT(".noncacheable.bss")
+#define ATTR_PLACE_AT_NONCACHEABLE_BSS_WITH_ALIGNMENT(alignment) \
+	ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_ALIGN(alignment)
+
+/* initialize variable x with y using PLACE_AT_NONCACHEABLE_INIT(x) = {y}; */
+#define ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_PLACE_AT(".noncacheable.init")
+#define ATTR_PLACE_AT_NONCACHEABLE_INIT_WITH_ALIGNMENT(alignment) \
+	ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_ALIGN(alignment)
+
+#define ATTR_RAMFUNC ATTR_PLACE_AT(".fast")
+#define ATTR_RAMFUNC_WITH_ALIGNMENT(alignment) \
+	ATTR_RAMFUNC ATTR_ALIGN(alignment)
+
+#define ATTR_SHARE_MEM ATTR_PLACE_AT(".sh_mem")
+
+#define NOP() __asm volatile("nop")
+#define WFI() __asm volatile("wfi")
+
+#define HPM_ATTR_MACHINE_INTERRUPT __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4)))
+
+#elif defined(__ICCRISCV__)
+
+/* alway_inline */
+#define ATTR_ALWAYS_INLINE __attribute__((always_inline))
+
+/* weak */
+#define ATTR_WEAK __weak
+
+/* alignment */
+#define ATTR_ALIGN(alignment) __attribute__((aligned(alignment)))
+
+/* place var_declare at section_name, e.x. PLACE_AT(".target_section", var); */
+#define ATTR_PLACE_AT(section_name) __attribute__((section(section_name)))
+
+#define ATTR_PLACE_AT_WITH_ALIGNMENT(section_name, alignment) \
+ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment)
+
+#define ATTR_PLACE_AT_NONCACHEABLE ATTR_PLACE_AT(".noncacheable.bss")
+#define ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(alignment) \
+	ATTR_PLACE_AT_NONCACHEABLE ATTR_ALIGN(alignment)
+
+#define ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_PLACE_AT(".noncacheable.bss")
+#define ATTR_PLACE_AT_NONCACHEABLE_BSS_WITH_ALIGNMENT(alignment) \
+	ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_ALIGN(alignment)
+
+/* initialize variable x with y using PLACE_AT_NONCACHEABLE_INIT(x) = {y}; */
+#define ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_PLACE_AT(".noncacheable.init")
+#define ATTR_PLACE_AT_NONCACHEABLE_INIT_WITH_ALIGNMENT(alignment) \
+	ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_ALIGN(alignment)
+
+#define ATTR_RAMFUNC ATTR_PLACE_AT(".fast")
+#define ATTR_RAMFUNC_WITH_ALIGNMENT(alignment) \
+	ATTR_RAMFUNC ATTR_ALIGN(alignment)
+
+#define ATTR_SHARE_MEM ATTR_PLACE_AT(".sh_mem")
+
+#define NOP() __asm volatile("nop")
+#define WFI() __asm volatile("wfi")
+
+#define HPM_ATTR_MACHINE_INTERRUPT __machine __interrupt
+
+#else
+#error Unknown toolchain
+#endif
+#endif /* _HPM_COMMON_H */

contrib/loaders/flash/hpmicro/hpm_romapi.h

@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ */
+
+#ifndef HPM_ROMAPI_H
+#define HPM_ROMAPI_H
+
+/**
+ * @brief ROM APIs
+ * @defgroup romapi_interface ROM APIs
+ * @{
+ */
+
+#include "hpm_common.h"
+#include "hpm_romapi_xpi_def.h"
+#include "hpm_romapi_xpi_soc_def.h"
+#include "hpm_romapi_xpi_nor_def.h"
+
+/***********************************************************************************************************************
+ *
+ *
+ *	  Definitions
+ *
+ *
+ **********************************************************************************************************************/
+
+/**
+ * @brief Bootloader API table
+ */
+struct bootloader_api_table_t {
+	/**< Bootloader API table: version */
+	const uint32_t version;
+	/**< Bootloader API table: copyright string address */
+	const char *copyright;
+	/**< Bootloader API table: run_bootloader API */
+	const uint32_t reserved0;
+	/**< Bootloader API table: otp driver interface address */
+	const uint32_t reserved1;
+	/**< Bootloader API table: xpi driver interface address */
+	const struct xpi_driver_interface_t *xpi_driver_if;
+	/**< Bootloader API table: xpi nor driver interface address */
+	const struct xpi_nor_driver_interface_t *xpi_nor_driver_if;
+	/**< Bootloader API table: xpi ram driver interface address */
+	const uint32_t reserved2;
+};
+
+/**< Bootloader API table Root */
+#define ROM_API_TABLE_ROOT ((const struct bootloader_api_table_t *)0x2001FF00U)
+
+#endif /* HPM_ROMAPI_H */

contrib/loaders/flash/hpmicro/hpm_romapi_xpi_def.h

@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/*
+ * Copyright (c) 2021 HPMicro
+ */
+#ifndef HPM_ROMAPI_XPI_DEF_H
+#define HPM_ROMAPI_XPI_DEF_H
+
+/**
+ * @brief XPI ROM APIs
+ * @defgroup xpi_interface XPI driver APIs
+ * @{
+ */
+
+#include "hpm_common.h"
+
+/**
+ * @brief XPI Read Sample Clock source options
+ */
+enum xpi_rxclksrc_type_t {
+	xpi_rxclksrc_internal_loopback = 0, /**< Internal loopback */
+	xpi_rxclksrc_dqs_loopback = 1,	  /**< Loopback from DQS pad */
+	xpi_rxclksrc_external_dqs = 3,	  /**< Read is driven by External DQS pad */
+};
+
+/**
+ * @brief XPI pad definitions
+ */
+#define XPI_1PAD	(0U)	/**< Single pad */
+#define XPI_2PADS   (1U)	/**< Dual pads */
+#define XPI_4PADS   (2U)	/**< Quad pads */
+#define XPI_8PADS   (3U)	/**< Octal pads */
+
+/**
+ * @brief XPI IO pin group options
+ */
+enum xpi_io_group_t {
+	xpi_io_1st_group,	   /**< First/Primary group */
+	xpi_io_2nd_group,	   /**< Second/Secondary group */
+};
+
+/**
+ * @brief XPI Transfer Channel type definitions
+ */
+enum xpi_xfer_channel_t {
+	xpi_xfer_channel_a1,					/**< The address is based on the device connected to Channel A1 */
+	xpi_xfer_channel_a2,					/**< The address is based on the device connected to Channel A2 */
+	xpi_xfer_channel_b1,					/**< The address is based on the device connected to Channel B1 */
+	xpi_xfer_channel_b2,					/**< The address is based on the device connected to Channel B2 */
+	xpi_xfer_channel_auto,				  /**< The channel is auto determined */
+};
+
+/**
+ * @brief XPI Channel definitions
+ */
+enum xpi_channel_t {
+	xpi_channel_a1,		/**< Port:  Channel A1 */
+	xpi_channel_a2,		/**< Port:  Channel A2 */
+	xpi_channel_b1,		/**< Port:  Channel B1 */
+	xpi_channel_b2,		/**< Port:  Channel B2 */
+};
+
+/**
+ * @brief XPI APB Transfer type
+ */
+enum xpi_apb_xfer_type_t {
+	xpi_apb_xfer_type_cmd,		  /**< APB Command Type: Command only */
+	xpi_apb_xfer_type_config,	   /**< APB Command Type: Configuration */
+	xpi_apb_xfer_type_read,		 /**< APB Command Type: Read */
+	xpi_apb_xfer_type_write,		/**< APB Command Type: Write */
+};
+
+/**
+ * @brief XPI Xfer Mode
+ */
+enum xpi_xfer_mode_t {
+	xpi_xfer_mode_polling,	  /**< Transfer mode: Polling */
+	xpi_xfer_mode_dma,		  /**< Transfer mode: DMA */
+	xpi_xfer_mode_interrupt,	/**< Transfer mode: Interrupt */
+};
+
+/**
+ * @brief XPI Xfer context
+ */
+struct xpi_xfer_ctx_t {
+	uint32_t addr;		  /**< device address for XPI transfer */
+	uint8_t channel;		   /**< channel for XPI transfer */
+	uint8_t cmd_type;	   /**< command type for XPI transfer */
+	uint8_t seq_idx;		/**< Sequence index for XPI transfer */
+	uint8_t seq_num;		/**< Sequence number for XPI transfer */
+	uint32_t *buf;		  /**< Buffer for XPI transfer */
+	uint32_t xfer_size;	 /**< Transfer size in bytes */
+};
+
+/**
+ * @brief XPI instruction sequence
+ */
+struct xpi_instr_seq_t {
+	uint32_t entry[4];
+};
+
+/**
+ * @brief XPI Phase definitions
+ */
+#define XPI_PHASE_STOP			(0x00U)   /**< Phase: Stop */
+#define XPI_PHASE_CMD_SDR		 (0x01U)   /**< Phase: Send CMD in SDR mode */
+#define XPI_PHASE_RADDR_SDR	   (0x02U)   /**< Phase: Send Row Address in SDR Mode */
+#define XPI_PHASE_CADDR_SDR	   (0x03U)   /**< Phase: Send Column Address in SDR Mode */
+#define XPI_PHASE_MODE4_SDR	   (0x06U)   /**< Phase: Send Mode 4 in SDR Mode */
+#define XPI_PHASE_MODE8_SDR	   (0x07U)   /**< Phase: Send Mode 8 in SDR Mode */
+#define XPI_PHASE_WRITE_SDR	   (0x08U)   /**< Phase: Write data in SDR Mode */
+#define XPI_PHASE_READ_SDR		(0x09U)   /**< Phase: Read data in SDR Mode */
+#define XPI_PHASE_DUMMY_SDR	   (0X0CU)   /**< Phase: Send Dummy in SDR Mode */
+#define XPI_PHASE_DUMMY_RWDS_SDR  (0x0DU)   /**< Phase: Send Dummy RWDS  in SDR Mode */
+
+#define XPI_PHASE_CMD_DDR		 (0x21U)   /**< Phase: Send CMD in DDR Mode */
+#define XPI_PHASE_RADDR_DDR	   (0x22U)   /**< Phase: Send Raw Address in DDR Mode */
+#define XPI_PHASE_CADDR_DDR	   (0x23U)   /**< Phase: Send Column address in DDR Mode */
+#define XPI_PHASE_MODE4_DDR	   (0x26U)   /**< Phase: Send Mode 4 in DDR Mode */
+#define XPI_PHASE_MODE8_DDR	   (0x27U)   /**< Phase: Send Mode 8 in DDR Mode */
+#define XPI_PHASE_WRITE_DDR	   (0x28U)   /**< Phase: Write data in DDR Mode */
+#define XPI_PHASE_READ_DDR		(0x29U)   /**< Phase: Read data in SDR Mode */
+#define XPI_PHASE_DUMMY_DDR	   (0x2CU)   /**< Phase: Send DUMMY in DDR Mode */
+#define XPI_PHASE_DUMMY_RWDS_DDR  (0x2DU)   /**< Phase: Send DUMMY RWDS in DDR Mode */
+
+/**
+ * @brief XPI API command error codes
+ */
+enum {
+	status_xpi_apb_jump_on_cs = MAKE_STATUS(status_group_xpi, 1),
+	status_xpi_apb_unknown_inst = MAKE_STATUS(status_group_xpi, 2),
+	status_xpi_apb_dummy_sdr_in_ddr_seq = MAKE_STATUS(status_group_xpi, 3),
+	status_xpi_apb_dummy_ddr_in_sdr_seq = MAKE_STATUS(status_group_xpi, 4),
+	status_xpi_apb_exceed_addr_range = MAKE_STATUS(status_group_xpi, 5),
+	status_xpi_apb_seq_timeout = MAKE_STATUS(status_group_xpi, 6),
+	status_xpi_apb_cross_boundary = MAKE_STATUS(status_group_xpi, 7),
+};
+
+/**
+ * @brief Delay line definitions
+ */
+enum {
+	xpi_dll_half_cycle = 0xFU,
+	xpi_dll_quarter_cycle = 0x7U,
+	xpi_dll_sdr_default_cycle = xpi_dll_half_cycle,
+	xpi_dll_ddr_default_cycle = xpi_dll_quarter_cycle,
+};
+
+/**
+ * @brief XPI configuration structure
+ */
+struct xpi_config_t {
+	uint8_t rxclk_src;					  /**< Read sample clock source */
+	uint8_t reserved0[7];				   /**< Reserved */
+	uint8_t tx_watermark_in_dwords;		 /**< Tx watermark in double words */
+	uint8_t rx_watermark_in_dwords;		 /**< Rx watermark in double words */
+	uint8_t enable_differential_clk;		/**< Enable differential clock */
+	uint8_t reserved1[5];				   /**< Reserved */
+	uint32_t access_flags;				  /**< Access flags */
+};
+
+/**
+ * @brief XPI Device Configuration structure
+ */
+struct xpi_device_config_t {
+	uint32_t size_in_kbytes;				/**< Device size in kbytes */
+	uint32_t serial_root_clk_freq;		  /**< XPI serial root clock frequency */
+
+	uint8_t enable_write_mask;			  /**< Enable write mask, typically for PSRAM/HyperRAM */
+	uint8_t data_valid_time;				/**< Data valid time, Unit 0.1ns */
+	uint8_t reserved0[2];
+
+	uint8_t cs_hold_time;				   /**< CS hold time, cycles in terms of FLASH clock */
+	uint8_t cs_setup_time;				  /**< CS setup time, cycles in terms of FLASH clock */
+	uint16_t cs_interval;				   /**< CS interval, cycles in terms of FLASH clock */
+
+	uint8_t reserved1;
+	uint8_t column_addr_size;			   /**< Column address bits */
+	uint8_t enable_word_address;			/**< Enable word address, for HyperFLASH/HyperRAM */
+	uint8_t dly_target;					 /**< Delay target */
+
+	uint8_t ahb_write_seq_idx;			  /**< AHB write sequence index */
+	uint8_t ahb_write_seq_num;			  /**< AHB write sequence number */
+	uint8_t ahb_read_seq_idx;			   /**< AHB read sequence index */
+	uint8_t ahb_read_seq_num;			   /**< AHB read sequence number */
+
+	uint8_t ahb_write_wait_interval;		/**< AHB write wait interval, in terms of FLASH clock */
+	uint8_t reserved2[3];
+};
+
+/**
+ * @brief SUB Instruction
+ * @param [in] phase Name
+ * @param [in] pad  Pad for Phase
+ * @param [in] op   Operand for Phase
+ */
+#define SUB_INSTR(phase, pad, op) ((uint32_t)(((uint16_t)(phase) << 10) | ((uint16_t)(pad) << 8) | ((uint16_t)(op))))
+/**
+ * @brief Generate a single word INSTRUCTION sequence word
+ * @note  Here intentionally use the MACRO because when the arguments are constant value, the compiler
+ *		can generate the const entry word during pre-processing
+ */
+#define XPI_INSTR_SEQ(phase0, pad0, op0, phase1, pad1, op1) \
+	(SUB_INSTR(phase0, pad0, op0) | (SUB_INSTR(phase1, pad1, op1) << 16))
+
+struct xpi_ahb_buffer_cfg_t {
+	struct {
+		uint8_t priority;				   /* Offset: 0x00 */
+		uint8_t master_idx;				 /* Offset: 0x01 */
+		uint8_t buf_size_in_dword;		  /* Offset: 0x02 */
+		bool enable_prefetch;			   /* Offset: 0x03 */
+	} entry[8];
+};
+
+/**
+ * @brief XPI driver interface
+ */
+struct xpi_driver_interface_t {
+	/**< XPI driver interface: version */
+	uint32_t version;
+	/**< XPI driver interface: get default configuration */
+	hpm_stat_t (*get_default_config)(struct xpi_config_t *xpi_config);
+	/**< XPI driver interface: get default device configuration */
+	hpm_stat_t (*get_default_device_config)(struct xpi_device_config_t *dev_config);
+	/**< XPI driver interface: initialize the XPI using xpi_config */
+	hpm_stat_t (*init)(uint32_t *base, struct xpi_config_t *xpi_config);
+	/**< XPI driver interface: configure the AHB buffer */
+	hpm_stat_t (*config_ahb_buffer)(uint32_t *base, struct xpi_ahb_buffer_cfg_t *ahb_buf_cfg);
+	/**< XPI driver interface: configure the device */
+	hpm_stat_t (*config_device)(uint32_t *base, struct xpi_device_config_t *dev_cfg, enum xpi_channel_t channel);
+	/**< XPI driver interface: update instruction talbe */
+	hpm_stat_t (*update_instr_table)(uint32_t *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num);
+	/**< XPI driver interface: transfer command/data using block interface */
+	hpm_stat_t (*transfer_blocking)(uint32_t *base, struct xpi_xfer_ctx_t *xfer);
+	/**< Software reset the XPI controller */
+	void (*software_reset)(uint32_t *base);
+	/**< XPI driver interface: Check whether IP is idle */
+	bool (*is_idle)(uint32_t *base);
+	/**< XPI driver interface: update delay line setting */
+	void (*update_dllcr)(uint32_t *base,
+						 uint32_t serial_root_clk_freq,
+						 uint32_t data_valid_time,
+						 enum xpi_channel_t channel,
+						 uint32_t dly_target);
+	/**< XPI driver interface: Get absolute address for APB transfer */
+	hpm_stat_t
+	(*get_abs_apb_xfer_addr)(uint32_t *base, enum xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr);
+};
+
+/**
+ * @}
+ */
+
+#endif /* HPM_ROMAPI_XPI_DEF_H */

contrib/loaders/flash/hpmicro/hpm_romapi_xpi_nor_def.h

@@ -0,0 +1,426 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/*
+ * Copyright (c) 2021 HPMicro
+ */
+#ifndef HPM_ROMAPI_XPI_NOR_DEF_H
+#define HPM_ROMAPI_XPI_NOR_DEF_H
+
+/**
+ * @brief XPI NOR ROM APIs
+ * @defgroup xpi_nor_interface XPI NOR driver APIs
+ * @ingroup romapi_interfaces
+ * @{
+ */
+
+#include "hpm_common.h"
+#include "hpm_romapi_xpi_def.h"
+
+#define XPI_NOR_CFG_TAG 0x524f4E58U /**< ASCII: "XNOR" */
+
+/**
+ * @brief XPI NOR properties
+ */
+enum {
+	xpi_nor_property_total_size,							/**< Total size in bytes */
+	xpi_nor_property_page_size,							 /**< Page size in bytes */
+	xpi_nor_property_sector_size,						   /**<sector size in bytes */
+	xpi_nor_property_block_size,							/**< block size in bytes */
+	xpi_nor_property_max = xpi_nor_property_block_size,
+};
+
+/**
+ * @brief XPI NOR safe frequency option
+ */
+enum {
+	xpi_nor_clk_safe_clk_freq = 1,
+};
+
+/**
+ * @brief XPI NOR miscellaneous options
+ */
+enum {
+	xpi_nor_option_misc_spi_only = 1,		   /**< SPI only */
+	xpi_nor_option_misc_internal_loopback = 2,  /**< Internal loopback mode */
+	xpi_nor_option_misc_ext_dqs = 3,			/**< External DQS pin */
+};
+
+/**
+ * @brief XPI NOR connection option
+ */
+enum {
+	xpi_nor_connection_sel_chna_cs0,			   /**< Channel A, CS0 */
+	xpi_nor_connection_sel_chnb_cs0,			   /**< Channel B, CS0 */
+	xpi_nor_connection_sel_chna_cs0_chnb_cs0,	 /**< Channel A + Channel B, CS0 */
+	xpi_nor_connection_sel_chna_cs0_cs1,		   /**< Channel A, CS0 + CS1 */
+	xpi_nor_connection_sel_chnb_cs0_cs1			/**< Channel B, CS0 + CS1 */
+};
+
+/**
+ * @brief QE bit enable sequence option
+ */
+enum xpi_nor_quad_enable_seq_t {
+	xpi_nor_quad_en_auto_or_ignore = 0U,						/**< Auto enable or ignore */
+	xpi_nor_quad_en_set_bit6_in_status_reg1 = 1U,			   /**< QE bit is at bit6 in Status register 1 */
+	xpi_nor_quad_en_set_bit1_in_status_reg2 = 2U,			   /**< QE bit is at bit1 in Status register 2 register 2 */
+	xpi_nor_quad_en_set_bit7_in_status_reg2 = 3U,			   /**< QE bit is at bit7 in Status register 2 */
+	xpi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd = 4U,   /**< QE bit is in status register 2 via CMD 0x31 */
+};
+
+/**
+ * @brief XPI working mode
+ */
+enum xpi_working_mode_t {
+	xpi_working_mode_extend_spi,	/**< XPI works in extended SPI mode, including 1-1-1, 1-2-2, 1-4-4, 1-8-8 */
+	xpi_working_mode_xpi,		   /**< XPI works in XPI mode, including, 1-1-1, 2-2-2, 4-4-4, 8-8-8 */
+	xpi_working_mode_hyperbus,	  /**< XPI works in HyperBus mode */
+};
+
+/**
+ * @brief XPI NOR configuration command type
+ */
+enum xpi_nor_cfg_cmd_type_t {
+	xpi_nor_cfg_cmd_type_no_cfg = 0U,   /**< No configuration */
+	xpi_nor_cfg_cmd_type_generic = 1U,  /**< Generic configuration */
+	xpi_nor_cfg_cmd_type_spi2xpi = 2U,  /**< SPI to XPI mode */
+	xpi_nor_cfg_cmd_type_xpi2spi = 3U,  /**< XPI to SPI mode */
+};
+
+/**
+ * @brief XPI NOR probe options
+ */
+enum xpi_nor_probe_t {
+	xpi_nor_probe_sfdp_sdr = 0U,	/**< Probe FLASH using SFDP and set FLASH to SDR mode */
+	xpi_nor_probe_sfdp_ddr = 1U,	/**< Probe FLASH using SDP and set FLASH to DDR mode */
+	xpi_nor_quad_read_0xeb = 2U,	/**< Set FLASH to default Quad I/O read in SDR mode */
+	xpi_nor_dual_read_0xbb = 3U,	/**< Set FLASH to default Dual I/O read in SDR mode */
+	xpi_nor_hyperbus_1v8 = 4U,	  /**< Probe FLASH using HyperBus in 1.8V voltage */
+	xpi_nor_hyperbus_3v0 = 5U,	  /**< Probe FLASH using HyperBus in 3.0V voltage */
+	xpi_nor_octabus_ddr = 6U,	   /**< Probe FLASH using Macronix OctaBus and configure FLASH to OPI DDR mode */
+	xpi_nor_octabus_sdr = 7U,	   /**< Probe FLASH using Macronix OctaBus and configure FLASH to OPI SDR mode */
+	xpi_nor_xccela_ddr = 8U,		/**< Probe FLASH using Xccela Protocol and configure FLASH to OPI DDR mode */
+	xpi_nor_xccela_sdr = 9U,		/**< Probe FLASH using Xccela Protocol and configure FLASH to SDR mode */
+	xpi_nor_ecoxip_ddr = 10U,	   /**< Probe FLASH using EcoXiP Protocol and configure FLASH to OPI DDR mode */
+	xpi_nor_ecoxip_sdr = 11U,	   /**< Probe FLASH using EcoXiP Protocol and configure FLASH to SDR mode */
+};
+
+/**
+ * @brief Standard XPI NOR seuqnce index definitions
+ */
+enum xpi_std_nor_instr_idx_t {
+	xpi_std_nor_seq_idx_read = 0U,					 /**< 0 - Read */
+	xpi_std_nor_seq_idx_page_program = 1U,			 /**< 1 - Page Program */
+	xpi_std_nor_seq_idx_read_status = 2U,			  /**< 2 - Read Status */
+	xpi_std_nor_seq_idx_read_status_xpi = 3U,		  /**< 3 - Read Status in xSPI mode */
+	xpi_std_nor_seq_idx_write_enable = 4U,			 /**< 4 - Write Enable */
+	xpi_std_nor_seq_idx_write_enable_xpi = 5U,		 /**< 5 - Write Enable in xSPI mode */
+	xpi_std_nor_seq_idx_erase_sector = 6U,			 /**< 6 - Erase sector */
+	xpi_std_nor_seq_idx_erase_block = 7U,			  /**< 7 - Erase block */
+	xpi_std_nor_seq_idx_erase_chip = 8U,			   /**< 8 - Erase full chip */
+	xpi_std_nor_seq_idx_max = 9,					   /**< 9 */
+};
+
+/**
+ * @brief XPI NOR option tag
+ */
+#define XPI_NOR_CFG_OPTION_TAG (0xfcf90U)
+
+/**
+ * @brief XPI NOR configuration option
+ *		The ROM SW can detect the FLASH configuration based on the following structure specified by the end-user
+ */
+struct xpi_nor_config_option_t {
+	union {
+		struct {
+			uint32_t words: 4;	   /**< Option words, exclude the header itself */
+			uint32_t reserved: 8;	/**< Reserved for future use */
+			uint32_t tag: 20;		/**< Must be 0xfcf90 */
+		};
+		uint32_t U;
+	} header;
+	union {
+		struct {
+			uint32_t freq_opt: 4;				/**< 1 - 30MHz, others, SoC specific setting */
+			uint32_t misc: 4;					/**< Not used for now */
+			uint32_t dummy_cycles: 8;			/**< 0 - Auto detected/ use predefined value, others: by end-user */
+			uint32_t quad_enable_seq: 4;		 /**< See the xpi_nor_quad_enable_seq_t definitions for more details */
+			uint32_t cmd_pads_after_init: 4;	 /**< See the xpi_data_pad_t definitions for more details */
+			uint32_t cmd_pads_after_por: 4;	  /**< See the xpi_data_pad_t definitions for more details */
+			uint32_t probe_type: 4;			  /**< See the xpi_nor_probe_t definitions for more details */
+		};
+		uint32_t U;
+	} option0;
+	union {
+		struct {
+			uint32_t drive_strength: 8;	  /**< IO drive strength, 0 - pre-defined, Others - specified by end-user */
+			uint32_t connection_sel: 4;	  /**< Device connection selection: 0 - PORTA, 1 - PORTB, 2 - Parallel mode */
+			uint32_t pin_group_sel: 4;	   /**< Pin group selection, 0 - 1st group, 1 - 2nd group, default, 1st group */
+			uint32_t io_voltage: 4;		  /**< SoC pad voltage, 0 - 3.0V, 1-1.8V */
+			uint32_t reserved: 12;		   /**< Reserved for future use */
+		};
+		uint32_t U;
+	} option1;
+	union {
+		struct {
+			uint32_t flash_size_option:8;			   /**< FLASH size option */
+			uint32_t flash_sector_size_option:4;		/**< FLASH sector size option */
+			uint32_t flash_sector_erase_cmd_option:4;   /**< Sector Erase command option */
+			uint32_t reserved:20;
+		};
+		uint32_t U;
+	} option2;
+};
+
+/**
+ * @brief Sector size options
+ */
+enum {
+	serial_nor_sector_size_4kb,	 /**< Sector size: 4KB */
+	serial_nor_sector_size_32kb,	/**< Sector size: 32KB */
+	serial_nor_sector_size_64kb,	/**< Sector size: 64KB */
+	serial_nor_sector_size_256kb,   /**< Sector size: 256KB */
+};
+
+/**
+ * @brief Sector erase command options
+ */
+enum  {
+	serial_nor_erase_type_4kb,	  /**< Sector erase command: 4KB Erase */
+	serial_nor_erase_type_32kb,	 /**< Sector erase command: 32KB Erase */
+	serial_nor_erase_type_64kb,	 /**< Sector erase command: 64KB Erase */
+	serial_nor_erase_type_256kb,	/**< Sector erase command: 256KB Erase */
+};
+
+/**
+ * @brief FLASH size options
+ */
+enum {
+	flash_size_4mb,	 /**< FLASH size: 4MB */
+	flash_size_8mb,	 /**< FLASH size: 8MB */
+	flash_size_16mb,	/**< FLASH size: 16MB */
+};
+
+/**
+ * @brief Device Mode configuration structure
+ */
+struct device_mode_cfg_t {
+	uint8_t cfg_cmd_type;	   /**< Configuration command type */
+	uint8_t param_size;		 /**< Size for parameter */
+};
+
+/**
+ * @brief Device mode parameter structure
+ */
+struct device_mode_param_t {
+	uint32_t instr_seq[4];  /**< Command Instruction sequence*/
+	uint32_t param;		 /**< Parameter */
+};
+
+/**
+ * @brief XPI NOR device information structure
+ */
+struct xpi_device_info_t {
+	uint32_t size_in_kbytes;				/**< Device Size in Kilobytes, offset 0x00 */
+	uint16_t page_size;					 /**< Page size, offset 0x04 */
+	uint16_t sector_size_kbytes;			/**< Sector size in kilobytes, offset 0x06 */
+	uint16_t block_size_kbytes;			 /**< Block size in kilobytes, offset 0x08 */
+	uint8_t busy_offset;					/**< Busy offset, offset 0x0a */
+	uint8_t busy_polarity;				  /**< Busy polarity, offset 0x0b */
+	uint8_t data_pads;					  /**< Device Size in Kilobytes, offset 0x0c */
+	uint8_t en_ddr_mode;					/**< Enable DDR mode, offset 0x0d */
+	uint8_t clk_freq_for_device_cfg;		/**< Clk frequency for device configuration offset 0x0e */
+	uint8_t working_mode_por;			   /**< Working mode after POR reset offset 0x0f */
+	uint8_t working_mode;				   /**< The device working mode, offset 0x10 */
+	uint8_t en_diff_clk;					/**< Enable Differential clock, offset 0x11 */
+	uint8_t data_valid_time;				/**< Data valid time, in 0.1ns, offset 0x12 */
+	uint8_t en_half_clk_for_non_read_cmd;   /**< Enable half clock for non-read command, offset 0x13 */
+	uint8_t clk_freq_for_non_read_cmd;	  /**< Enable safe clock for non-read command, offset 0x14 */
+	uint8_t dll_dly_target;				 /**< XPI DLL Delay Target, offset 0x15 */
+	uint8_t io_voltage;					 /**< IO voltage, offset 0x16 */
+	uint8_t reserved0;					  /**< Reserved for future use, offset 0x17 */
+	uint8_t cs_hold_time;				   /**< CS hold time, 0 - default, others - user specified, offset 0x18 */
+	uint8_t cs_setup_time;				  /**< CS setup time, 0 - default, others - user specified, offset 0x19 */
+	uint8_t cs_interval;					/**< CS interval, intervals between to CS active, offset 0x1a */
+	uint8_t en_dev_mode_cfg;				/**< Enable device mode configuration, offset 0x1b */
+	uint32_t flash_state_ctx;			   /**< Flash state context, offset 0x1c  */
+	struct device_mode_cfg_t mode_cfg_list[2];	 /**< Mode configuration sequences, offset 0x20 */
+	uint32_t mode_cfg_param[2];			 /**< Mode configuration parameters, offset 0x24 */
+	uint32_t reserved1;					 /**< Reserved for future use, offset 0x2C */
+	struct {
+		uint32_t entry[4];
+	} cfg_instr_seq[2];					  /**< Mode Configuration Instruction sequence, offset 0x30 */
+};
+
+/**
+ * @brief XPI NOR configuration structure
+ */
+struct xpi_nor_config_t {
+	uint32_t tag;						 /**< Must be "XNOR", offset 0x000 */
+	uint32_t reserved0;				   /**< Reserved for future use, offset 0x004 */
+	uint8_t rxclk_src;					/**< RXCLKSRC value, offset 0x008 */
+	uint8_t clk_freq;					 /**< Clock frequency, offset 0x009 */
+	uint8_t drive_strength;			   /**< Drive strength, offset 0x0a */
+	uint8_t column_addr_size;			 /**< Column address size, offset 0x0b */
+	uint8_t rxclk_src_for_init;		   /**< RXCLKSRC during FLASH initialization, offset 0x0c */
+	uint8_t config_in_progress;		   /**< Indicate whether device configuration is in progress, offset: 0x0d */
+	uint8_t reserved[2];				  /**< Reserved for future use, offset 0x00f */
+	struct {
+		uint8_t enable;				   /**<  Port enable flag, 0 - not enabled, 1 - enabled */
+		uint8_t group;					/**< 0 - 1st IO group, 1 - 2nd IO group */
+		uint8_t reserved[2];
+	} chn_info[4];						/**< Device connection information */
+	struct xpi_device_info_t device_info;	   /**< Device info, offset 0x20 */
+	struct xpi_instr_seq_t instr_set[xpi_std_nor_seq_idx_max];/**< Standard instruction sequence table, offset 0x70 */
+};
+
+/**
+ * @brief FLASH runtime context structure
+ */
+union flash_run_context_t {
+	struct {
+		uint32_t wait_time: 7;			  /**< Wait time */
+		uint32_t wait_time_unit: 1;		 /**< 0 - 10us, 1 - 1ms */
+		uint32_t reset_gpio: 8;			 /**<Reset GPIO */
+		uint32_t restore_sequence: 4;	   /**<Restore sequence */
+		uint32_t exit_no_cmd_sequence: 4;   /**< Exit no-cmd sequence */
+		uint32_t current_mode: 4;		   /**< Current FLASH mode */
+		uint32_t por_mode: 4;			   /**< FLASH mode upon Power-on Reset */
+	};
+	uint32_t U;
+};
+
+/**
+ * @brief XPI NOR API error codes
+ */
+enum {
+	status_xpi_nor_sfdp_not_found = MAKE_STATUS(status_group_xpi_nor, 0),   /**<  SFDP table was not found */
+	status_xpi_nor_ddr_read_dummy_cycle_probe_failed =
+					MAKE_STATUS(status_group_xpi_nor, 1),	/**<  Probing Dummy cyles for DDR read failed */
+	status_xpi_nor_flash_not_found = MAKE_STATUS(status_group_xpi_nor, 2),	/**< FLASH was not detected */
+};
+
+/**
+ * @brief XPI NOR driver interface
+ */
+struct xpi_nor_driver_interface_t {
+	/**< XPI NOR driver interface: API version */
+	uint32_t version;
+	/**< XPI NOR driver interface: Get FLASH configuration */
+	hpm_stat_t (*get_config)(uint32_t *base,
+							 struct xpi_nor_config_t *nor_cfg,
+							 struct xpi_nor_config_option_t *cfg_option);
+	/**< XPI NOR driver interface: initialize FLASH */
+	hpm_stat_t (*init)(uint32_t *base, struct xpi_nor_config_t *nor_config);
+	/**< XPI NOR driver interface: Enable write access to FLASH */
+	hpm_stat_t
+	(*enable_write)(uint32_t *base, enum xpi_xfer_channel_t channel,
+					const struct xpi_nor_config_t *nor_config, uint32_t addr);
+	/**< XPI NOR driver interface: Get FLASH status register */
+	hpm_stat_t (*get_status)(uint32_t *base,
+							 enum xpi_xfer_channel_t channel,
+							 const struct xpi_nor_config_t *nor_config,
+							 uint32_t addr,
+							 uint16_t *out_status);
+	/**< XPI NOR driver interface: Wait when FLASH is still busy */
+	hpm_stat_t
+	(*wait_busy)(uint32_t *base, enum xpi_xfer_channel_t channel,
+				const struct xpi_nor_config_t *nor_config, uint32_t addr);
+	/**< XPI NOR driver interface: erase a specified FLASH region */
+	hpm_stat_t (*erase)(uint32_t *base,
+						enum xpi_xfer_channel_t channel,
+						const struct xpi_nor_config_t *nor_config,
+						uint32_t start,
+						uint32_t length);
+	/**< XPI NOR driver interface: Erase the whole FLASH */
+	hpm_stat_t (*erase_chip)(uint32_t *base, enum xpi_xfer_channel_t channel,
+							const struct xpi_nor_config_t *nor_config);
+	/**< XPI NOR driver interface: Erase specified FLASH sector */
+	hpm_stat_t
+	(*erase_sector)(uint32_t *base, enum xpi_xfer_channel_t channel,
+					const struct xpi_nor_config_t *nor_config, uint32_t addr);
+	/**< XPI NOR driver interface: Erase specified FLASH block */
+	hpm_stat_t
+	(*erase_block)(uint32_t *base, enum xpi_xfer_channel_t channel,
+					const struct xpi_nor_config_t *nor_config, uint32_t addr);
+	/**< XPI NOR driver interface: Program data to specified FLASH address */
+	hpm_stat_t (*program)(uint32_t *base,
+						  enum xpi_xfer_channel_t channel,
+						  const struct xpi_nor_config_t *nor_config,
+						  const uint32_t *src,
+						  uint32_t dst_addr,
+						  uint32_t length);
+	/**< XPI NOR driver interface: read data from specified FLASH address */
+	hpm_stat_t (*read)(uint32_t *base,
+					   enum xpi_xfer_channel_t channel,
+					   const struct xpi_nor_config_t *nor_config,
+					   uint32_t *dst,
+					   uint32_t start,
+					   uint32_t length);
+	/**< XPI NOR driver interface: program FLASH page using nonblocking interface */
+	hpm_stat_t (*page_program_nonblocking)(uint32_t *base,
+										   enum xpi_xfer_channel_t channel,
+										   const struct xpi_nor_config_t *nor_config,
+										   const uint32_t *src,
+										   uint32_t dst_addr,
+										   uint32_t length);
+	/**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */
+	hpm_stat_t (*erase_sector_nonblocking)(uint32_t *base,
+										   enum xpi_xfer_channel_t channel,
+										   const struct xpi_nor_config_t *nor_config,
+										   uint32_t addr);
+	/**< XPI NOR driver interface: erase FLASH block using nonblocking interface */
+	hpm_stat_t (*erase_block_nonblocking)(uint32_t *base,
+										  enum xpi_xfer_channel_t channel,
+										  const struct xpi_nor_config_t *nor_config,
+										  uint32_t addr);
+	/**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */
+	hpm_stat_t (*erase_chip_nonblocking)(uint32_t *base,
+										 enum xpi_xfer_channel_t channel,
+										 const struct xpi_nor_config_t *nor_config);
+
+	uint32_t reserved0[3];
+
+	/**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */
+	hpm_stat_t (*auto_config)(uint32_t *base, struct xpi_nor_config_t *nor_cfg,
+								struct xpi_nor_config_option_t *cfg_option);
+
+	/**< XPI NOR driver interface: Get FLASH properties */
+	hpm_stat_t (*get_property)(uint32_t *base, struct xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value);
+
+	uint32_t reserved1;
+
+	/**< Post Erase Sector Nonblocking operation: For Hybrid mode only */
+	hpm_stat_t (*post_erase_sector_nonblocking)(uint32_t *base, enum xpi_xfer_channel_t chn,
+												struct xpi_nor_config_t *nor_cfg, uint32_t addr);
+
+	 /**< Post Erase Block Nonblocking operation: For Hybrid mode only */
+	hpm_stat_t (*post_erase_block_nonblocking)(uint32_t *base, enum xpi_xfer_channel_t chn,
+												struct xpi_nor_config_t *nor_cfg, uint32_t addr);
+
+	/**< Post Erase Chip Nonblocking operation: For Hybrid mode only */
+	hpm_stat_t (*post_erase_chip_nonblocking)(uint32_t *base, enum xpi_xfer_channel_t chn,
+											struct xpi_nor_config_t *nor_cfg);
+
+	 /**< Post Page Program Nonblocking operation: For Hybrid mode only */
+	hpm_stat_t (*post_page_program_nonblocking)(uint32_t *base, enum xpi_xfer_channel_t chn,
+												struct xpi_nor_config_t *nor_config,
+												const uint32_t *src, uint32_t dst_addr, uint32_t length);
+	/**< Turn on the power for Internal FLASH */
+	void (*sip_flash_power_on)(uint32_t *base);
+
+	/**< Turn off the power for Internal FLASH */
+	void (*sip_flash_power_off)(uint32_t *base);
+
+	/**< Enable Hybrid mode */
+	void (*enable_hybrid_xpi)(uint32_t *base);
+
+	/**< Disable Hybrid mode */
+	void (*disable_hybrid_xpi)(uint32_t *base);
+
+};
+
+/**
+ * @}
+ */
+
+#endif /* HPM_ROMAPI_XPI_NOR_DEF_H */

contrib/loaders/flash/hpmicro/hpm_romapi_xpi_soc_def.h

@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/*
+ * Copyright (c) 2021 HPMicro
+ */
+
+#ifndef HPM_ROMAPI_XPI_SOC_DEF_H
+#define HPM_ROMAPI_XPI_SOC_DEF_H
+
+#include "hpm_common.h"
+#include "hpm_romapi_xpi_def.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+#define XPI_CLK_OUT_FREQ_OPTION_30MHZ (1U)
+#define XPI_CLK_OUT_FREQ_OPTION_50MHZ (2U)
+#define XPI_CLK_OUT_FREQ_OPTION_66MHZ (3U)
+#define XPI_CLK_OUT_FREQ_OPTION_80MHZ (4U)
+#define XPI_CLK_OUT_FREQ_OPTION_104MHZ (5U)
+#define XPI_CLK_OUT_FREQ_OPTION_120MHZ (6U)
+#define XPI_CLK_OUT_FREQ_OPTION_133MHZ (7U)
+#define XPI_CLK_OUT_FREQ_OPTION_166MHZ (8U)
+#define XPI_CLK_OUT_FREQ_OPTION_200MHZ (9U)
+
+struct xpi_io_config_t {
+	uint8_t data_pads;
+	enum xpi_channel_t channel;
+	enum xpi_io_group_t io_group;
+	uint8_t drive_strength;
+	bool enable_dqs;
+	bool enable_diff_clk;
+};
+
+enum clk_freq_type_t {
+	xpi_freq_type_typical,
+	xpi_freq_type_mhz,
+};
+
+enum xpi_clk_src_t {
+	xpi_clk_src_auto,
+	xpi_clk_src_osc,
+	xpi_clk_src_pll0clk0,
+	xpi_clk_src_pll1clk0,
+	xpi_clk_src_pll1clk1,
+	xpi_clk_src_pll2clk0,
+	xpi_clk_src_pll2clk1,
+	xpi_clk_src_pll3clk0,
+	xpi_clk_src_pll4clk0,
+};
+
+union xpi_clk_config_t {
+	struct {
+		uint8_t freq;
+		bool enable_ddr;
+		enum xpi_clk_src_t clk_src;
+		enum clk_freq_type_t freq_type;
+	};
+	uint32_t freq_opt;
+};
+
+enum xpi_clock_t {
+	xpi_clock_bus,
+	xpi_clock_serial_root,
+	xpi_clock_serial,
+};
+
+#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */

contrib/loaders/flash/hpmicro/hpm_xpi_flash.h

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/*
+ * Copyright (c) 2021 hpmicro
+ */
+
+#ifndef HPM_XPI_FLASH_H
+#define HPM_XPI_FLASH_H
+
+#define FLASH_INIT          (0)
+#define FLASH_ERASE         (0x6)
+#define FLASH_PROGRAM       (0xc)
+#define FLASH_READ          (0x12)
+#define FLASH_GET_INFO      (0x18)
+#define FLASH_ERASE_CHIP    (0x1e)
+
+#endif

contrib/loaders/flash/hpmicro/hpm_xpi_flash.inc

@@ -0,0 +1,72 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
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+0x3e,0x96,0xe3,0x74,0xc3,0xf8,0xa5,0xb7,

contrib/loaders/flash/hpmicro/linker.ld

@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 HPMicro
+ */
+ENTRY(_init)
+
+SECTIONS
+{
+	.text : {
+		*(.func_table)
+		KEEP(*(.flash_algo.text*))
+		KEEP(*(.rodata))
+		KEEP(*(.rodata*))
+		KEEP(*(.flash_algo.data*))
+		*(.text)
+		*(.text*)
+		__etext = .;
+	}
+	.discard : {
+		__noncacheable_start__ = .;
+		__noncacheable_bss_start__ = .;
+		__bss_start__ = .;
+		__bss_end__ = .;
+		__noncacheable_bss_end__ = .;
+		_end = .;
+		__noncacheable_init_start__ = .;
+		__data_start__ = .;
+		__data_end__ = .;
+		__noncacheable_init_end__ = .;
+		__noncacheable_end__ = .;
+		__heap_start__ = .;
+		__heap_end__ = .;
+		__ramfunc_start__ = .;
+		__ramfunc_end__ = .;
+		__noncacheable_bss_start__ = .;
+		__noncacheable_bss_end__ = .;
+		__noncacheable_init_start__ = .;
+		__noncacheable_init_end__ = .;
+		__tdata_start__ = .;
+		__tdata_end__ = .;
+		__tbss_start__ = .;
+		__tbss_end__ = .;
+		__data_load_addr__ = .;
+		__fast_load_addr__ = .;
+		__tdata_load_addr__ = .;
+		__noncacheable_init_load_addr__ = .;
+	}
+}

contrib/loaders/flash/hpmicro/openocd_flash_algo.c

@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 HPMicro
+ */
+
+#include "hpm_romapi.h"
+
+#define CSR_MCACHE_CTL (0x7CA)
+#define HPM_MCACHE_CTL_DC_EN_MASK  (0x2UL)
+
+#define XPI_USE_PORT_B_MASK (0x100)
+#define XPI_USE_PORT_A_MASK (0)
+#define XPI_USE_PORT_SHIFT (0x8)
+
+#define ROMAPI_SUPPORTS_HYBRIDXPI() (ROM_API_TABLE_ROOT->xpi_nor_driver_if->version >= 0x56010300)
+
+struct hpm_flash_info_t {
+	uint32_t total_sz_in_bytes;
+	uint32_t sector_sz_in_bytes;
+};
+
+__attribute__ ((section(".flash_algo.data"))) struct xpi_nor_config_t nor_config;
+__attribute__ ((section(".flash_algo.data"))) bool xpi_inited = false;
+__attribute__ ((section(".flash_algo.data"))) uint32_t channel = xpi_channel_a1;
+__attribute__ ((section(".flash_algo.data"))) uint32_t *xpi_base;
+
+__attribute__ ((section(".flash_algo.text"))) void refresh_device_size(uint32_t *base,
+																		struct xpi_nor_config_option_t *option)
+{
+	volatile uint32_t *dev_size = (volatile uint32_t *)((uint32_t)base + 0x60);
+	bool enable_channelb = false;
+	if (option->header.words > 1)
+		enable_channelb = option->option1.connection_sel == xpi_nor_connection_sel_chnb_cs0;
+	if (enable_channelb) {
+		dev_size[0] = 0;
+		dev_size[1] = 0;
+	}
+}
+
+__attribute__ ((section(".flash_algo.text"))) uint32_t flash_init(uint32_t flash_base, uint32_t header,
+		uint32_t opt0, uint32_t opt1, uint32_t xpi_base_addr)
+{
+	uint32_t i = 0;
+	struct xpi_nor_config_option_t cfg_option;
+	hpm_stat_t stat = status_success;
+
+	xpi_base = (uint32_t *)xpi_base_addr;
+	if (xpi_inited)
+		return stat;
+
+	__asm volatile("csrc %0, %1" : : "i"(CSR_MCACHE_CTL), "r"(HPM_MCACHE_CTL_DC_EN_MASK));
+	for (i = 0; i < sizeof(cfg_option); i++)
+		*((uint8_t *)&cfg_option + i) = 0;
+	for (i = 0; i < sizeof(nor_config); i++)
+		*((uint8_t *)&nor_config + i) = 0;
+
+	cfg_option.header.U = header;
+	cfg_option.option0.U = opt0;
+	cfg_option.option1.U = opt1;
+
+	if (opt1 & XPI_USE_PORT_B_MASK)
+		channel = xpi_channel_b1;
+	else
+		channel = xpi_channel_a1;
+
+	stat = ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(xpi_base, &nor_config, &cfg_option);
+	if (stat)
+		return stat;
+
+	if (ROMAPI_SUPPORTS_HYBRIDXPI())
+		ROM_API_TABLE_ROOT->xpi_nor_driver_if->enable_hybrid_xpi(xpi_base);
+
+	refresh_device_size(xpi_base, &cfg_option);
+
+	nor_config.device_info.clk_freq_for_non_read_cmd = 0;
+	if (!xpi_inited)
+		xpi_inited = true;
+	return stat;
+}
+
+__attribute__ ((section(".flash_algo.text"))) uint32_t flash_erase(uint32_t flash_base, uint32_t address, uint32_t size)
+{
+	hpm_stat_t stat = status_success;
+	uint32_t left, start, block_size, align;
+
+	left = size;
+	start = address;
+	if (ROMAPI_SUPPORTS_HYBRIDXPI())
+		start += flash_base;
+	block_size = nor_config.device_info.block_size_kbytes * 1024;
+	if (left >= block_size) {
+		align = block_size - (start % block_size);
+		if (align != block_size) {
+			stat = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(xpi_base, channel, &nor_config, start, align);
+			if (stat != status_success)
+				return stat;
+			left -= align;
+			start += align;
+		}
+		while (left > block_size) {
+			stat = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(xpi_base, channel, &nor_config, start);
+			if (stat != status_success)
+				break;
+			left -= block_size;
+			start += block_size;
+		}
+	}
+	if (stat == status_success && left)
+		stat = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(xpi_base, channel, &nor_config, start, left);
+	return stat;
+}
+
+__attribute__ ((section(".flash_algo.text"))) uint32_t flash_program(uint32_t flash_base, uint32_t address,
+		uint32_t *buf, uint32_t size)
+{
+	hpm_stat_t stat;
+
+	if (ROMAPI_SUPPORTS_HYBRIDXPI())
+		address += flash_base;
+	stat = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(xpi_base, channel, &nor_config, buf, address, size);
+	return stat;
+}
+
+__attribute__ ((section(".flash_algo.text"))) uint32_t flash_read(uint32_t flash_base, uint32_t *buf,
+		uint32_t address, uint32_t size)
+{
+	hpm_stat_t stat;
+
+	if (ROMAPI_SUPPORTS_HYBRIDXPI())
+		address += flash_base;
+	stat = ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(xpi_base, channel, &nor_config, buf, address, size);
+	return stat;
+}
+
+__attribute__ ((section(".flash_algo.text"))) uint32_t flash_get_info(uint32_t flash_base,
+																		struct hpm_flash_info_t *flash_info)
+{
+	if (!flash_info)
+		return status_invalid_argument;
+
+	flash_info->total_sz_in_bytes = nor_config.device_info.size_in_kbytes << 10;
+	flash_info->sector_sz_in_bytes = nor_config.device_info.sector_size_kbytes << 10;
+	return status_success;
+}
+
+__attribute__ ((section(".flash_algo.text"))) uint32_t flash_erase_chip(uint32_t flash_base)
+{
+	return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(xpi_base, channel, &nor_config);
+}
+
+__attribute__ ((section(".flash_algo.text"))) void flash_deinit(void)
+{
+}

contrib/loaders/flash/max32xxx/Makefile

@@ -1,21 +1,30 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
+TARGET=max32xxx_write
+ENTRY=algo_write
+
 BIN2C = ../../../../src/helper/bin2char.sh
 
-CROSS_COMPILE ?= arm-none-eabi-
-AS      = $(CROSS_COMPILE)as
-OBJCOPY = $(CROSS_COMPILE)objcopy
+PREFIX=arm-none-eabi
+CFLAGS=-mthumb -mcpu=cortex-m4 -Wa,-mimplicit-it=thumb
 
-all: max32xxx.inc
+all: $(TARGET).inc
 
-%.elf: %.s
-	$(AS) $< -o $@
+%.o: %.c
+	$(PREFIX)-gcc $(CFLAGS) -Os -Wall -c ${<} -o ${@}
+
+%.elf: %.o
+	$(PREFIX)-ld -nostdlib --entry $(ENTRY) ${<} -o ${@}
+	$(PREFIX)-size ${@}
 
 %.bin: %.elf
-	$(OBJCOPY) -Obinary $< $@
+	$(PREFIX)-objcopy -O binary ${<} ${@}
 
 %.inc: %.bin
 	$(BIN2C) < $< > $@
 
+%.dasm: %.o
+	$(PREFIX)-objdump -S ${<} > ${TARGET}.dasm
+
 clean:
-	-rm -f *.elf *.bin *.inc
+	rm -rf $(TARGET).bin $(TARGET).elf $(TARGET).o $(TARGET).dasm $(TARGET).inc

contrib/loaders/flash/max32xxx/algo_options.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ *   Copyright (C) 2016 by Maxim Integrated                                *
+ *   Copyright (C) 2025 Analog Devices, Inc.                               *
+ ***************************************************************************/
+
+#define OPTIONS_128                     0x01 /* Perform 128 bit flash writes */
+#define OPTIONS_ENC                     0x02 /* Encrypt the flash contents */
+#define OPTIONS_AUTH                    0x04 /* Authenticate the flash contents */
+#define OPTIONS_COUNT                   0x08 /* Add counter values to authentication */
+#define OPTIONS_INTER                   0x10 /* Interleave the authentication and count values*/
+#define OPTIONS_RELATIVE_XOR            0x20 /* Only XOR the offset of the address when encrypting */
+#define OPTIONS_KEYSIZE                 0x40 /* Use a 256 bit KEY */

contrib/loaders/flash/max32xxx/flc_regs.h

@@ -0,0 +1,238 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ *   Copyright (C) 2016 by Maxim Integrated                                *
+ *   Copyright (C) 2025 Analog Devices, Inc.                               *
+ ***************************************************************************/
+
+#ifndef _FLC_REGS_H_
+#define _FLC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__ICCARM__)
+#pragma system_include
+#endif
+
+/*/ @cond */
+/*
+	If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+/*/ @endcond */
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     flc
+ * @defgroup    flc_registers Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
+ * @description Flash Memory Control.
+ */
+
+/**
+ * @ingroup flc_registers
+ * Structure type to access the FLC Registers.
+ */
+struct mxc_flc_regs {
+	__IO uint32_t addr;	  /**< <tt>\b 0x00:<\tt> FLC ADDR Register */
+	__IO uint32_t clkdiv; /**< <tt>\b 0x04:<\tt> FLC CLKDIV Register */
+	__IO uint32_t cn;	  /**< <tt>\b 0x08:<\tt> FLC CN Register */
+	__R uint32_t rsv_0xc_0x23[6];
+	__IO uint32_t intr; /**< <tt>\b 0x024:<\tt> FLC INTR Register */
+	__R uint32_t rsv_0x28_0x2f[2];
+	__IO uint32_t data[4]; /**< <tt>\b 0x30:<\tt> FLC DATA Register */
+	__O uint32_t acntl;	   /**< <tt>\b 0x40:<\tt> FLC ACNTL Register */
+};
+
+/* Register offsets for module FLC */
+/**
+ * @ingroup    flc_registers
+ * @defgroup   FLC_Register_Offsets Register Offsets
+ * @brief      FLC Peripheral Register Offsets from the FLC Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL)	  /**< Offset from FLC Base Address: <tt> 0x0x000 */
+#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0x004 */
+#define MXC_R_FLC_CN ((uint32_t)0x00000008UL)	  /**< Offset from FLC Base Address: <tt> 0x0x008 */
+#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL)	  /**< Offset from FLC Base Address: <tt> 0x0x024 */
+#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL)	  /**< Offset from FLC Base Address: <tt> 0x0x030 */
+#define MXC_R_FLC_ACNTL ((uint32_t)0x00000040UL)  /**< Offset from FLC Base Address: <tt> 0x0x040 */
+/**@} end of group flc_registers */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup ADDR_Register
+ * @brief    Flash Write Address.
+ * @{
+ */
+#define MXC_F_FLC_ADDR_ADDR_POS 0												  /**< ADDR_ADDR Position */
+#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
+
+/**@} end of group ADDR_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup CLKDIV_Register
+ * @brief    Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
+ *           MHz clock for Flash controller.
+ * @{
+ */
+#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0												/**< CLKDIV_CLKDIV Position */
+#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
+
+/**@} end of group CLKDIV_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup CN_Register
+ * @brief    Flash Control Register.
+ * @{
+ */
+#define MXC_F_FLC_CN_WR_POS 0													   /**< CN_WR Position */
+#define MXC_F_FLC_CN_WR ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS))				   /**< CN_WR Mask */
+#define MXC_V_FLC_CN_WR_COMPLETE ((uint32_t)0x0UL)								   /**< CN_WR_COMPLETE Value */
+#define MXC_S_FLC_CN_WR_COMPLETE (MXC_V_FLC_CN_WR_COMPLETE << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE Setting */
+#define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL)									   /**< CN_WR_START Value */
+#define MXC_S_FLC_CN_WR_START (MXC_V_FLC_CN_WR_START << MXC_F_FLC_CN_WR_POS)	   /**< CN_WR_START Setting */
+
+#define MXC_F_FLC_CN_ME_POS 1									   /**< CN_ME Position */
+#define MXC_F_FLC_CN_ME ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */
+
+#define MXC_F_FLC_CN_PGE_POS 2										 /**< CN_PGE Position */
+#define MXC_F_FLC_CN_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */
+
+#define MXC_F_FLC_CN_WDTH_POS 4														   /**< CN_WDTH Position */
+#define MXC_F_FLC_CN_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS))				   /**< CN_WDTH Mask */
+#define MXC_V_FLC_CN_WDTH_SIZE128 ((uint32_t)0x0UL)									   /**< CN_WDTH_SIZE128 Value */
+#define MXC_S_FLC_CN_WDTH_SIZE128 (MXC_V_FLC_CN_WDTH_SIZE128 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */
+#define MXC_V_FLC_CN_WDTH_SIZE32 ((uint32_t)0x1UL)									   /**< CN_WDTH_SIZE32 Value */
+#define MXC_S_FLC_CN_WDTH_SIZE32 (MXC_V_FLC_CN_WDTH_SIZE32 << MXC_F_FLC_CN_WDTH_POS)   /**< CN_WDTH_SIZE32 Setting */
+
+#define MXC_F_FLC_CN_ERASE_CODE_POS 8												/**< CN_ERASE_CODE Position */
+#define MXC_F_FLC_CN_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */
+#define MXC_V_FLC_CN_ERASE_CODE_NOP ((uint32_t)0x0UL)								/**< CN_ERASE_CODE_NOP Value */
+#define MXC_S_FLC_CN_ERASE_CODE_NOP                                                                                    \
+	(MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */
+#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL)	 /**< CN_ERASE_CODE_ERASEPAGE Value */
+#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE                                                                              \
+	(MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting */
+#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL)			   /**< CN_ERASE_CODE_ERASEALL Value */
+#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL                                                                               \
+	(MXC_V_FLC_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting */
+
+#define MXC_F_FLC_CN_PEND_POS 24												 /**< CN_PEND Position */
+#define MXC_F_FLC_CN_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS))			 /**< CN_PEND Mask */
+#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL)								 /**< CN_PEND_IDLE Value */
+#define MXC_S_FLC_CN_PEND_IDLE (MXC_V_FLC_CN_PEND_IDLE << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE Setting */
+#define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL)								 /**< CN_PEND_BUSY Value */
+#define MXC_S_FLC_CN_PEND_BUSY (MXC_V_FLC_CN_PEND_BUSY << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */
+
+#define MXC_F_FLC_CN_LVE_POS 25												/**< CN_LVE Position */
+#define MXC_F_FLC_CN_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS))		/**< CN_LVE Mask */
+#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL)								/**< CN_LVE_DIS Value */
+#define MXC_S_FLC_CN_LVE_DIS (MXC_V_FLC_CN_LVE_DIS << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting */
+#define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL)								/**< CN_LVE_EN Value */
+#define MXC_S_FLC_CN_LVE_EN (MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS)	/**< CN_LVE_EN Setting */
+
+#define MXC_F_FLC_CN_BRST_POS 27													   /**< CN_BRST Position */
+#define MXC_F_FLC_CN_BRST ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS))				   /**< CN_BRST Mask */
+#define MXC_V_FLC_CN_BRST_DISABLE ((uint32_t)0x0UL)									   /**< CN_BRST_DISABLE Value */
+#define MXC_S_FLC_CN_BRST_DISABLE (MXC_V_FLC_CN_BRST_DISABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */
+#define MXC_V_FLC_CN_BRST_ENABLE ((uint32_t)0x1UL)									   /**< CN_BRST_ENABLE Value */
+#define MXC_S_FLC_CN_BRST_ENABLE (MXC_V_FLC_CN_BRST_ENABLE << MXC_F_FLC_CN_BRST_POS)   /**< CN_BRST_ENABLE Setting */
+
+#define MXC_F_FLC_CN_UNLOCK_POS 28										   /**< CN_UNLOCK Position */
+#define MXC_F_FLC_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */
+#define MXC_V_FLC_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL)					   /**< CN_UNLOCK_UNLOCKED Value */
+#define MXC_S_FLC_CN_UNLOCK_UNLOCKED                                                                                   \
+	(MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */
+#define MXC_V_FLC_CN_UNLOCK_LOCKED ((uint32_t)0x3UL)		  /**< CN_UNLOCK_LOCKED Value */
+#define MXC_S_FLC_CN_UNLOCK_LOCKED                                                                                     \
+	(MXC_V_FLC_CN_UNLOCK_LOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_LOCKED Setting */
+
+/**@} end of group CN_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup INTR_Register
+ * @brief    Flash Interrupt Register.
+ * @{
+ */
+#define MXC_F_FLC_INTR_DONE_POS 0										   /**< INTR_DONE Position */
+#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
+#define MXC_V_FLC_INTR_DONE_INACTIVE ((uint32_t)0x0UL)					   /**< INTR_DONE_INACTIVE Value */
+#define MXC_S_FLC_INTR_DONE_INACTIVE                                                                                   \
+	(MXC_V_FLC_INTR_DONE_INACTIVE << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */
+#define MXC_V_FLC_INTR_DONE_PENDING ((uint32_t)0x1UL)		  /**< INTR_DONE_PENDING Value */
+#define MXC_S_FLC_INTR_DONE_PENDING                                                                                    \
+	(MXC_V_FLC_INTR_DONE_PENDING << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */
+
+#define MXC_F_FLC_INTR_AF_POS 1														   /**< INTR_AF Position */
+#define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS))				   /**< INTR_AF Mask */
+#define MXC_V_FLC_INTR_AF_NOERROR ((uint32_t)0x0UL)									   /**< INTR_AF_NOERROR Value */
+#define MXC_S_FLC_INTR_AF_NOERROR (MXC_V_FLC_INTR_AF_NOERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */
+#define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL)									   /**< INTR_AF_ERROR Value */
+#define MXC_S_FLC_INTR_AF_ERROR (MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS)	   /**< INTR_AF_ERROR Setting */
+
+#define MXC_F_FLC_INTR_DONEIE_POS 8											   /**< INTR_DONEIE Position */
+#define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
+#define MXC_V_FLC_INTR_DONEIE_DISABLE ((uint32_t)0x0UL)						   /**< INTR_DONEIE_DISABLE Value */
+#define MXC_S_FLC_INTR_DONEIE_DISABLE                                                                                  \
+	(MXC_V_FLC_INTR_DONEIE_DISABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */
+#define MXC_V_FLC_INTR_DONEIE_ENABLE ((uint32_t)0x1UL)			 /**< INTR_DONEIE_ENABLE Value */
+#define MXC_S_FLC_INTR_DONEIE_ENABLE                                                                                   \
+	(MXC_V_FLC_INTR_DONEIE_ENABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */
+
+#define MXC_F_FLC_INTR_AFIE_POS 9										   /**< INTR_AFIE Position */
+#define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
+
+/**@} end of group INTR_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup DATA_Register
+ * @brief    Flash Write Data.
+ * @{
+ */
+#define MXC_F_FLC_DATA_DATA_POS 0												  /**< DATA_DATA Position */
+#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
+
+/**@} end of group DATA_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup ACNTL_Register
+ * @brief    Access Control Register. Writing the ACNTL register with the following values in
+ *           the order shown, allows read and write access to the system and user Information
+ *           block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl =
+ *           0x9608b2c1. When unlocked, a write of any word will disable access to system and
+ *           user information block. Readback of this register is always zero.
+ * @{
+ */
+#define MXC_F_FLC_ACNTL_ACNTL_POS 0													  /**< ACNTL_ACNTL Position */
+#define MXC_F_FLC_ACNTL_ACNTL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */
+
+/**@} end of group ACNTL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FLC_REGS_H_ */

contrib/loaders/flash/max32xxx/gcr_regs.h

@@ -0,0 +1,777 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ *   Copyright (C) 2016 by Maxim Integrated                                *
+ *   Copyright (C) 2025 Analog Devices, Inc.                               *
+ ***************************************************************************/
+
+#ifndef _GCR_REGS_H_
+#define _GCR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__ICCARM__)
+#pragma system_include
+#endif
+
+#if defined(__CC_ARM)
+#pragma anon_unions
+#endif
+/*/ @cond */
+/*
+	If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+/*/ @endcond */
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     gcr
+ * @defgroup    gcr_registers GCR_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
+ * @details Global Control Registers.
+ */
+
+/**
+ * @ingroup gcr_registers
+ * Structure type to access the GCR Registers.
+ */
+struct mxc_gcr_regs {
+	__IO uint32_t scon;	 /**< <tt>\b 0x00:</tt> GCR SCON Register */
+	__IO uint32_t rstr0; /**< <tt>\b 0x04:</tt> GCR RSTR0 Register */
+	__IO uint32_t clkcn; /**< <tt>\b 0x08:</tt> GCR CLKCN Register */
+	__IO uint32_t pm;	 /**< <tt>\b 0x0C:</tt> GCR PM Register */
+	__R uint32_t rsv_0x10_0x17[2];
+	__IO uint32_t pckdiv; /**< <tt>\b 0x18:</tt> GCR PCKDIV Register */
+	__R uint32_t rsv_0x1c_0x23[2];
+	__IO uint32_t perckcn0; /**< <tt>\b 0x24:</tt> GCR PERCKCN0 Register */
+	__IO uint32_t memckcn;	/**< <tt>\b 0x28:</tt> GCR MEMCKCN Register */
+	__IO uint32_t memzcn;	/**< <tt>\b 0x2C:</tt> GCR MEMZCN Register */
+	__R uint32_t rsv_0x30_0x3f[4];
+	__IO uint32_t sysst;	/**< <tt>\b 0x40:</tt> GCR SYSST Register */
+	__IO uint32_t rstr1;	/**< <tt>\b 0x44:</tt> GCR RSTR1 Register */
+	__IO uint32_t perckcn1; /**< <tt>\b 0x48:</tt> GCR PERCKCN1 Register */
+	__IO uint32_t evten;	/**< <tt>\b 0x4C:</tt> GCR EVTEN Register */
+	__I uint32_t revision;	/**< <tt>\b 0x50:</tt> GCR REVISION Register */
+	__IO uint32_t syssie;	/**< <tt>\b 0x54:</tt> GCR SYSSIE Register */
+	__R uint32_t rsv_0x58_0x63[3];
+	__IO uint32_t eccerr;	/**< <tt>\b 0x64:</tt> GCR ECCERR Register */
+	__IO uint32_t eccnded;	/**< <tt>\b 0x68:</tt> GCR ECCNDED Register */
+	__IO uint32_t eccirqen; /**< <tt>\b 0x6C:</tt> GCR ECCIRQEN Register */
+	__IO uint32_t eccerrad; /**< <tt>\b 0x70:</tt> GCR ECCERRAD Register */
+};
+
+/* Register offsets for module GCR */
+/**
+ * @ingroup    gcr_registers
+ * @defgroup   GCR_Register_Offsets Register Offsets
+ * @brief      GCR Peripheral Register Offsets from the GCR Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GCR_SCON ((uint32_t)0x00000000UL)		/**< Offset from GCR Base Address: 0x0000 */
+#define MXC_R_GCR_RSTR0 ((uint32_t)0x00000004UL)	/**< Offset from GCR Base Address: 0x0004 */
+#define MXC_R_GCR_CLKCN ((uint32_t)0x00000008UL)	/**< Offset from GCR Base Address: 0x0008 */
+#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL)		/**< Offset from GCR Base Address: 0x000C */
+#define MXC_R_GCR_PCKDIV ((uint32_t)0x00000018UL)	/**< Offset from GCR Base Address: 0x0018 */
+#define MXC_R_GCR_PERCKCN0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: 0x0024 */
+#define MXC_R_GCR_MEMCKCN ((uint32_t)0x00000028UL)	/**< Offset from GCR Base Address: 0x0028 */
+#define MXC_R_GCR_MEMZCN ((uint32_t)0x0000002CUL)	/**< Offset from GCR Base Address: 0x002C */
+#define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL)	/**< Offset from GCR Base Address: 0x0040 */
+#define MXC_R_GCR_RSTR1 ((uint32_t)0x00000044UL)	/**< Offset from GCR Base Address: 0x0044 */
+#define MXC_R_GCR_PERCKCN1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: 0x0048 */
+#define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL)	/**< Offset from GCR Base Address: 0x004C */
+#define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */
+#define MXC_R_GCR_SYSSIE ((uint32_t)0x00000054UL)	/**< Offset from GCR Base Address: 0x0054 */
+#define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL)	/**< Offset from GCR Base Address: 0x0064 */
+#define MXC_R_GCR_ECCNDED ((uint32_t)0x00000068UL)	/**< Offset from GCR Base Address: 0x0068 */
+#define MXC_R_GCR_ECCIRQEN ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: 0x006C */
+#define MXC_R_GCR_ECCERRAD ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: 0x0070 */
+													/**@} end of group gcr_registers */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_SCON GCR_SCON
+ * @brief    System Control.
+ * @{
+ */
+#define MXC_F_GCR_SCON_BSTAPEN_POS 0											 /**< SCON_BSTAPEN Position */
+#define MXC_F_GCR_SCON_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SCON_BSTAPEN_POS)) /**< SCON_BSTAPEN Mask */
+#define MXC_V_GCR_SCON_BSTAPEN_DIS ((uint32_t)0x0UL)							 /**< SCON_BSTAPEN_DIS Value */
+#define MXC_S_GCR_SCON_BSTAPEN_DIS                                                                                     \
+	(MXC_V_GCR_SCON_BSTAPEN_DIS << MXC_F_GCR_SCON_BSTAPEN_POS) /**< SCON_BSTAPEN_DIS Setting */
+#define MXC_V_GCR_SCON_BSTAPEN_EN ((uint32_t)0x1UL)			   /**< SCON_BSTAPEN_EN Value */
+#define MXC_S_GCR_SCON_BSTAPEN_EN                                                                                      \
+	(MXC_V_GCR_SCON_BSTAPEN_EN << MXC_F_GCR_SCON_BSTAPEN_POS) /**< SCON_BSTAPEN_EN Setting */
+
+#define MXC_F_GCR_SCON_SBUSARB_POS 1											 /**< SCON_SBUSARB Position */
+#define MXC_F_GCR_SCON_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */
+#define MXC_V_GCR_SCON_SBUSARB_FIX ((uint32_t)0x0UL)							 /**< SCON_SBUSARB_FIX Value */
+#define MXC_S_GCR_SCON_SBUSARB_FIX                                                                                     \
+	(MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */
+#define MXC_V_GCR_SCON_SBUSARB_ROUND ((uint32_t)0x1UL)		   /**< SCON_SBUSARB_ROUND Value */
+#define MXC_S_GCR_SCON_SBUSARB_ROUND                                                                                   \
+	(MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */
+
+#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */
+#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP                                                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS))	/**< SCON_FLASH_PAGE_FLIP Mask */
+#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL ((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */
+#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                                                          \
+	(MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                                                             \
+	 << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)						 /**< SCON_FLASH_PAGE_FLIP_NORMAL Setting */
+#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED ((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */
+#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                                                         \
+	(MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                                                            \
+	 << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Setting */
+
+#define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */
+#define MXC_F_GCR_SCON_CCACHE_FLUSH                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS))	 /**< SCON_CCACHE_FLUSH Mask */
+#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL ((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */
+#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL                                                                             \
+	(MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL Setting */
+#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH ((uint32_t)0x1UL)					/**< SCON_CCACHE_FLUSH_FLUSH Value */
+#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH                                                                              \
+	(MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH Setting */
+
+#define MXC_F_GCR_SCON_CCHK_POS 13										   /**< SCON_CCHK Position */
+#define MXC_F_GCR_SCON_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCHK_POS)) /**< SCON_CCHK Mask */
+#define MXC_V_GCR_SCON_CCHK_COMPLETE ((uint32_t)0x0UL)					   /**< SCON_CCHK_COMPLETE Value */
+#define MXC_S_GCR_SCON_CCHK_COMPLETE                                                                                   \
+	(MXC_V_GCR_SCON_CCHK_COMPLETE << MXC_F_GCR_SCON_CCHK_POS) /**< SCON_CCHK_COMPLETE Setting */
+#define MXC_V_GCR_SCON_CCHK_START ((uint32_t)0x1UL)			  /**< SCON_CCHK_START Value */
+#define MXC_S_GCR_SCON_CCHK_START (MXC_V_GCR_SCON_CCHK_START << MXC_F_GCR_SCON_CCHK_POS) /**< SCON_CCHK_START Setting  \
+																						  */
+
+#define MXC_F_GCR_SCON_CHKRES_POS 15										   /**< SCON_CHKRES Position */
+#define MXC_F_GCR_SCON_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CHKRES_POS)) /**< SCON_CHKRES Mask */
+#define MXC_V_GCR_SCON_CHKRES_PASS ((uint32_t)0x0UL)						   /**< SCON_CHKRES_PASS Value */
+#define MXC_S_GCR_SCON_CHKRES_PASS                                                                                     \
+	(MXC_V_GCR_SCON_CHKRES_PASS << MXC_F_GCR_SCON_CHKRES_POS) /**< SCON_CHKRES_PASS Setting */
+#define MXC_V_GCR_SCON_CHKRES_FAIL ((uint32_t)0x1UL)		  /**< SCON_CHKRES_FAIL Value */
+#define MXC_S_GCR_SCON_CHKRES_FAIL                                                                                     \
+	(MXC_V_GCR_SCON_CHKRES_FAIL << MXC_F_GCR_SCON_CHKRES_POS) /**< SCON_CHKRES_FAIL Setting */
+
+#define MXC_F_GCR_SCON_OVR_POS 16													/**< SCON_OVR Position */
+#define MXC_F_GCR_SCON_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SCON_OVR_POS))			/**< SCON_OVR Mask */
+#define MXC_V_GCR_SCON_OVR_0_9V ((uint32_t)0x0UL)									/**< SCON_OVR_0_9V Value */
+#define MXC_S_GCR_SCON_OVR_0_9V (MXC_V_GCR_SCON_OVR_0_9V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_0_9V Setting */
+#define MXC_V_GCR_SCON_OVR_1_0V ((uint32_t)0x1UL)									/**< SCON_OVR_1_0V Value */
+#define MXC_S_GCR_SCON_OVR_1_0V (MXC_V_GCR_SCON_OVR_1_0V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_1_0V Setting */
+#define MXC_V_GCR_SCON_OVR_1_1V ((uint32_t)0x2UL)									/**< SCON_OVR_1_1V Value */
+#define MXC_S_GCR_SCON_OVR_1_1V (MXC_V_GCR_SCON_OVR_1_1V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_1_1V Setting */
+
+#define MXC_F_GCR_SCON_MEMPROT_EN_POS 20											   /**< SCON_MEMPROT_EN Position */
+#define MXC_F_GCR_SCON_MEMPROT_EN ((uint32_t)(0x1UL << MXC_F_GCR_SCON_MEMPROT_EN_POS)) /**< SCON_MEMPROT_EN Mask */
+#define MXC_V_GCR_SCON_MEMPROT_EN_DIS ((uint32_t)0x0UL)								   /**< SCON_MEMPROT_EN_DIS Value */
+#define MXC_S_GCR_SCON_MEMPROT_EN_DIS                                                                                  \
+	(MXC_V_GCR_SCON_MEMPROT_EN_DIS << MXC_F_GCR_SCON_MEMPROT_EN_POS) /**< SCON_MEMPROT_EN_DIS Setting */
+#define MXC_V_GCR_SCON_MEMPROT_EN_EN ((uint32_t)0x1UL)				 /**< SCON_MEMPROT_EN_EN Value */
+#define MXC_S_GCR_SCON_MEMPROT_EN_EN                                                                                   \
+	(MXC_V_GCR_SCON_MEMPROT_EN_EN << MXC_F_GCR_SCON_MEMPROT_EN_POS) /**< SCON_MEMPROT_EN_EN Setting */
+
+#define MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS 21 /**< SCON_MEMPROT_KEYSZ Position */
+#define MXC_F_GCR_SCON_MEMPROT_KEYSZ                                                                                   \
+	((uint32_t)(0x1UL << MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS)) /**< SCON_MEMPROT_KEYSZ Mask */
+#define MXC_V_GCR_SCON_MEMPROT_KEYSZ_128 ((uint32_t)0x0UL)	/**< SCON_MEMPROT_KEYSZ_128 Value */
+#define MXC_S_GCR_SCON_MEMPROT_KEYSZ_128                                                                               \
+	(MXC_V_GCR_SCON_MEMPROT_KEYSZ_128 << MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS) /**< SCON_MEMPROT_KEYSZ_128 Setting */
+#define MXC_V_GCR_SCON_MEMPROT_KEYSZ_256 ((uint32_t)0x1UL)				   /**< SCON_MEMPROT_KEYSZ_256 Value */
+#define MXC_S_GCR_SCON_MEMPROT_KEYSZ_256                                                                               \
+	(MXC_V_GCR_SCON_MEMPROT_KEYSZ_256 << MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS) /**< SCON_MEMPROT_KEYSZ_256 Setting */
+
+/**@} end of group GCR_SCON_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_RSTR0 GCR_RSTR0
+ * @brief    Reset.
+ * @{
+ */
+#define MXC_F_GCR_RSTR0_DMA_POS 0										   /**< RSTR0_DMA Position */
+#define MXC_F_GCR_RSTR0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */
+#define MXC_V_GCR_RSTR0_DMA_RESET_DONE ((uint32_t)0x0UL)				   /**< RSTR0_DMA_RESET_DONE Value */
+#define MXC_S_GCR_RSTR0_DMA_RESET_DONE                                                                                 \
+	(MXC_V_GCR_RSTR0_DMA_RESET_DONE << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */
+#define MXC_V_GCR_RSTR0_DMA_BUSY ((uint32_t)0x1UL)				/**< RSTR0_DMA_BUSY Value */
+#define MXC_S_GCR_RSTR0_DMA_BUSY (MXC_V_GCR_RSTR0_DMA_BUSY << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */
+
+#define MXC_F_GCR_RSTR0_WDT_POS 1										   /**< RSTR0_WDT Position */
+#define MXC_F_GCR_RSTR0_WDT ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */
+
+#define MXC_F_GCR_RSTR0_GPIO0_POS 2											   /**< RSTR0_GPIO0 Position */
+#define MXC_F_GCR_RSTR0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */
+
+#define MXC_F_GCR_RSTR0_GPIO1_POS 3											   /**< RSTR0_GPIO1 Position */
+#define MXC_F_GCR_RSTR0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO1_POS)) /**< RSTR0_GPIO1 Mask */
+
+#define MXC_F_GCR_RSTR0_TIMER0_POS 5											 /**< RSTR0_TIMER0 Position */
+#define MXC_F_GCR_RSTR0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */
+
+#define MXC_F_GCR_RSTR0_TIMER1_POS 6											 /**< RSTR0_TIMER1 Position */
+#define MXC_F_GCR_RSTR0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */
+
+#define MXC_F_GCR_RSTR0_TIMER2_POS 7											 /**< RSTR0_TIMER2 Position */
+#define MXC_F_GCR_RSTR0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */
+
+#define MXC_F_GCR_RSTR0_TIMER3_POS 8											 /**< RSTR0_TIMER3 Position */
+#define MXC_F_GCR_RSTR0_TIMER3 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER3_POS)) /**< RSTR0_TIMER3 Mask */
+
+#define MXC_F_GCR_RSTR0_UART0_POS 11										   /**< RSTR0_UART0 Position */
+#define MXC_F_GCR_RSTR0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */
+
+#define MXC_F_GCR_RSTR0_SPI0_POS 13											 /**< RSTR0_SPI0 Position */
+#define MXC_F_GCR_RSTR0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask */
+
+#define MXC_F_GCR_RSTR0_SPI1_POS 14											 /**< RSTR0_SPI1 Position */
+#define MXC_F_GCR_RSTR0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask */
+
+#define MXC_F_GCR_RSTR0_I2C0_POS 16											 /**< RSTR0_I2C0 Position */
+#define MXC_F_GCR_RSTR0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask */
+
+#define MXC_F_GCR_RSTR0_CRYPTO_POS 18											 /**< RSTR0_CRYPTO Position */
+#define MXC_F_GCR_RSTR0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_CRYPTO_POS)) /**< RSTR0_CRYPTO Mask */
+
+#define MXC_F_GCR_RSTR0_SMPHR_POS 22										   /**< RSTR0_SMPHR Position */
+#define MXC_F_GCR_RSTR0_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SMPHR_POS)) /**< RSTR0_SMPHR Mask */
+
+#define MXC_F_GCR_RSTR0_TRNG_POS 24											 /**< RSTR0_TRNG Position */
+#define MXC_F_GCR_RSTR0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TRNG_POS)) /**< RSTR0_TRNG Mask */
+
+#define MXC_F_GCR_RSTR0_SRST_POS 29											 /**< RSTR0_SRST Position */
+#define MXC_F_GCR_RSTR0_SRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask */
+
+#define MXC_F_GCR_RSTR0_PRST_POS 30											 /**< RSTR0_PRST Position */
+#define MXC_F_GCR_RSTR0_PRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask */
+
+#define MXC_F_GCR_RSTR0_SYSTEM_POS 31											 /**< RSTR0_SYSTEM Position */
+#define MXC_F_GCR_RSTR0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */
+
+/**@} end of group GCR_RSTR0_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_CLKCN GCR_CLKCN
+ * @brief    Clock Control.
+ * @{
+ */
+#define MXC_F_GCR_CLKCN_PSC_POS 6														 /**< CLKCN_PSC Position */
+#define MXC_F_GCR_CLKCN_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS))				 /**< CLKCN_PSC Mask */
+#define MXC_V_GCR_CLKCN_PSC_DIV1 ((uint32_t)0x0UL)										 /**< CLKCN_PSC_DIV1 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV1 (MXC_V_GCR_CLKCN_PSC_DIV1 << MXC_F_GCR_CLKCN_PSC_POS)	 /**< CLKCN_PSC_DIV1 Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV2 ((uint32_t)0x1UL)										 /**< CLKCN_PSC_DIV2 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV2 (MXC_V_GCR_CLKCN_PSC_DIV2 << MXC_F_GCR_CLKCN_PSC_POS)	 /**< CLKCN_PSC_DIV2 Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV4 ((uint32_t)0x2UL)										 /**< CLKCN_PSC_DIV4 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV4 (MXC_V_GCR_CLKCN_PSC_DIV4 << MXC_F_GCR_CLKCN_PSC_POS)	 /**< CLKCN_PSC_DIV4 Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV8 ((uint32_t)0x3UL)										 /**< CLKCN_PSC_DIV8 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV8 (MXC_V_GCR_CLKCN_PSC_DIV8 << MXC_F_GCR_CLKCN_PSC_POS)	 /**< CLKCN_PSC_DIV8 Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV16 ((uint32_t)0x4UL)										 /**< CLKCN_PSC_DIV16 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV16 (MXC_V_GCR_CLKCN_PSC_DIV16 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting  \
+																						  */
+#define MXC_V_GCR_CLKCN_PSC_DIV32 ((uint32_t)0x5UL)										 /**< CLKCN_PSC_DIV32 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV32 (MXC_V_GCR_CLKCN_PSC_DIV32 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting  \
+																						  */
+#define MXC_V_GCR_CLKCN_PSC_DIV64 ((uint32_t)0x6UL)										 /**< CLKCN_PSC_DIV64 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV64 (MXC_V_GCR_CLKCN_PSC_DIV64 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting  \
+																						  */
+#define MXC_V_GCR_CLKCN_PSC_DIV128 ((uint32_t)0x7UL)									 /**< CLKCN_PSC_DIV128 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV128                                                                                     \
+	(MXC_V_GCR_CLKCN_PSC_DIV128 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */
+
+#define MXC_F_GCR_CLKCN_CLKSEL_POS 9											 /**< CLKCN_CLKSEL Position */
+#define MXC_F_GCR_CLKCN_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */
+#define MXC_V_GCR_CLKCN_CLKSEL_HIRC ((uint32_t)0x0UL)							 /**< CLKCN_CLKSEL_HIRC Value */
+#define MXC_S_GCR_CLKCN_CLKSEL_HIRC                                                                                    \
+	(MXC_V_GCR_CLKCN_CLKSEL_HIRC << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */
+#define MXC_V_GCR_CLKCN_CLKSEL_LIRC8 ((uint32_t)0x3UL)			/**< CLKCN_CLKSEL_LIRC8 Value */
+#define MXC_S_GCR_CLKCN_CLKSEL_LIRC8                                                                                   \
+	(MXC_V_GCR_CLKCN_CLKSEL_LIRC8 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_LIRC8 Setting */
+#define MXC_V_GCR_CLKCN_CLKSEL_HIRC8 ((uint32_t)0x5UL)			 /**< CLKCN_CLKSEL_HIRC8 Value */
+#define MXC_S_GCR_CLKCN_CLKSEL_HIRC8                                                                                   \
+	(MXC_V_GCR_CLKCN_CLKSEL_HIRC8 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC8 Setting */
+
+#define MXC_F_GCR_CLKCN_CKRDY_POS 13										   /**< CLKCN_CKRDY Position */
+#define MXC_F_GCR_CLKCN_CKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */
+#define MXC_V_GCR_CLKCN_CKRDY_BUSY ((uint32_t)0x0UL)						   /**< CLKCN_CKRDY_BUSY Value */
+#define MXC_S_GCR_CLKCN_CKRDY_BUSY                                                                                     \
+	(MXC_V_GCR_CLKCN_CKRDY_BUSY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */
+#define MXC_V_GCR_CLKCN_CKRDY_READY ((uint32_t)0x1UL)		  /**< CLKCN_CKRDY_READY Value */
+#define MXC_S_GCR_CLKCN_CKRDY_READY                                                                                    \
+	(MXC_V_GCR_CLKCN_CKRDY_READY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */
+
+#define MXC_F_GCR_CLKCN_HIRC_EN_POS 18											   /**< CLKCN_HIRC_EN Position */
+#define MXC_F_GCR_CLKCN_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */
+#define MXC_V_GCR_CLKCN_HIRC_EN_DIS ((uint32_t)0x0UL)							   /**< CLKCN_HIRC_EN_DIS Value */
+#define MXC_S_GCR_CLKCN_HIRC_EN_DIS                                                                                    \
+	(MXC_V_GCR_CLKCN_HIRC_EN_DIS << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */
+#define MXC_V_GCR_CLKCN_HIRC_EN_EN ((uint32_t)0x1UL)			 /**< CLKCN_HIRC_EN_EN Value */
+#define MXC_S_GCR_CLKCN_HIRC_EN_EN                                                                                     \
+	(MXC_V_GCR_CLKCN_HIRC_EN_EN << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */
+
+#define MXC_F_GCR_CLKCN_HIRC8M_EN_POS 20											   /**< CLKCN_HIRC8M_EN Position */
+#define MXC_F_GCR_CLKCN_HIRC8M_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_EN_POS)) /**< CLKCN_HIRC8M_EN Mask */
+
+#define MXC_F_GCR_CLKCN_HIRC8M_VS_POS 21											   /**< CLKCN_HIRC8M_VS Position */
+#define MXC_F_GCR_CLKCN_HIRC8M_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_VS_POS)) /**< CLKCN_HIRC8M_VS Mask */
+#define MXC_V_GCR_CLKCN_HIRC8M_VS_VCOR ((uint32_t)0x0UL) /**< CLKCN_HIRC8M_VS_VCOR Value */
+#define MXC_S_GCR_CLKCN_HIRC8M_VS_VCOR                                                                                 \
+	(MXC_V_GCR_CLKCN_HIRC8M_VS_VCOR << MXC_F_GCR_CLKCN_HIRC8M_VS_POS) /**< CLKCN_HIRC8M_VS_VCOR Setting */
+#define MXC_V_GCR_CLKCN_HIRC8M_VS_1V ((uint32_t)0x1UL)				  /**< CLKCN_HIRC8M_VS_1V Value */
+#define MXC_S_GCR_CLKCN_HIRC8M_VS_1V                                                                                   \
+	(MXC_V_GCR_CLKCN_HIRC8M_VS_1V << MXC_F_GCR_CLKCN_HIRC8M_VS_POS) /**< CLKCN_HIRC8M_VS_1V Setting */
+
+#define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26												 /**< CLKCN_HIRC_RDY Position */
+#define MXC_F_GCR_CLKCN_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */
+#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT ((uint32_t)0x0UL)								 /**< CLKCN_HIRC_RDY_NOT Value */
+#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT                                                                                   \
+	(MXC_V_GCR_CLKCN_HIRC_RDY_NOT << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */
+#define MXC_V_GCR_CLKCN_HIRC_RDY_READY ((uint32_t)0x1UL)		   /**< CLKCN_HIRC_RDY_READY Value */
+#define MXC_S_GCR_CLKCN_HIRC_RDY_READY                                                                                 \
+	(MXC_V_GCR_CLKCN_HIRC_RDY_READY << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */
+
+#define MXC_F_GCR_CLKCN_HIRC8M_RDY_POS 28 /**< CLKCN_HIRC8M_RDY Position */
+#define MXC_F_GCR_CLKCN_HIRC8M_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_RDY_POS)) /**< CLKCN_HIRC8M_RDY Mask */
+
+#define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */
+#define MXC_F_GCR_CLKCN_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY Mask */
+
+/**@} end of group GCR_CLKCN_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PM GCR_PM
+ * @brief    Power Management.
+ * @{
+ */
+#define MXC_F_GCR_PM_MODE_POS 0														 /**< PM_MODE Position */
+#define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS))				 /**< PM_MODE Mask */
+#define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL)									 /**< PM_MODE_ACTIVE Value */
+#define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
+#define MXC_V_GCR_PM_MODE_DEEPSLEEP ((uint32_t)0x2UL)								 /**< PM_MODE_DEEPSLEEP Value */
+#define MXC_S_GCR_PM_MODE_DEEPSLEEP                                                                                    \
+	(MXC_V_GCR_PM_MODE_DEEPSLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_DEEPSLEEP Setting */
+#define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL)	   /**< PM_MODE_SHUTDOWN Value */
+#define MXC_S_GCR_PM_MODE_SHUTDOWN                                                                                     \
+	(MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS)							 /**< PM_MODE_SHUTDOWN Setting */
+#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL)									 /**< PM_MODE_BACKUP Value */
+#define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
+
+#define MXC_F_GCR_PM_GPIOWKEN_POS 4											   /**< PM_GPIOWKEN Position */
+#define MXC_F_GCR_PM_GPIOWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */
+#define MXC_V_GCR_PM_GPIOWKEN_DIS ((uint32_t)0x0UL)							   /**< PM_GPIOWKEN_DIS Value */
+#define MXC_S_GCR_PM_GPIOWKEN_DIS                                                                                      \
+	(MXC_V_GCR_PM_GPIOWKEN_DIS << MXC_F_GCR_PM_GPIOWKEN_POS)							 /**< PM_GPIOWKEN_DIS Setting */
+#define MXC_V_GCR_PM_GPIOWKEN_EN ((uint32_t)0x1UL)										 /**< PM_GPIOWKEN_EN Value */
+#define MXC_S_GCR_PM_GPIOWKEN_EN (MXC_V_GCR_PM_GPIOWKEN_EN << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting   \
+																						  */
+
+#define MXC_F_GCR_PM_HIRCPD_POS 15										   /**< PM_HIRCPD Position */
+#define MXC_F_GCR_PM_HIRCPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */
+#define MXC_V_GCR_PM_HIRCPD_ACTIVE ((uint32_t)0x0UL)					   /**< PM_HIRCPD_ACTIVE Value */
+#define MXC_S_GCR_PM_HIRCPD_ACTIVE                                                                                     \
+	(MXC_V_GCR_PM_HIRCPD_ACTIVE << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */
+#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP ((uint32_t)0x1UL)		/**< PM_HIRCPD_DEEPSLEEP Value */
+#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP                                                                                  \
+	(MXC_V_GCR_PM_HIRCPD_DEEPSLEEP << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */
+
+#define MXC_F_GCR_PM_HIRC8MPD_POS 17										   /**< PM_HIRC8MPD Position */
+#define MXC_F_GCR_PM_HIRC8MPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRC8MPD_POS)) /**< PM_HIRC8MPD Mask */
+
+/**@} end of group GCR_PM_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PCKDIV GCR_PCKDIV
+ * @brief    Peripheral Clock Divider.
+ * @{
+ */
+#define MXC_F_GCR_PCKDIV_PCF_POS 0											 /**< PCKDIV_PCF Position */
+#define MXC_F_GCR_PCKDIV_PCF ((uint32_t)(0x7UL << MXC_F_GCR_PCKDIV_PCF_POS)) /**< PCKDIV_PCF Mask */
+#define MXC_V_GCR_PCKDIV_PCF_96MHZ ((uint32_t)0x2UL)						 /**< PCKDIV_PCF_96MHZ Value */
+#define MXC_S_GCR_PCKDIV_PCF_96MHZ                                                                                     \
+	(MXC_V_GCR_PCKDIV_PCF_96MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_96MHZ Setting */
+#define MXC_V_GCR_PCKDIV_PCF_48MHZ ((uint32_t)0x3UL)		 /**< PCKDIV_PCF_48MHZ Value */
+#define MXC_S_GCR_PCKDIV_PCF_48MHZ                                                                                     \
+	(MXC_V_GCR_PCKDIV_PCF_48MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_48MHZ Setting */
+#define MXC_V_GCR_PCKDIV_PCF_24MHZ ((uint32_t)0x4UL)		 /**< PCKDIV_PCF_24MHZ Value */
+#define MXC_S_GCR_PCKDIV_PCF_24MHZ                                                                                     \
+	(MXC_V_GCR_PCKDIV_PCF_24MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_24MHZ Setting */
+#define MXC_V_GCR_PCKDIV_PCF_12MHZ ((uint32_t)0x5UL)		 /**< PCKDIV_PCF_12MHZ Value */
+#define MXC_S_GCR_PCKDIV_PCF_12MHZ                                                                                     \
+	(MXC_V_GCR_PCKDIV_PCF_12MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_12MHZ Setting */
+#define MXC_V_GCR_PCKDIV_PCF_6MHZ ((uint32_t)0x6UL)			 /**< PCKDIV_PCF_6MHZ Value */
+#define MXC_S_GCR_PCKDIV_PCF_6MHZ                                                                                      \
+	(MXC_V_GCR_PCKDIV_PCF_6MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_6MHZ Setting */
+#define MXC_V_GCR_PCKDIV_PCF_3MHZ ((uint32_t)0x7UL)			/**< PCKDIV_PCF_3MHZ Value */
+#define MXC_S_GCR_PCKDIV_PCF_3MHZ                                                                                      \
+	(MXC_V_GCR_PCKDIV_PCF_3MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_3MHZ Setting */
+
+#define MXC_F_GCR_PCKDIV_PCFWEN_POS 3											   /**< PCKDIV_PCFWEN Position */
+#define MXC_F_GCR_PCKDIV_PCFWEN ((uint32_t)(0x1UL << MXC_F_GCR_PCKDIV_PCFWEN_POS)) /**< PCKDIV_PCFWEN Mask */
+#define MXC_V_GCR_PCKDIV_PCFWEN_DISABLED ((uint32_t)0x0UL)						   /**< PCKDIV_PCFWEN_DISABLED Value */
+#define MXC_S_GCR_PCKDIV_PCFWEN_DISABLED                                                                               \
+	(MXC_V_GCR_PCKDIV_PCFWEN_DISABLED << MXC_F_GCR_PCKDIV_PCFWEN_POS) /**< PCKDIV_PCFWEN_DISABLED Setting */
+#define MXC_V_GCR_PCKDIV_PCFWEN_ENABLED ((uint32_t)0x1UL)			  /**< PCKDIV_PCFWEN_ENABLED Value */
+#define MXC_S_GCR_PCKDIV_PCFWEN_ENABLED                                                                                \
+	(MXC_V_GCR_PCKDIV_PCFWEN_ENABLED << MXC_F_GCR_PCKDIV_PCFWEN_POS) /**< PCKDIV_PCFWEN_ENABLED Setting */
+
+#define MXC_F_GCR_PCKDIV_AONCD_POS 14											 /**< PCKDIV_AONCD Position */
+#define MXC_F_GCR_PCKDIV_AONCD ((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_4 ((uint32_t)0x0UL)							 /**< PCKDIV_AONCD_DIV_4 Value */
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_4                                                                                   \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_4 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_8 ((uint32_t)0x1UL)			 /**< PCKDIV_AONCD_DIV_8 Value */
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_8                                                                                   \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_8 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_16 ((uint32_t)0x2UL)			 /**< PCKDIV_AONCD_DIV_16 Value */
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_16                                                                                  \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_16 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_32 ((uint32_t)0x3UL)			  /**< PCKDIV_AONCD_DIV_32 Value */
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_32                                                                                  \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_32 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */
+
+/**@} end of group GCR_PCKDIV_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PERCKCN0 GCR_PERCKCN0
+ * @brief    Peripheral Clock Disable.
+ * @{
+ */
+#define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0												   /**< PERCKCN0_GPIO0D Position */
+#define MXC_F_GCR_PERCKCN0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D Mask */
+#define MXC_V_GCR_PERCKCN0_GPIO0D_EN ((uint32_t)0x0UL)								   /**< PERCKCN0_GPIO0D_EN Value */
+#define MXC_S_GCR_PERCKCN0_GPIO0D_EN                                                                                   \
+	(MXC_V_GCR_PERCKCN0_GPIO0D_EN << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */
+#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS ((uint32_t)0x1UL)				/**< PERCKCN0_GPIO0D_DIS Value */
+#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS                                                                                  \
+	(MXC_V_GCR_PERCKCN0_GPIO0D_DIS << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */
+
+#define MXC_F_GCR_PERCKCN0_GPIO1D_POS 1												   /**< PERCKCN0_GPIO1D Position */
+#define MXC_F_GCR_PERCKCN0_GPIO1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO1D_POS)) /**< PERCKCN0_GPIO1D Mask */
+
+#define MXC_F_GCR_PERCKCN0_DMAD_POS 5											   /**< PERCKCN0_DMAD Position */
+#define MXC_F_GCR_PERCKCN0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */
+
+#define MXC_F_GCR_PERCKCN0_SPI0D_POS 6												 /**< PERCKCN0_SPI0D Position */
+#define MXC_F_GCR_PERCKCN0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */
+
+#define MXC_F_GCR_PERCKCN0_SPI1D_POS 7												 /**< PERCKCN0_SPI1D Position */
+#define MXC_F_GCR_PERCKCN0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */
+
+#define MXC_F_GCR_PERCKCN0_UART0D_POS 9												   /**< PERCKCN0_UART0D Position */
+#define MXC_F_GCR_PERCKCN0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D Mask */
+
+#define MXC_F_GCR_PERCKCN0_I2C0D_POS 13												 /**< PERCKCN0_I2C0D Position */
+#define MXC_F_GCR_PERCKCN0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */
+
+#define MXC_F_GCR_PERCKCN0_CRYPTOD_POS 14 /**< PERCKCN0_CRYPTOD Position */
+#define MXC_F_GCR_PERCKCN0_CRYPTOD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_CRYPTOD_POS)) /**< PERCKCN0_CRYPTOD Mask */
+
+#define MXC_F_GCR_PERCKCN0_T0D_POS 15											 /**< PERCKCN0_T0D Position */
+#define MXC_F_GCR_PERCKCN0_T0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */
+
+#define MXC_F_GCR_PERCKCN0_T1D_POS 16											 /**< PERCKCN0_T1D Position */
+#define MXC_F_GCR_PERCKCN0_T1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */
+
+#define MXC_F_GCR_PERCKCN0_T2D_POS 17											 /**< PERCKCN0_T2D Position */
+#define MXC_F_GCR_PERCKCN0_T2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */
+
+#define MXC_F_GCR_PERCKCN0_T3D_POS 18											 /**< PERCKCN0_T3D Position */
+#define MXC_F_GCR_PERCKCN0_T3D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T3D_POS)) /**< PERCKCN0_T3D Mask */
+
+/**@} end of group GCR_PERCKCN0_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_MEMCKCN GCR_MEMCKCN
+ * @brief    Memory Clock Control Register.
+ * @{
+ */
+#define MXC_F_GCR_MEMCKCN_FWS_POS 0											   /**< MEMCKCN_FWS Position */
+#define MXC_F_GCR_MEMCKCN_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */
+
+#define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 16 /**< MEMCKCN_SYSRAM0LS Position */
+#define MXC_F_GCR_MEMCKCN_SYSRAM0LS                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS))	 /**< MEMCKCN_SYSRAM0LS Mask */
+#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */
+#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                                                             \
+	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE Setting */
+#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP ((uint32_t)0x1UL)			/**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */
+#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                                                                        \
+	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                                                                           \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Setting */
+
+#define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 17 /**< MEMCKCN_SYSRAM1LS Position */
+#define MXC_F_GCR_MEMCKCN_SYSRAM1LS                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS Mask */
+
+#define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 18 /**< MEMCKCN_SYSRAM2LS Position */
+#define MXC_F_GCR_MEMCKCN_SYSRAM2LS                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS Mask */
+
+#define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 19 /**< MEMCKCN_SYSRAM3LS Position */
+#define MXC_F_GCR_MEMCKCN_SYSRAM3LS                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS Mask */
+
+#define MXC_F_GCR_MEMCKCN_SYSRAM4LS_POS 20 /**< MEMCKCN_SYSRAM4LS Position */
+#define MXC_F_GCR_MEMCKCN_SYSRAM4LS                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM4LS_POS)) /**< MEMCKCN_SYSRAM4LS Mask */
+
+#define MXC_F_GCR_MEMCKCN_ICACHELS_POS 24 /**< MEMCKCN_ICACHELS Position */
+#define MXC_F_GCR_MEMCKCN_ICACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS Mask */
+
+#define MXC_F_GCR_MEMCKCN_ROMLS_POS 29											   /**< MEMCKCN_ROMLS Position */
+#define MXC_F_GCR_MEMCKCN_ROMLS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ROMLS_POS)) /**< MEMCKCN_ROMLS Mask */
+
+/**@} end of group GCR_MEMCKCN_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_MEMZCN GCR_MEMZCN
+ * @brief    Memory Zeroize Control.
+ * @{
+ */
+#define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0											   /**< MEMZCN_SRAM0Z Position */
+#define MXC_F_GCR_MEMZCN_SRAM0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */
+#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP ((uint32_t)0x0UL)							   /**< MEMZCN_SRAM0Z_NOP Value */
+#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP                                                                                    \
+	(MXC_V_GCR_MEMZCN_SRAM0Z_NOP << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */
+#define MXC_V_GCR_MEMZCN_SRAM0Z_START ((uint32_t)0x1UL)			 /**< MEMZCN_SRAM0Z_START Value */
+#define MXC_S_GCR_MEMZCN_SRAM0Z_START                                                                                  \
+	(MXC_V_GCR_MEMZCN_SRAM0Z_START << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */
+
+#define MXC_F_GCR_MEMZCN_SRAM1Z_POS 1											   /**< MEMZCN_SRAM1Z Position */
+#define MXC_F_GCR_MEMZCN_SRAM1Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM1Z_POS)) /**< MEMZCN_SRAM1Z Mask */
+
+#define MXC_F_GCR_MEMZCN_SRAM2Z_POS 2											   /**< MEMZCN_SRAM2Z Position */
+#define MXC_F_GCR_MEMZCN_SRAM2Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM2Z_POS)) /**< MEMZCN_SRAM2Z Mask */
+
+#define MXC_F_GCR_MEMZCN_SRAM3Z_POS 3											   /**< MEMZCN_SRAM3Z Position */
+#define MXC_F_GCR_MEMZCN_SRAM3Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM3Z_POS)) /**< MEMZCN_SRAM3Z Mask */
+
+#define MXC_F_GCR_MEMZCN_SRAM4Z_POS 4											   /**< MEMZCN_SRAM4Z Position */
+#define MXC_F_GCR_MEMZCN_SRAM4Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM4Z_POS)) /**< MEMZCN_SRAM4Z Mask */
+
+#define MXC_F_GCR_MEMZCN_ICACHEZ_POS 8												 /**< MEMZCN_ICACHEZ Position */
+#define MXC_F_GCR_MEMZCN_ICACHEZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */
+
+/**@} end of group GCR_MEMZCN_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_SYSST GCR_SYSST
+ * @brief    System Status Register.
+ * @{
+ */
+#define MXC_F_GCR_SYSST_ICECLOCK_POS 0												 /**< SYSST_ICECLOCK Position */
+#define MXC_F_GCR_SYSST_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */
+#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED ((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */
+#define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED                                                                              \
+	(MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting */
+#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED ((uint32_t)0x1UL)				/**< SYSST_ICECLOCK_LOCKED Value */
+#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED                                                                                \
+	(MXC_V_GCR_SYSST_ICECLOCK_LOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting */
+
+/**@} end of group GCR_SYSST_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_RSTR1 GCR_RSTR1
+ * @brief    Reset 1.
+ * @{
+ */
+#define MXC_F_GCR_RSTR1_WDT1_POS 8											 /**< RSTR1_WDT1 Position */
+#define MXC_F_GCR_RSTR1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_WDT1_POS)) /**< RSTR1_WDT1 Mask */
+#define MXC_V_GCR_RSTR1_WDT1_RESET_DONE ((uint32_t)0x0UL)					 /**< RSTR1_WDT1_RESET_DONE Value */
+#define MXC_S_GCR_RSTR1_WDT1_RESET_DONE                                                                                \
+	(MXC_V_GCR_RSTR1_WDT1_RESET_DONE << MXC_F_GCR_RSTR1_WDT1_POS) /**< RSTR1_WDT1_RESET_DONE Setting */
+#define MXC_V_GCR_RSTR1_WDT1_BUSY ((uint32_t)0x1UL)				  /**< RSTR1_WDT1_BUSY Value */
+#define MXC_S_GCR_RSTR1_WDT1_BUSY                                                                                      \
+	(MXC_V_GCR_RSTR1_WDT1_BUSY << MXC_F_GCR_RSTR1_WDT1_POS) /**< RSTR1_WDT1_BUSY Setting */
+
+#define MXC_F_GCR_RSTR1_PUFC_POS 27											 /**< RSTR1_PUFC Position */
+#define MXC_F_GCR_RSTR1_PUFC ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_PUFC_POS)) /**< RSTR1_PUFC Mask */
+
+#define MXC_F_GCR_RSTR1_CSPIS_POS 28										   /**< RSTR1_CSPIS Position */
+#define MXC_F_GCR_RSTR1_CSPIS ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_CSPIS_POS)) /**< RSTR1_CSPIS Mask */
+
+/**@} end of group GCR_RSTR1_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PERCKCN1 GCR_PERCKCN1
+ * @brief    Peripheral Clock Disable.
+ * @{
+ */
+#define MXC_F_GCR_PERCKCN1_TRNGD_POS 2												 /**< PERCKCN1_TRNGD Position */
+#define MXC_F_GCR_PERCKCN1_TRNGD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_TRNGD_POS)) /**< PERCKCN1_TRNGD Mask */
+#define MXC_V_GCR_PERCKCN1_TRNGD_EN ((uint32_t)0x0UL)								 /**< PERCKCN1_TRNGD_EN Value */
+#define MXC_S_GCR_PERCKCN1_TRNGD_EN                                                                                    \
+	(MXC_V_GCR_PERCKCN1_TRNGD_EN << MXC_F_GCR_PERCKCN1_TRNGD_POS) /**< PERCKCN1_TRNGD_EN Setting */
+#define MXC_V_GCR_PERCKCN1_TRNGD_DIS ((uint32_t)0x1UL)			  /**< PERCKCN1_TRNGD_DIS Value */
+#define MXC_S_GCR_PERCKCN1_TRNGD_DIS                                                                                   \
+	(MXC_V_GCR_PERCKCN1_TRNGD_DIS << MXC_F_GCR_PERCKCN1_TRNGD_POS) /**< PERCKCN1_TRNGD_DIS Setting */
+
+#define MXC_F_GCR_PERCKCN1_PUFCD_POS 3												 /**< PERCKCN1_PUFCD Position */
+#define MXC_F_GCR_PERCKCN1_PUFCD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_PUFCD_POS)) /**< PERCKCN1_PUFCD Mask */
+
+#define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */
+#define MXC_F_GCR_PERCKCN1_ICACHED ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED Mask */
+
+#define MXC_F_GCR_PERCKCN1_CSPISD_POS 30											   /**< PERCKCN1_CSPISD Position */
+#define MXC_F_GCR_PERCKCN1_CSPISD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_CSPISD_POS)) /**< PERCKCN1_CSPISD Mask */
+
+/**@} end of group GCR_PERCKCN1_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_EVTEN GCR_EVTEN
+ * @brief    Event Enable Register.
+ * @{
+ */
+#define MXC_F_GCR_EVTEN_CPU0DMAEVENT_POS 0 /**< EVTEN_CPU0DMAEVENT Position */
+#define MXC_F_GCR_EVTEN_CPU0DMAEVENT                                                                                   \
+	((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0DMAEVENT_POS)) /**< EVTEN_CPU0DMAEVENT Mask */
+
+#define MXC_F_GCR_EVTEN_CPU0RXEVENT_POS 1 /**< EVTEN_CPU0RXEVENT Position */
+#define MXC_F_GCR_EVTEN_CPU0RXEVENT                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0RXEVENT_POS)) /**< EVTEN_CPU0RXEVENT Mask */
+
+#define MXC_F_GCR_EVTEN_CPU0TXEVENT_POS 2 /**< EVTEN_CPU0TXEVENT Position */
+#define MXC_F_GCR_EVTEN_CPU0TXEVENT                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0TXEVENT_POS)) /**< EVTEN_CPU0TXEVENT Mask */
+
+/**@} end of group GCR_EVTEN_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_REVISION GCR_REVISION
+ * @brief    Revision Register.
+ * @{
+ */
+#define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */
+#define MXC_F_GCR_REVISION_REVISION                                                                                    \
+	((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */
+
+/**@} end of group GCR_REVISION_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_SYSSIE GCR_SYSSIE
+ * @brief    System Status Interrupt Enable Register.
+ * @{
+ */
+#define MXC_F_GCR_SYSSIE_ICEULIE_POS 0												 /**< SYSSIE_ICEULIE Position */
+#define MXC_F_GCR_SYSSIE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */
+#define MXC_V_GCR_SYSSIE_ICEULIE_DIS ((uint32_t)0x0UL)								 /**< SYSSIE_ICEULIE_DIS Value */
+#define MXC_S_GCR_SYSSIE_ICEULIE_DIS                                                                                   \
+	(MXC_V_GCR_SYSSIE_ICEULIE_DIS << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */
+#define MXC_V_GCR_SYSSIE_ICEULIE_EN ((uint32_t)0x1UL)			   /**< SYSSIE_ICEULIE_EN Value */
+#define MXC_S_GCR_SYSSIE_ICEULIE_EN                                                                                    \
+	(MXC_V_GCR_SYSSIE_ICEULIE_EN << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */
+
+/**@} end of group GCR_SYSSIE_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_ECCERR GCR_ECCERR
+ * @brief    ECC Error Register
+ * @{
+ */
+#define MXC_F_GCR_ECCERR_SYSRAM0ECCERR_POS 0 /**< ECCERR_SYSRAM0ECCERR Position */
+#define MXC_F_GCR_ECCERR_SYSRAM0ECCERR                                                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM0ECCERR_POS)) /**< ECCERR_SYSRAM0ECCERR Mask */
+
+#define MXC_F_GCR_ECCERR_SYSRAM1ECCERR_POS 1 /**< ECCERR_SYSRAM1ECCERR Position */
+#define MXC_F_GCR_ECCERR_SYSRAM1ECCERR                                                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM1ECCERR_POS)) /**< ECCERR_SYSRAM1ECCERR Mask */
+
+#define MXC_F_GCR_ECCERR_SYSRAM2ECCERR_POS 2 /**< ECCERR_SYSRAM2ECCERR Position */
+#define MXC_F_GCR_ECCERR_SYSRAM2ECCERR                                                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM2ECCERR_POS)) /**< ECCERR_SYSRAM2ECCERR Mask */
+
+#define MXC_F_GCR_ECCERR_SYSRAM3ECCERR_POS 3 /**< ECCERR_SYSRAM3ECCERR Position */
+#define MXC_F_GCR_ECCERR_SYSRAM3ECCERR                                                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM3ECCERR_POS)) /**< ECCERR_SYSRAM3ECCERR Mask */
+
+#define MXC_F_GCR_ECCERR_SYSRAM4ECCERR_POS 4 /**< ECCERR_SYSRAM4ECCERR Position */
+#define MXC_F_GCR_ECCERR_SYSRAM4ECCERR                                                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM4ECCERR_POS)) /**< ECCERR_SYSRAM4ECCERR Mask */
+
+/**@} end of group GCR_ECCERR_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_ECCNDED GCR_ECCNDED
+ * @brief    ECC Not Double Error Detect Register
+ * @{
+ */
+#define MXC_F_GCR_ECCNDED_SYSRAM0ECCNDED_POS 0 /**< ECCNDED_SYSRAM0ECCNDED Position */
+#define MXC_F_GCR_ECCNDED_SYSRAM0ECCNDED                                                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM0ECCNDED_POS)) /**< ECCNDED_SYSRAM0ECCNDED Mask */
+
+#define MXC_F_GCR_ECCNDED_SYSRAM1ECCNDED_POS 1 /**< ECCNDED_SYSRAM1ECCNDED Position */
+#define MXC_F_GCR_ECCNDED_SYSRAM1ECCNDED                                                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM1ECCNDED_POS)) /**< ECCNDED_SYSRAM1ECCNDED Mask */
+
+#define MXC_F_GCR_ECCNDED_SYSRAM2ECCNDED_POS 2 /**< ECCNDED_SYSRAM2ECCNDED Position */
+#define MXC_F_GCR_ECCNDED_SYSRAM2ECCNDED                                                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM2ECCNDED_POS)) /**< ECCNDED_SYSRAM2ECCNDED Mask */
+
+#define MXC_F_GCR_ECCNDED_SYSRAM3ECCNDED_POS 3 /**< ECCNDED_SYSRAM3ECCNDED Position */
+#define MXC_F_GCR_ECCNDED_SYSRAM3ECCNDED                                                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM3ECCNDED_POS)) /**< ECCNDED_SYSRAM3ECCNDED Mask */
+
+#define MXC_F_GCR_ECCNDED_SYSRAM4ECCNDED_POS 4 /**< ECCNDED_SYSRAM4ECCNDED Position */
+#define MXC_F_GCR_ECCNDED_SYSRAM4ECCNDED                                                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM4ECCNDED_POS)) /**< ECCNDED_SYSRAM4ECCNDED Mask */
+
+/**@} end of group GCR_ECCNDED_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_ECCIRQEN GCR_ECCIRQEN
+ * @brief    ECC IRQ Enable Register
+ * @{
+ */
+#define MXC_F_GCR_ECCIRQEN_ECCERAD_POS 0 /**< ECCIRQEN_ECCERAD Position */
+#define MXC_F_GCR_ECCIRQEN_ECCERAD                                                                                     \
+	((uint32_t)(0x7FFFFFFFUL << MXC_F_GCR_ECCIRQEN_ECCERAD_POS)) /**< ECCIRQEN_ECCERAD Mask */
+
+/**@} end of group GCR_ECCIRQEN_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_ECCERRAD GCR_ECCERRAD
+ * @brief    ECC Error Address Register
+ * @{
+ */
+#define MXC_F_GCR_ECCERRAD_ECCERAD_POS 0 /**< ECCERRAD_ECCERAD Position */
+#define MXC_F_GCR_ECCERRAD_ECCERAD                                                                                     \
+	((uint32_t)(0x7FFFFFFFUL << MXC_F_GCR_ECCERRAD_ECCERAD_POS)) /**< ECCERRAD_ECCERAD Mask */
+
+/**@} end of group GCR_ECCERRAD_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GCR_REGS_H_ */

contrib/loaders/flash/max32xxx/max32xxx.inc

@@ -1,6 +0,0 @@
-/* Autogenerated with ../../../../src/helper/bin2char.sh */
-0xdf,0xf8,0x44,0x40,0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x1a,0xd0,0x47,0x68,
-0x47,0x45,0xf7,0xd0,0x22,0x60,0x02,0xf1,0x04,0x02,0x57,0xf8,0x04,0x8b,0xc4,0xf8,
-0x30,0x80,0xa5,0x68,0x45,0xf0,0x01,0x05,0xa5,0x60,0xd4,0xf8,0x08,0x80,0x18,0xf0,
-0x01,0x0f,0xfa,0xd1,0x8f,0x42,0x28,0xbf,0x00,0xf1,0x08,0x07,0x47,0x60,0x01,0x3b,
-0x03,0xb1,0xdf,0xe7,0x00,0xbe,0x00,0xbf,0x00,0x00,0x00,0x40,

contrib/loaders/flash/max32xxx/max32xxx.s

@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/***************************************************************************
- *   Copyright (C) 2016 by Maxim Integrated                                *
- *   Kevin Gillespie <kevin.gillespie@maximintegrated.com                  *
- ***************************************************************************/
-
-.text
-.syntax unified
-.cpu cortex-m3
-.thumb
-.thumb_func
-
-/*
- * Params :
- * r0 = workarea start
- * r1 = workarea end
- * r2 = target address
- * r3 = count (32bit words)
- * r4 = pFLASH_CTRL_BASE
- *
- * Clobbered:
- * r5 = FLASHWRITECMD
- * r7 - rp
- * r8 - wp, tmp
- */
-
-write:
-
-wait_fifo:
-ldr 	r8, [r0, #0]	/* read wp */
-cmp 	r8, #0			/* abort if wp == 0 */
-beq 	exit
-ldr 	r7, [r0, #4]	/* read rp */
-cmp 	r7, r8			/* wait until rp != wp */
-beq 	wait_fifo
-
-mainloop:
-str		r2, [r4, #0x00]	/* FLSH_ADDR - write address */
-add		r2, r2, #4		/* increment target address */
-ldr		r8, [r7], #4
-str		r8, [r4, #0x30]	/* FLSH_DATA0 - write data */
-ldr		r5, [r4, #0x08]	/* FLSH_CN */
-orr		r5, r5, #1
-str		r5, [r4, #0x08]	/* FLSH_CN - enable write */
-busy:
-ldr		r8, [r4, #0x08]	/* FLSH_CN */
-tst		r8, #1
-bne		busy
-
-cmp 	r7, r1			/* wrap rp at end of buffer */
-it  	cs
-addcs	r7, r0, #8		/* skip loader args */
-str 	r7, [r0, #4]	/* store rp */
-subs	r3, r3, #1		/* decrement word count */
-cbz 	r3, exit		/* loop if not done */
-b		wait_fifo
-exit:
-bkpt

contrib/loaders/flash/max32xxx/max32xxx_write.c

@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/***************************************************************************
+ *   Copyright (C) 2015 by Maxim Integrated                                *
+ *   Copyright (C) 2025 Analog Devices, Inc.                               *
+ ***************************************************************************/
+
+/***** Includes *****/
+#ifdef ALGO_TEST
+#include "mxc_device.h"
+#endif
+
+#include "tpu_regs.h"
+#include "gcr_regs.h"
+#include "flc_regs.h"
+#include "algo_options.h"
+
+#ifdef ALGO_TEST
+#include <stdio.h>
+#else
+#define printf(...)
+#endif
+
+/***** Definitions *****/
+#define MXC_BASE_TPU                    ((uint32_t)0x40001000UL)
+#define MXC_TPU                         ((struct mxc_tpu_regs *)MXC_BASE_TPU)
+#define MXC_BASE_GCR                    ((uint32_t)0x40000000UL)
+#define MXC_GCR                         ((struct mxc_gcr_regs *)MXC_BASE_GCR)
+
+/******************************************************************************/
+#define getbyte(temp8)                                                  \
+/* Wait for the Read FIFO to not equal the Write FIFO */                \
+	do { while (*read_ptr == *write_ptr);                               \
+		temp8 = **read_ptr;                                             \
+/* Increment and wrap around the read pointer */                        \
+		if ((*read_ptr + 1) >= (uint8_t *)(work_end - 8 - 256)) {       \
+			*read_ptr = (uint8_t *)(work_start + 8);                    \
+		} else {                                                        \
+			(*read_ptr)++;                                              \
+		}                                                               \
+		len--;                                                          \
+		addr++; } while (0)
+
+/******************************************************************************/
+#ifndef ALGO_TEST
+__attribute__ ((naked, section(".algo")))
+#endif
+void algo_write(uint8_t *work_start, uint8_t *work_end, uint32_t len, uint32_t addr)
+{
+	printf(" > %s starting\n", __func__);
+
+	volatile uint8_t * (*write_ptr) = (volatile uint8_t **)work_start;
+	volatile uint8_t * (*read_ptr) = (volatile uint8_t **)(work_start + 4);
+	uint32_t *flc_base = (uint32_t *)(work_end - 4 - 128);
+	uint32_t *options = (uint32_t *)(work_end - 8 - 128);
+	uint32_t *enc_buffer = (uint32_t *)(work_end - 8 - 256);
+	uint8_t temp8;
+	uint32_t addr_save;
+	int i;
+	struct mxc_flc_regs *MXC_FLC = (struct mxc_flc_regs *)*flc_base;
+
+	printf(" > w%08x r%08x o%08x f%08x b%08x b%08x\n",
+		(uint32_t)write_ptr, (uint32_t)read_ptr, (uint32_t)*options, (uint32_t)*flc_base,
+		(uint32_t)enc_buffer, (uint32_t)(enc_buffer + 256));
+
+	if (*options & OPTIONS_ENC) {
+		/* Enable Memory Protection */
+		MXC_GCR->scon |= MXC_F_GCR_SCON_MEMPROT_EN;
+
+		/* Set the keysize */
+		if (*options & OPTIONS_KEYSIZE)
+			MXC_GCR->scon |= MXC_F_GCR_SCON_MEMPROT_KEYSZ;
+		else
+			MXC_GCR->scon &= ~(MXC_F_GCR_SCON_MEMPROT_KEYSZ);
+	} else {
+		/* Disable memory protection */
+		MXC_GCR->scon &= ~MXC_F_GCR_SCON_MEMPROT_EN;
+	}
+
+	if (*options & OPTIONS_ENC) {
+		/* Setup the AES */
+
+		/* Enable CRYPTO clock */
+		if ((MXC_GCR->clkcn & MXC_F_GCR_CLKCN_HIRC_EN) == 0)
+			MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC_EN;
+
+		/* Disable CRYPTO clock gate */
+		if (MXC_GCR->perckcn0 & MXC_F_GCR_PERCKCN0_CRYPTOD)
+			MXC_GCR->perckcn0 &= ~(MXC_F_GCR_PERCKCN0_CRYPTOD);
+
+		/* Reset Crypto block and clear state */
+		MXC_TPU->ctrl = MXC_F_TPU_CTRL_RST;
+
+		/* Set the legacy bit */
+		MXC_TPU->ctrl |= MXC_F_TPU_CTRL_FLAG_MODE;
+
+		/* Byte swap the input and output */
+		MXC_TPU->ctrl |= MXC_F_TPU_CTRL_BSO;
+		MXC_TPU->ctrl |= MXC_F_TPU_CTRL_BSI;
+	}
+
+	while (len) {
+		if ((*options & OPTIONS_128) == 0) {
+			/* Save the current address before we read from the working area */
+			addr_save = addr;
+
+			/* 32-bit write */
+			MXC_FLC->cn |= MXC_F_FLC_CN_WDTH;
+
+			enc_buffer[0] = 0;
+			for (i = 0; i < 4; i++) {
+				/* Get data from the working area, pad with 0xFF */
+				if (len) {
+					getbyte(temp8);
+					__asm("nop\n");
+				} else {
+					temp8 = 0xFF;
+					__asm("nop\n");
+				}
+				enc_buffer[0] |= (temp8 << (i * 8));
+			}
+
+			/* 32-bit write */
+			MXC_FLC->cn |= MXC_F_FLC_CN_WDTH;
+
+			MXC_FLC->addr = addr_save;
+			MXC_FLC->data[0] = enc_buffer[0];
+
+			/* Enable the write */
+			MXC_FLC->cn |= MXC_F_FLC_CN_WR;
+
+			/* Wait for the operation to complete */
+			do {} while (MXC_FLC->cn & MXC_F_FLC_CN_WR);
+
+			/* Check access violations */
+			if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
+				MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
+				#ifndef ALGO_TEST
+				#ifdef __riscv
+				__asm("ebreak\n");
+				#else
+				__asm("bkpt\n");
+				#endif
+				#else
+				printf(" > Error writing to flash\n");
+				return;
+				#endif
+			}
+		} else {
+			/* Save the current address before we read from the working area */
+			addr_save = addr;
+
+			/* Fill the buffer with the plain text data from the working area */
+			for (i = 0; i < 4; i++) {
+				/* Get data from the working area, pad with 0xFF */
+				enc_buffer[i] = 0;
+				if (len) {
+					getbyte(temp8);
+					__asm("nop\n");
+				} else {
+					temp8 = 0xFF;
+					__asm("nop\n");
+				}
+				enc_buffer[i] |= (temp8 << (0));
+				/* Get data from the working area, pad with 0xFF */
+				if (len) {
+					getbyte(temp8);
+					__asm("nop\n");
+				} else {
+					temp8 = 0xFF;
+					__asm("nop\n");
+				}
+				enc_buffer[i] |= (temp8 << (8));
+				/* Get data from the working area, pad with 0xFF */
+				if (len) {
+					getbyte(temp8);
+					__asm("nop\n");
+				} else {
+					temp8 = 0xFF;
+					__asm("nop\n");
+				}
+				enc_buffer[i] |= (temp8 << (16));
+				/* Get data from the working area, pad with 0xFF */
+				if (len) {
+					getbyte(temp8);
+					__asm("nop\n");
+				} else {
+					temp8 = 0xFF;
+					__asm("nop\n");
+				}
+				enc_buffer[i] |= (temp8 << (24));
+			}
+
+			if (*options & OPTIONS_ENC) {
+				/* XOR data with the address */
+				for (i = 0; i < 4; i++) {
+					if (*options & OPTIONS_RELATIVE_XOR)
+						enc_buffer[i] ^= ((addr_save & 0x00FFFFFF) + i * 4);
+					else
+						enc_buffer[i] ^= (addr_save + i * 4);
+				}
+
+				/* Encrypt the plain text
+				 * Clear interrupt flags*/
+				MXC_TPU->ctrl |= MXC_F_TPU_CTRL_CPH_DONE;
+
+				MXC_TPU->cipher_ctrl = ((0x0 << MXC_F_TPU_CIPHER_CTRL_MODE_POS) |
+					(0x0 << MXC_F_TPU_CIPHER_CTRL_ENC_POS));
+
+				if (*options & OPTIONS_KEYSIZE) {
+					/* ECB, AES-256, encrypt */
+					MXC_TPU->cipher_ctrl |=
+						(0x3 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS);
+				} else {
+					/* ECB, AES-128, encrypt */
+					MXC_TPU->cipher_ctrl |=
+						(0x1 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS);
+				}
+
+				/* Set the key source */
+				MXC_TPU->cipher_ctrl =
+					((MXC_TPU->cipher_ctrl & ~MXC_F_TPU_CIPHER_CTRL_SRC) |
+					(0x3 << MXC_F_TPU_CIPHER_CTRL_SRC_POS));
+
+				/* Copy data to start the operation */
+				MXC_TPU->din[0] = enc_buffer[0];
+				MXC_TPU->din[1] = enc_buffer[1];
+				MXC_TPU->din[2] = enc_buffer[2];
+				MXC_TPU->din[3] = enc_buffer[3];
+
+				/* Wait until operation is complete */
+				do {} while (!(MXC_TPU->ctrl & MXC_F_TPU_CTRL_CPH_DONE));
+
+				/* Copy the data out */
+				enc_buffer[0] = MXC_TPU->dout[0];
+				enc_buffer[1] = MXC_TPU->dout[1];
+				enc_buffer[2] = MXC_TPU->dout[2];
+				enc_buffer[3] = MXC_TPU->dout[3];
+			}
+
+			/* 128-bit write */
+			MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH;
+
+			MXC_FLC->addr = addr_save;
+			MXC_FLC->data[0] = enc_buffer[0];
+			MXC_FLC->data[1] = enc_buffer[1];
+			MXC_FLC->data[2] = enc_buffer[2];
+			MXC_FLC->data[3] = enc_buffer[3];
+
+			/* Enable the write */
+			MXC_FLC->cn |= MXC_F_FLC_CN_WR;
+
+			/* Wait for the operation to complete */
+			do {} while (MXC_FLC->cn & MXC_F_FLC_CN_WR);
+
+			/* Check access violations */
+			if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
+				MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
+				#ifndef ALGO_TEST
+				#ifdef __riscv
+				__asm("ebreak\n");
+				#else
+				__asm("bkpt\n");
+				#endif
+				printf(" > Error writing to flash\n");
+				return;
+				#endif
+			}
+		}
+	}
+
+	#ifndef ALGO_TEST
+	#ifdef __riscv
+	__asm("ebreak\n");
+	#else
+	__asm("bkpt\n");
+	#endif
+	#else
+	printf(" > %s returning\n", __func__);
+	return;
+	#endif
+}

contrib/loaders/flash/max32xxx/max32xxx_write_arm.inc

@@ -0,0 +1,57 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
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contrib/loaders/flash/max32xxx/tpu_regs.h

@@ -0,0 +1,572 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ *   Copyright (C) 2016 by Maxim Integrated                                *
+ *   Copyright (C) 2025 Analog Devices, Inc.                               *
+ ***************************************************************************/
+
+#ifndef _TPU_REGS_H_
+#define _TPU_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__ICCARM__)
+#pragma system_include
+#endif
+
+/*/ @cond */
+/*
+	If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+/*/ @endcond */
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     tpu
+ * @defgroup    tpu_registers Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the TPU Peripheral Module.
+ * @description The Trust Protection Unit used to assist the computationally intensive operations of several common
+ * cryptographic algorithms.
+ */
+
+/**
+ * @ingroup tpu_registers
+ * Structure type to access the TPU Registers.
+ */
+struct mxc_tpu_regs {
+	__IO uint32_t ctrl;			   /**< <tt>\b 0x00:<\tt> TPU CTRL Register */
+	__IO uint32_t cipher_ctrl;	   /**< <tt>\b 0x04:<\tt> TPU CIPHER_CTRL Register */
+	__IO uint32_t hash_ctrl;	   /**< <tt>\b 0x08:<\tt> TPU HASH_CTRL Register */
+	__IO uint32_t crc_ctrl;		   /**< <tt>\b 0x0C:<\tt> TPU CRC_CTRL Register */
+	__IO uint32_t dma_src;		   /**< <tt>\b 0x10:<\tt> TPU DMA_SRC Register */
+	__IO uint32_t dma_dest;		   /**< <tt>\b 0x14:<\tt> TPU DMA_DEST Register */
+	__IO uint32_t dma_cnt;		   /**< <tt>\b 0x18:<\tt> TPU DMA_CNT Register */
+	__IO uint32_t maa_ctrl;		   /**< <tt>\b 0x1C:<\tt> TPU MAA_CTRL Register */
+	__O uint32_t din[4];		   /**< <tt>\b 0x20:<\tt> TPU DIN Register */
+	__I uint32_t dout[4];		   /**< <tt>\b 0x30:<\tt> TPU DOUT Register */
+	__IO uint32_t crc_poly;		   /**< <tt>\b 0x40:<\tt> TPU CRC_POLY Register */
+	__IO uint32_t crc_val;		   /**< <tt>\b 0x44:<\tt> TPU CRC_VAL Register */
+	__I uint32_t crc_prng;		   /**< <tt>\b 0x48:<\tt> TPU CRC_PRNG Register */
+	__IO uint32_t ham_ecc;		   /**< <tt>\b 0x4C:<\tt> TPU HAM_ECC Register */
+	__IO uint32_t cipher_init[4];  /**< <tt>\b 0x50:<\tt> TPU CIPHER_INIT Register */
+	__O uint32_t cipher_key[8];	   /**< <tt>\b 0x60:<\tt> TPU CIPHER_KEY Register */
+	__IO uint32_t hash_digest[16]; /**< <tt>\b 0x80:<\tt> TPU HASH_DIGEST Register */
+	__IO uint32_t hash_msg_sz[4];  /**< <tt>\b 0xC0:<\tt> TPU HASH_MSG_SZ Register */
+	__IO uint32_t maa_maws;		   /**< <tt>\b 0xD0:<\tt> TPU MAA_MAWS Register */
+};
+
+/* Register offsets for module TPU */
+/**
+ * @ingroup    tpu_registers
+ * @defgroup   TPU_Register_Offsets Register Offsets
+ * @brief      TPU Peripheral Register Offsets from the TPU Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_TPU_CTRL ((uint32_t)0x00000000UL)		   /**< Offset from TPU Base Address: <tt> 0x0x000 */
+#define MXC_R_TPU_CIPHER_CTRL ((uint32_t)0x00000004UL) /**< Offset from TPU Base Address: <tt> 0x0x004 */
+#define MXC_R_TPU_HASH_CTRL ((uint32_t)0x00000008UL)   /**< Offset from TPU Base Address: <tt> 0x0x008 */
+#define MXC_R_TPU_CRC_CTRL ((uint32_t)0x0000000CUL)	   /**< Offset from TPU Base Address: <tt> 0x0x00C */
+#define MXC_R_TPU_DMA_SRC ((uint32_t)0x00000010UL)	   /**< Offset from TPU Base Address: <tt> 0x0x010 */
+#define MXC_R_TPU_DMA_DEST ((uint32_t)0x00000014UL)	   /**< Offset from TPU Base Address: <tt> 0x0x014 */
+#define MXC_R_TPU_DMA_CNT ((uint32_t)0x00000018UL)	   /**< Offset from TPU Base Address: <tt> 0x0x018 */
+#define MXC_R_TPU_MAA_CTRL ((uint32_t)0x0000001CUL)	   /**< Offset from TPU Base Address: <tt> 0x0x01C */
+#define MXC_R_TPU_DIN ((uint32_t)0x00000020UL)		   /**< Offset from TPU Base Address: <tt> 0x0x020 */
+#define MXC_R_TPU_DOUT ((uint32_t)0x00000030UL)		   /**< Offset from TPU Base Address: <tt> 0x0x030 */
+#define MXC_R_TPU_CRC_POLY ((uint32_t)0x00000040UL)	   /**< Offset from TPU Base Address: <tt> 0x0x040 */
+#define MXC_R_TPU_CRC_VAL ((uint32_t)0x00000044UL)	   /**< Offset from TPU Base Address: <tt> 0x0x044 */
+#define MXC_R_TPU_CRC_PRNG ((uint32_t)0x00000048UL)	   /**< Offset from TPU Base Address: <tt> 0x0x048 */
+#define MXC_R_TPU_HAM_ECC ((uint32_t)0x0000004CUL)	   /**< Offset from TPU Base Address: <tt> 0x0x04C */
+#define MXC_R_TPU_CIPHER_INIT ((uint32_t)0x00000050UL) /**< Offset from TPU Base Address: <tt> 0x0x050 */
+#define MXC_R_TPU_CIPHER_KEY ((uint32_t)0x00000060UL)  /**< Offset from TPU Base Address: <tt> 0x0x060 */
+#define MXC_R_TPU_HASH_DIGEST ((uint32_t)0x00000080UL) /**< Offset from TPU Base Address: <tt> 0x0x080 */
+#define MXC_R_TPU_HASH_MSG_SZ ((uint32_t)0x000000C0UL) /**< Offset from TPU Base Address: <tt> 0x0x0C0 */
+#define MXC_R_TPU_MAA_MAWS ((uint32_t)0x000000D0UL)	   /**< Offset from TPU Base Address: <tt> 0x0x0D0 */
+													   /**@} end of group tpu_registers */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup CTRL_Register
+ * @brief    Crypto Control Register.
+ * @{
+ */
+#define MXC_F_TPU_CTRL_RST_POS 0										 /**< CTRL_RST Position */
+#define MXC_F_TPU_CTRL_RST ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_RST_POS)) /**< CTRL_RST Mask */
+
+#define MXC_F_TPU_CTRL_INTR_POS 1										   /**< CTRL_INTR Position */
+#define MXC_F_TPU_CTRL_INTR ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_INTR_POS)) /**< CTRL_INTR Mask */
+
+#define MXC_F_TPU_CTRL_SRC_POS 2										 /**< CTRL_SRC Position */
+#define MXC_F_TPU_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_SRC_POS)) /**< CTRL_SRC Mask */
+
+#define MXC_F_TPU_CTRL_BSO_POS 4										 /**< CTRL_BSO Position */
+#define MXC_F_TPU_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_BSO_POS)) /**< CTRL_BSO Mask */
+
+#define MXC_F_TPU_CTRL_BSI_POS 5										 /**< CTRL_BSI Position */
+#define MXC_F_TPU_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_BSI_POS)) /**< CTRL_BSI Mask */
+
+#define MXC_F_TPU_CTRL_WAIT_EN_POS 6											 /**< CTRL_WAIT_EN Position */
+#define MXC_F_TPU_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_WAIT_EN_POS)) /**< CTRL_WAIT_EN Mask */
+
+#define MXC_F_TPU_CTRL_WAIT_POL_POS 7											   /**< CTRL_WAIT_POL Position */
+#define MXC_F_TPU_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_WAIT_POL_POS)) /**< CTRL_WAIT_POL Mask */
+
+#define MXC_F_TPU_CTRL_WRSRC_POS 8											 /**< CTRL_WRSRC Position */
+#define MXC_F_TPU_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_TPU_CTRL_WRSRC_POS)) /**< CTRL_WRSRC Mask */
+#define MXC_V_TPU_CTRL_WRSRC_NONE ((uint32_t)0x0UL)							 /**< CTRL_WRSRC_NONE Value */
+#define MXC_S_TPU_CTRL_WRSRC_NONE                                                                                      \
+	(MXC_V_TPU_CTRL_WRSRC_NONE << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_NONE Setting */
+#define MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL) /**< CTRL_WRSRC_CIPHEROUTPUT Value */
+#define MXC_S_TPU_CTRL_WRSRC_CIPHEROUTPUT                                                                              \
+	(MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_CIPHEROUTPUT Setting */
+#define MXC_V_TPU_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL)				/**< CTRL_WRSRC_READFIFO Value */
+#define MXC_S_TPU_CTRL_WRSRC_READFIFO                                                                                  \
+	(MXC_V_TPU_CTRL_WRSRC_READFIFO << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_READFIFO Setting */
+#define MXC_V_TPU_CTRL_WRSRC_RFU ((uint32_t)0x3UL)				/**< CTRL_WRSRC_RFU Value */
+#define MXC_S_TPU_CTRL_WRSRC_RFU (MXC_V_TPU_CTRL_WRSRC_RFU << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_RFU Setting */
+
+#define MXC_F_TPU_CTRL_RDSRC_POS 10											 /**< CTRL_RDSRC Position */
+#define MXC_F_TPU_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_TPU_CTRL_RDSRC_POS)) /**< CTRL_RDSRC Mask */
+#define MXC_V_TPU_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL)					 /**< CTRL_RDSRC_DMADISABLED Value */
+#define MXC_S_TPU_CTRL_RDSRC_DMADISABLED                                                                               \
+	(MXC_V_TPU_CTRL_RDSRC_DMADISABLED << MXC_F_TPU_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMADISABLED Setting */
+#define MXC_V_TPU_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL)			   /**< CTRL_RDSRC_DMAORAPB Value */
+#define MXC_S_TPU_CTRL_RDSRC_DMAORAPB                                                                                  \
+	(MXC_V_TPU_CTRL_RDSRC_DMAORAPB << MXC_F_TPU_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMAORAPB Setting */
+#define MXC_V_TPU_CTRL_RDSRC_RNG ((uint32_t)0x2UL)				/**< CTRL_RDSRC_RNG Value */
+#define MXC_S_TPU_CTRL_RDSRC_RNG (MXC_V_TPU_CTRL_RDSRC_RNG << MXC_F_TPU_CTRL_RDSRC_POS) /**< CTRL_RDSRC_RNG Setting */
+
+#define MXC_F_TPU_CTRL_FLAG_MODE_POS 14												 /**< CTRL_FLAG_MODE Position */
+#define MXC_F_TPU_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_FLAG_MODE_POS)) /**< CTRL_FLAG_MODE Mask */
+
+#define MXC_F_TPU_CTRL_DMADNEMSK_POS 15												 /**< CTRL_DMADNEMSK Position */
+#define MXC_F_TPU_CTRL_DMADNEMSK ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DMADNEMSK_POS)) /**< CTRL_DMADNEMSK Mask */
+
+#define MXC_F_TPU_CTRL_DMA_DONE_POS 24											   /**< CTRL_DMA_DONE Position */
+#define MXC_F_TPU_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DMA_DONE_POS)) /**< CTRL_DMA_DONE Mask */
+
+#define MXC_F_TPU_CTRL_GLS_DONE_POS 25											   /**< CTRL_GLS_DONE Position */
+#define MXC_F_TPU_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_GLS_DONE_POS)) /**< CTRL_GLS_DONE Mask */
+
+#define MXC_F_TPU_CTRL_HSH_DONE_POS 26											   /**< CTRL_HSH_DONE Position */
+#define MXC_F_TPU_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_HSH_DONE_POS)) /**< CTRL_HSH_DONE Mask */
+
+#define MXC_F_TPU_CTRL_CPH_DONE_POS 27											   /**< CTRL_CPH_DONE Position */
+#define MXC_F_TPU_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_CPH_DONE_POS)) /**< CTRL_CPH_DONE Mask */
+
+#define MXC_F_TPU_CTRL_MAA_DONE_POS 28											   /**< CTRL_MAA_DONE Position */
+#define MXC_F_TPU_CTRL_MAA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_MAA_DONE_POS)) /**< CTRL_MAA_DONE Mask */
+
+#define MXC_F_TPU_CTRL_ERR_POS 29										 /**< CTRL_ERR Position */
+#define MXC_F_TPU_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_ERR_POS)) /**< CTRL_ERR Mask */
+
+#define MXC_F_TPU_CTRL_RDY_POS 30										 /**< CTRL_RDY Position */
+#define MXC_F_TPU_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
+
+#define MXC_F_TPU_CTRL_DONE_POS 31										   /**< CTRL_DONE Position */
+#define MXC_F_TPU_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DONE_POS)) /**< CTRL_DONE Mask */
+
+/**@} end of group CTRL_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup CIPHER_CTRL_Register
+ * @brief    Cipher Control Register.
+ * @{
+ */
+#define MXC_F_TPU_CIPHER_CTRL_ENC_POS 0												   /**< CIPHER_CTRL_ENC Position */
+#define MXC_F_TPU_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_ENC_POS)) /**< CIPHER_CTRL_ENC Mask */
+
+#define MXC_F_TPU_CIPHER_CTRL_KEY_POS 1												   /**< CIPHER_CTRL_KEY Position */
+#define MXC_F_TPU_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_KEY_POS)) /**< CIPHER_CTRL_KEY Mask */
+
+#define MXC_F_TPU_CIPHER_CTRL_SRC_POS 2												   /**< CIPHER_CTRL_SRC Position */
+#define MXC_F_TPU_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_TPU_CIPHER_CTRL_SRC_POS)) /**< CIPHER_CTRL_SRC Mask */
+#define MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL) /**< CIPHER_CTRL_SRC_CIPHERKEY Value */
+#define MXC_S_TPU_CIPHER_CTRL_SRC_CIPHERKEY                                                                            \
+	(MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_CIPHERKEY Setting */
+#define MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL)				   /**< CIPHER_CTRL_SRC_REGFILE Value */
+#define MXC_S_TPU_CIPHER_CTRL_SRC_REGFILE                                                                              \
+	(MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_REGFILE Setting */
+#define MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL)		 /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Value */
+#define MXC_S_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE                                                                      \
+	(MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE                                                                         \
+	 << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Setting */
+
+#define MXC_F_TPU_CIPHER_CTRL_CIPHER_POS 4 /**< CIPHER_CTRL_CIPHER Position */
+#define MXC_F_TPU_CIPHER_CTRL_CIPHER                                                                                   \
+	((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)) /**< CIPHER_CTRL_CIPHER Mask */
+#define MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL)	/**< CIPHER_CTRL_CIPHER_DIS Value */
+#define MXC_S_TPU_CIPHER_CTRL_CIPHER_DIS                                                                               \
+	(MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DIS Setting */
+#define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL)			   /**< CIPHER_CTRL_CIPHER_AES128 Value */
+#define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES128                                                                            \
+	(MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES128 Setting   \
+																			   */
+#define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL)				  /**< CIPHER_CTRL_CIPHER_AES192 Value */
+#define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES192                                                                            \
+	(MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES192 Setting   \
+																			   */
+#define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL)				  /**< CIPHER_CTRL_CIPHER_AES256 Value */
+#define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES256                                                                            \
+	(MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES256 Setting   \
+																			   */
+#define MXC_V_TPU_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL)					  /**< CIPHER_CTRL_CIPHER_DES Value */
+#define MXC_S_TPU_CIPHER_CTRL_CIPHER_DES                                                                               \
+	(MXC_V_TPU_CIPHER_CTRL_CIPHER_DES << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DES Setting */
+#define MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES ((uint32_t)0x5UL)				   /**< CIPHER_CTRL_CIPHER_TDES Value */
+#define MXC_S_TPU_CIPHER_CTRL_CIPHER_TDES                                                                              \
+	(MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_TDES Setting */
+
+#define MXC_F_TPU_CIPHER_CTRL_MODE_POS 8 /**< CIPHER_CTRL_MODE Position */
+#define MXC_F_TPU_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_MODE_POS)) /**< CIPHER_CTRL_MODE Mask */
+#define MXC_V_TPU_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL) /**< CIPHER_CTRL_MODE_ECB Value */
+#define MXC_S_TPU_CIPHER_CTRL_MODE_ECB                                                                                 \
+	(MXC_V_TPU_CIPHER_CTRL_MODE_ECB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_ECB Setting */
+#define MXC_V_TPU_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL)			   /**< CIPHER_CTRL_MODE_CBC Value */
+#define MXC_S_TPU_CIPHER_CTRL_MODE_CBC                                                                                 \
+	(MXC_V_TPU_CIPHER_CTRL_MODE_CBC << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CBC Setting */
+#define MXC_V_TPU_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL)			   /**< CIPHER_CTRL_MODE_CFB Value */
+#define MXC_S_TPU_CIPHER_CTRL_MODE_CFB                                                                                 \
+	(MXC_V_TPU_CIPHER_CTRL_MODE_CFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CFB Setting */
+#define MXC_V_TPU_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL)			   /**< CIPHER_CTRL_MODE_OFB Value */
+#define MXC_S_TPU_CIPHER_CTRL_MODE_OFB                                                                                 \
+	(MXC_V_TPU_CIPHER_CTRL_MODE_OFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_OFB Setting */
+#define MXC_V_TPU_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL)			   /**< CIPHER_CTRL_MODE_CTR Value */
+#define MXC_S_TPU_CIPHER_CTRL_MODE_CTR                                                                                 \
+	(MXC_V_TPU_CIPHER_CTRL_MODE_CTR << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CTR Setting */
+
+/**@} end of group CIPHER_CTRL_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup HASH_CTRL_Register
+ * @brief    HASH Control Register.
+ * @{
+ */
+#define MXC_F_TPU_HASH_CTRL_INIT_POS 0												 /**< HASH_CTRL_INIT Position */
+#define MXC_F_TPU_HASH_CTRL_INIT ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_INIT_POS)) /**< HASH_CTRL_INIT Mask */
+
+#define MXC_F_TPU_HASH_CTRL_XOR_POS 1											   /**< HASH_CTRL_XOR Position */
+#define MXC_F_TPU_HASH_CTRL_XOR ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_XOR_POS)) /**< HASH_CTRL_XOR Mask */
+
+#define MXC_F_TPU_HASH_CTRL_HASH_POS 2												 /**< HASH_CTRL_HASH Position */
+#define MXC_F_TPU_HASH_CTRL_HASH ((uint32_t)(0x7UL << MXC_F_TPU_HASH_CTRL_HASH_POS)) /**< HASH_CTRL_HASH Mask */
+#define MXC_V_TPU_HASH_CTRL_HASH_DIS ((uint32_t)0x0UL)								 /**< HASH_CTRL_HASH_DIS Value */
+#define MXC_S_TPU_HASH_CTRL_HASH_DIS                                                                                   \
+	(MXC_V_TPU_HASH_CTRL_HASH_DIS << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_DIS Setting */
+#define MXC_V_TPU_HASH_CTRL_HASH_SHA1 ((uint32_t)0x1UL)			   /**< HASH_CTRL_HASH_SHA1 Value */
+#define MXC_S_TPU_HASH_CTRL_HASH_SHA1                                                                                  \
+	(MXC_V_TPU_HASH_CTRL_HASH_SHA1 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA1 Setting */
+#define MXC_V_TPU_HASH_CTRL_HASH_SHA224 ((uint32_t)0x2UL)			/**< HASH_CTRL_HASH_SHA224 Value */
+#define MXC_S_TPU_HASH_CTRL_HASH_SHA224                                                                                \
+	(MXC_V_TPU_HASH_CTRL_HASH_SHA224 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA224 Setting */
+#define MXC_V_TPU_HASH_CTRL_HASH_SHA256 ((uint32_t)0x3UL)			  /**< HASH_CTRL_HASH_SHA256 Value */
+#define MXC_S_TPU_HASH_CTRL_HASH_SHA256                                                                                \
+	(MXC_V_TPU_HASH_CTRL_HASH_SHA256 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA256 Setting */
+#define MXC_V_TPU_HASH_CTRL_HASH_SHA384 ((uint32_t)0x4UL)			  /**< HASH_CTRL_HASH_SHA384 Value */
+#define MXC_S_TPU_HASH_CTRL_HASH_SHA384                                                                                \
+	(MXC_V_TPU_HASH_CTRL_HASH_SHA384 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA384 Setting */
+#define MXC_V_TPU_HASH_CTRL_HASH_SHA512 ((uint32_t)0x5UL)			  /**< HASH_CTRL_HASH_SHA512 Value */
+#define MXC_S_TPU_HASH_CTRL_HASH_SHA512                                                                                \
+	(MXC_V_TPU_HASH_CTRL_HASH_SHA512 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA512 Setting */
+
+#define MXC_F_TPU_HASH_CTRL_LAST_POS 5												 /**< HASH_CTRL_LAST Position */
+#define MXC_F_TPU_HASH_CTRL_LAST ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_LAST_POS)) /**< HASH_CTRL_LAST Mask */
+
+/**@} end of group HASH_CTRL_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup CRC_CTRL_Register
+ * @brief    CRC Control Register.
+ * @{
+ */
+#define MXC_F_TPU_CRC_CTRL_CRC_POS 0											 /**< CRC_CTRL_CRC Position */
+#define MXC_F_TPU_CRC_CTRL_CRC ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_CRC_POS)) /**< CRC_CTRL_CRC Mask */
+
+#define MXC_F_TPU_CRC_CTRL_MSB_POS 1											 /**< CRC_CTRL_MSB Position */
+#define MXC_F_TPU_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_MSB_POS)) /**< CRC_CTRL_MSB Mask */
+
+#define MXC_F_TPU_CRC_CTRL_PRNG_POS 2											   /**< CRC_CTRL_PRNG Position */
+#define MXC_F_TPU_CRC_CTRL_PRNG ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_PRNG_POS)) /**< CRC_CTRL_PRNG Mask */
+
+#define MXC_F_TPU_CRC_CTRL_ENT_POS 3											 /**< CRC_CTRL_ENT Position */
+#define MXC_F_TPU_CRC_CTRL_ENT ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_ENT_POS)) /**< CRC_CTRL_ENT Mask */
+
+#define MXC_F_TPU_CRC_CTRL_HAM_POS 4											 /**< CRC_CTRL_HAM Position */
+#define MXC_F_TPU_CRC_CTRL_HAM ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_HAM_POS)) /**< CRC_CTRL_HAM Mask */
+
+#define MXC_F_TPU_CRC_CTRL_HRST_POS 5											   /**< CRC_CTRL_HRST Position */
+#define MXC_F_TPU_CRC_CTRL_HRST ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_HRST_POS)) /**< CRC_CTRL_HRST Mask */
+
+/**@} end of group CRC_CTRL_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup DMA_SRC_Register
+ * @brief    Crypto DMA Source Address.
+ * @{
+ */
+#define MXC_F_TPU_DMA_SRC_ADDR_POS 0													/**< DMA_SRC_ADDR Position */
+#define MXC_F_TPU_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_SRC_ADDR_POS)) /**< DMA_SRC_ADDR Mask */
+
+/**@} end of group DMA_SRC_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup DMA_DEST_Register
+ * @brief    Crypto DMA Destination Address.
+ * @{
+ */
+#define MXC_F_TPU_DMA_DEST_ADDR_POS 0													  /**< DMA_DEST_ADDR Position */
+#define MXC_F_TPU_DMA_DEST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_DEST_ADDR_POS)) /**< DMA_DEST_ADDR Mask */
+
+/**@} end of group DMA_DEST_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup DMA_CNT_Register
+ * @brief    Crypto DMA Byte Count.
+ * @{
+ */
+#define MXC_F_TPU_DMA_CNT_ADDR_POS 0													/**< DMA_CNT_ADDR Position */
+#define MXC_F_TPU_DMA_CNT_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_CNT_ADDR_POS)) /**< DMA_CNT_ADDR Mask */
+
+/**@} end of group DMA_CNT_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup MAA_CTRL_Register
+ * @brief    MAA Control Register.
+ * @{
+ */
+#define MXC_F_TPU_MAA_CTRL_STC_POS 0											 /**< MAA_CTRL_STC Position */
+#define MXC_F_TPU_MAA_CTRL_STC ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_STC_POS)) /**< MAA_CTRL_STC Mask */
+
+#define MXC_F_TPU_MAA_CTRL_CLC_POS 1											 /**< MAA_CTRL_CLC Position */
+#define MXC_F_TPU_MAA_CTRL_CLC ((uint32_t)(0x7UL << MXC_F_TPU_MAA_CTRL_CLC_POS)) /**< MAA_CTRL_CLC Mask */
+#define MXC_V_TPU_MAA_CTRL_CLC_EXP ((uint32_t)0x0UL)							 /**< MAA_CTRL_CLC_EXP Value */
+#define MXC_S_TPU_MAA_CTRL_CLC_EXP                                                                                     \
+	(MXC_V_TPU_MAA_CTRL_CLC_EXP << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_EXP Setting */
+#define MXC_V_TPU_MAA_CTRL_CLC_SQ ((uint32_t)0x1UL)			   /**< MAA_CTRL_CLC_SQ Value */
+#define MXC_S_TPU_MAA_CTRL_CLC_SQ                                                                                      \
+	(MXC_V_TPU_MAA_CTRL_CLC_SQ << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SQ Setting */
+#define MXC_V_TPU_MAA_CTRL_CLC_MUL ((uint32_t)0x2UL)		  /**< MAA_CTRL_CLC_MUL Value */
+#define MXC_S_TPU_MAA_CTRL_CLC_MUL                                                                                     \
+	(MXC_V_TPU_MAA_CTRL_CLC_MUL << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_MUL Setting */
+#define MXC_V_TPU_MAA_CTRL_CLC_SQMUL ((uint32_t)0x3UL)		   /**< MAA_CTRL_CLC_SQMUL Value */
+#define MXC_S_TPU_MAA_CTRL_CLC_SQMUL                                                                                   \
+	(MXC_V_TPU_MAA_CTRL_CLC_SQMUL << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SQMUL Setting */
+#define MXC_V_TPU_MAA_CTRL_CLC_ADD ((uint32_t)0x4UL)			 /**< MAA_CTRL_CLC_ADD Value */
+#define MXC_S_TPU_MAA_CTRL_CLC_ADD                                                                                     \
+	(MXC_V_TPU_MAA_CTRL_CLC_ADD << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_ADD Setting */
+#define MXC_V_TPU_MAA_CTRL_CLC_SUB ((uint32_t)0x5UL)		   /**< MAA_CTRL_CLC_SUB Value */
+#define MXC_S_TPU_MAA_CTRL_CLC_SUB                                                                                     \
+	(MXC_V_TPU_MAA_CTRL_CLC_SUB << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SUB Setting */
+
+#define MXC_F_TPU_MAA_CTRL_OCALC_POS 4												 /**< MAA_CTRL_OCALC Position */
+#define MXC_F_TPU_MAA_CTRL_OCALC ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_OCALC_POS)) /**< MAA_CTRL_OCALC Mask */
+
+#define MXC_F_TPU_MAA_CTRL_MAAER_POS 7												 /**< MAA_CTRL_MAAER Position */
+#define MXC_F_TPU_MAA_CTRL_MAAER ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_MAAER_POS)) /**< MAA_CTRL_MAAER Mask */
+
+#define MXC_F_TPU_MAA_CTRL_AMS_POS 8											 /**< MAA_CTRL_AMS Position */
+#define MXC_F_TPU_MAA_CTRL_AMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_AMS_POS)) /**< MAA_CTRL_AMS Mask */
+
+#define MXC_F_TPU_MAA_CTRL_BMS_POS 10											 /**< MAA_CTRL_BMS Position */
+#define MXC_F_TPU_MAA_CTRL_BMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_BMS_POS)) /**< MAA_CTRL_BMS Mask */
+
+#define MXC_F_TPU_MAA_CTRL_EMS_POS 12											 /**< MAA_CTRL_EMS Position */
+#define MXC_F_TPU_MAA_CTRL_EMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_EMS_POS)) /**< MAA_CTRL_EMS Mask */
+
+#define MXC_F_TPU_MAA_CTRL_MMS_POS 14											 /**< MAA_CTRL_MMS Position */
+#define MXC_F_TPU_MAA_CTRL_MMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_MMS_POS)) /**< MAA_CTRL_MMS Mask */
+
+#define MXC_F_TPU_MAA_CTRL_AMA_POS 16											 /**< MAA_CTRL_AMA Position */
+#define MXC_F_TPU_MAA_CTRL_AMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_AMA_POS)) /**< MAA_CTRL_AMA Mask */
+
+#define MXC_F_TPU_MAA_CTRL_BMA_POS 20											 /**< MAA_CTRL_BMA Position */
+#define MXC_F_TPU_MAA_CTRL_BMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_BMA_POS)) /**< MAA_CTRL_BMA Mask */
+
+#define MXC_F_TPU_MAA_CTRL_RMA_POS 24											 /**< MAA_CTRL_RMA Position */
+#define MXC_F_TPU_MAA_CTRL_RMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_RMA_POS)) /**< MAA_CTRL_RMA Mask */
+
+#define MXC_F_TPU_MAA_CTRL_TMA_POS 28											 /**< MAA_CTRL_TMA Position */
+#define MXC_F_TPU_MAA_CTRL_TMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_TMA_POS)) /**< MAA_CTRL_TMA Mask */
+
+/**@} end of group MAA_CTRL_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup DIN_Register
+ * @brief    Crypto Data Input. Data input can be written to this register instead of using
+ *           the DMA. This register writes to the FIFO. This register occupies four
+ *           successive words to allow the use of multi-store instructions. Words can be
+ *           written to any location, they will be placed in the FIFO in the order they are
+ *           written. The endian swap input control bit affects this register.
+ * @{
+ */
+#define MXC_F_TPU_DIN_DATA_POS 0												/**< DIN_DATA Position */
+#define MXC_F_TPU_DIN_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DIN_DATA_POS)) /**< DIN_DATA Mask */
+
+/**@} end of group DIN_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup DOUT_Register
+ * @brief    Crypto Data Output. Resulting data from cipher calculation. Data is placed in
+ *           the lower words of these four registers depending on the algorithm. For block
+ *           cipher modes, this register holds the result of most recent encryption or
+ *           decryption operation. These registers are affected by the endian swap bits.
+ * @{
+ */
+#define MXC_F_TPU_DOUT_DATA_POS 0												  /**< DOUT_DATA Position */
+#define MXC_F_TPU_DOUT_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DOUT_DATA_POS)) /**< DOUT_DATA Mask */
+
+/**@} end of group DOUT_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup CRC_POLY_Register
+ * @brief    CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or
+ *           LFSR) should be written to this register. This register is affected by the MSB
+ *           control bit.
+ * @{
+ */
+#define MXC_F_TPU_CRC_POLY_POLY_POS 0													  /**< CRC_POLY_POLY Position */
+#define MXC_F_TPU_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_POLY_POLY_POS)) /**< CRC_POLY_POLY Mask */
+
+/**@} end of group CRC_POLY_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup CRC_VAL_Register
+ * @brief    CRC Value. This is the state for the Galois Field. This register holds the
+ *           result of a CRC calculation or the current state of the LFSR. This register is
+ *           affected by the MSB control bit.
+ * @{
+ */
+#define MXC_F_TPU_CRC_VAL_VAL_POS 0													  /**< CRC_VAL_VAL Position */
+#define MXC_F_TPU_CRC_VAL_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_VAL_VAL_POS)) /**< CRC_VAL_VAL Mask */
+
+/**@} end of group CRC_VAL_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup CRC_PRNG_Register
+ * @brief    Pseudo Random Value. Output of the Galois Field shift register. This holds the
+ *           resulting pseudo-random number if entropy is disabled or true random number if
+ *           entropy is enabled.
+ * @{
+ */
+#define MXC_F_TPU_CRC_PRNG_PRNG_POS 0													  /**< CRC_PRNG_PRNG Position */
+#define MXC_F_TPU_CRC_PRNG_PRNG ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_PRNG_PRNG_POS)) /**< CRC_PRNG_PRNG Mask */
+
+/**@} end of group CRC_PRNG_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup HAM_ECC_Register
+ * @brief    Hamming ECC Register.
+ * @{
+ */
+#define MXC_F_TPU_HAM_ECC_ECC_POS 0												  /**< HAM_ECC_ECC Position */
+#define MXC_F_TPU_HAM_ECC_ECC ((uint32_t)(0xFFFFUL << MXC_F_TPU_HAM_ECC_ECC_POS)) /**< HAM_ECC_ECC Mask */
+
+#define MXC_F_TPU_HAM_ECC_PAR_POS 16										   /**< HAM_ECC_PAR Position */
+#define MXC_F_TPU_HAM_ECC_PAR ((uint32_t)(0x1UL << MXC_F_TPU_HAM_ECC_PAR_POS)) /**< HAM_ECC_PAR Mask */
+
+/**@} end of group HAM_ECC_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup CIPHER_INIT_Register
+ * @brief    Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR
+ *           modes, this register holds the initial value. This register is updated with each
+ *           encryption or decryption operation. This register is affected by the endian swap
+ *           bits.
+ * @{
+ */
+#define MXC_F_TPU_CIPHER_INIT_IVEC_POS 0 /**< CIPHER_INIT_IVEC Position */
+#define MXC_F_TPU_CIPHER_INIT_IVEC                                                                                     \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CIPHER_INIT_IVEC_POS)) /**< CIPHER_INIT_IVEC Mask */
+
+/**@} end of group CIPHER_INIT_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup CIPHER_KEY_Register
+ * @brief    Cipher Key. This register holds the key used for block cipher operations. The
+ *           lower words are used for block ciphers that use shorter key lengths. This
+ *           register is affected by the endian swap input control bits.
+ * @{
+ */
+#define MXC_F_TPU_CIPHER_KEY_KEY_POS 0 /**< CIPHER_KEY_KEY Position */
+#define MXC_F_TPU_CIPHER_KEY_KEY                                                                                       \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CIPHER_KEY_KEY_POS)) /**< CIPHER_KEY_KEY Mask                                \
+																*/
+
+/**@} end of group CIPHER_KEY_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup HASH_DIGEST_Register
+ * @brief    This register holds the calculated hash value. This register is affected by the
+ *           endian swap bits.
+ * @{
+ */
+#define MXC_F_TPU_HASH_DIGEST_HASH_POS 0 /**< HASH_DIGEST_HASH Position */
+#define MXC_F_TPU_HASH_DIGEST_HASH                                                                                     \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_HASH_DIGEST_HASH_POS)) /**< HASH_DIGEST_HASH Mask */
+
+/**@} end of group HASH_DIGEST_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup HASH_MSG_SZ_Register
+ * @brief    Message Size. This register holds the lowest 32-bit of message size in bytes.
+ * @{
+ */
+#define MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS 0 /**< HASH_MSG_SZ_MSGSZ Position */
+#define MXC_F_TPU_HASH_MSG_SZ_MSGSZ                                                                                    \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS)) /**< HASH_MSG_SZ_MSGSZ Mask */
+
+/**@} end of group HASH_MSG_SZ_Register */
+
+/**
+ * @ingroup  tpu_registers
+ * @defgroup MAA_MAWS_Register
+ * @brief    MAA Word Size. This register defines the number of bits for a modular operation.
+ *           This register must be set to a valid value prior to the MAA operation start.
+ *           Valid values are from 1 to 2048. Invalid values are ignored and will not
+ *           initiate a MAA operation.
+ * @{
+ */
+#define MXC_F_TPU_MAA_MAWS_MAWS_POS 0												 /**< MAA_MAWS_MAWS Position */
+#define MXC_F_TPU_MAA_MAWS_MAWS ((uint32_t)(0xFFFUL << MXC_F_TPU_MAA_MAWS_MAWS_POS)) /**< MAA_MAWS_MAWS Mask */
+
+/**@} end of group MAA_MAWS_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TPU_REGS_H_ */

contrib/loaders/flash/msp432/driverlib.c

@@ -67,20 +67,20 @@ static bool __pcm_set_core_voltage_level_advanced(uint_fast8_t voltage_level,
 		reg_value = PCM->CTL0;
 
 		switch (pcm_get_power_state()) {
-			case PCM_AM_LF_VCORE1:
-			case PCM_AM_DCDC_VCORE1:
-			case PCM_AM_LDO_VCORE0:
-				PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE1)
-					| (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
-				break;
-			case PCM_AM_LF_VCORE0:
-			case PCM_AM_DCDC_VCORE0:
-			case PCM_AM_LDO_VCORE1:
-				PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE0)
-					| (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
-				break;
-			default:
-				break;
+		case PCM_AM_LF_VCORE1:
+		case PCM_AM_DCDC_VCORE1:
+		case PCM_AM_LDO_VCORE0:
+			PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE1)
+				| (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
+			break;
+		case PCM_AM_LF_VCORE0:
+		case PCM_AM_DCDC_VCORE0:
+		case PCM_AM_LDO_VCORE1:
+			PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE0)
+				| (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
+			break;
+		default:
+			break;
 		}
 
 		if (blocking) {
@@ -117,22 +117,22 @@ uint8_t pcm_get_power_mode(void)
 	current_power_state = pcm_get_power_state();
 
 	switch (current_power_state) {
-		case PCM_AM_LDO_VCORE0:
-		case PCM_AM_LDO_VCORE1:
-		case PCM_LPM0_LDO_VCORE0:
-		case PCM_LPM0_LDO_VCORE1:
-		default:
-			return PCM_LDO_MODE;
-		case PCM_AM_DCDC_VCORE0:
-		case PCM_AM_DCDC_VCORE1:
-		case PCM_LPM0_DCDC_VCORE0:
-		case PCM_LPM0_DCDC_VCORE1:
-			return PCM_DCDC_MODE;
-		case PCM_LPM0_LF_VCORE0:
-		case PCM_LPM0_LF_VCORE1:
-		case PCM_AM_LF_VCORE1:
-		case PCM_AM_LF_VCORE0:
-			return PCM_LF_MODE;
+	case PCM_AM_DCDC_VCORE0:
+	case PCM_AM_DCDC_VCORE1:
+	case PCM_LPM0_DCDC_VCORE0:
+	case PCM_LPM0_DCDC_VCORE1:
+		return PCM_DCDC_MODE;
+	case PCM_LPM0_LF_VCORE0:
+	case PCM_LPM0_LF_VCORE1:
+	case PCM_AM_LF_VCORE1:
+	case PCM_AM_LF_VCORE0:
+		return PCM_LF_MODE;
+	case PCM_AM_LDO_VCORE0:
+	case PCM_AM_LDO_VCORE1:
+	case PCM_LPM0_LDO_VCORE0:
+	case PCM_LPM0_LDO_VCORE1:
+	default:
+		return PCM_LDO_MODE;
 	}
 }
 
@@ -141,23 +141,23 @@ uint8_t pcm_get_core_voltage_level(void)
 	uint8_t current_power_state = pcm_get_power_state();
 
 	switch (current_power_state) {
-		case PCM_AM_LDO_VCORE0:
-		case PCM_AM_DCDC_VCORE0:
-		case PCM_AM_LF_VCORE0:
-		case PCM_LPM0_LDO_VCORE0:
-		case PCM_LPM0_DCDC_VCORE0:
-		case PCM_LPM0_LF_VCORE0:
-		default:
-			return PCM_VCORE0;
-		case PCM_AM_LDO_VCORE1:
-		case PCM_AM_DCDC_VCORE1:
-		case PCM_AM_LF_VCORE1:
-		case PCM_LPM0_LDO_VCORE1:
-		case PCM_LPM0_DCDC_VCORE1:
-		case PCM_LPM0_LF_VCORE1:
-			return PCM_VCORE1;
-		case PCM_LPM3:
-			return PCM_VCORELPM3;
+	case PCM_AM_LDO_VCORE1:
+	case PCM_AM_DCDC_VCORE1:
+	case PCM_AM_LF_VCORE1:
+	case PCM_LPM0_LDO_VCORE1:
+	case PCM_LPM0_DCDC_VCORE1:
+	case PCM_LPM0_LF_VCORE1:
+		return PCM_VCORE1;
+	case PCM_LPM3:
+		return PCM_VCORELPM3;
+	case PCM_AM_LDO_VCORE0:
+	case PCM_AM_DCDC_VCORE0:
+	case PCM_AM_LF_VCORE0:
+	case PCM_LPM0_LDO_VCORE0:
+	case PCM_LPM0_DCDC_VCORE0:
+	case PCM_LPM0_LF_VCORE0:
+	default:
+		return PCM_VCORE0;
 	}
 }
 
@@ -186,44 +186,44 @@ static bool __pcm_set_power_mode_advanced(uint_fast8_t power_mode,
 		reg_value = PCM->CTL0;
 
 		switch (current_power_state) {
-			case PCM_AM_DCDC_VCORE0:
-			case PCM_AM_LF_VCORE0:
-				PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE0
-					| (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
-				break;
-			case PCM_AM_LF_VCORE1:
-			case PCM_AM_DCDC_VCORE1:
-				PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE1
-					| (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
-				break;
-			case PCM_AM_LDO_VCORE1: {
-				if (power_mode == PCM_DCDC_MODE) {
-					PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE1
-						| (reg_value & ~(PCM_CTL0_KEY_MASK
-						| PCM_CTL0_AMR_MASK)));
-				} else if (power_mode == PCM_LF_MODE) {
-					PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE1
-						| (reg_value & ~(PCM_CTL0_KEY_MASK
-						| PCM_CTL0_AMR_MASK)));
-				} else
-					return false;
-				break;
+		case PCM_AM_DCDC_VCORE0:
+		case PCM_AM_LF_VCORE0:
+			PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE0
+				| (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
+			break;
+		case PCM_AM_LF_VCORE1:
+		case PCM_AM_DCDC_VCORE1:
+			PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE1
+				| (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
+			break;
+		case PCM_AM_LDO_VCORE1:
+			if (power_mode == PCM_DCDC_MODE) {
+				PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE1
+					| (reg_value & ~(PCM_CTL0_KEY_MASK
+					| PCM_CTL0_AMR_MASK)));
+			} else if (power_mode == PCM_LF_MODE) {
+				PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE1
+					| (reg_value & ~(PCM_CTL0_KEY_MASK
+					| PCM_CTL0_AMR_MASK)));
+			} else {
+				return false;
 			}
-			case PCM_AM_LDO_VCORE0: {
-				if (power_mode == PCM_DCDC_MODE) {
-					PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE0
-						| (reg_value & ~(PCM_CTL0_KEY_MASK
-						| PCM_CTL0_AMR_MASK)));
-				} else if (power_mode == PCM_LF_MODE) {
-					PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE0
-						| (reg_value & ~(PCM_CTL0_KEY_MASK
-						| PCM_CTL0_AMR_MASK)));
-				} else
-					return false;
-				break;
+			break;
+		case PCM_AM_LDO_VCORE0:
+			if (power_mode == PCM_DCDC_MODE) {
+				PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE0
+					| (reg_value & ~(PCM_CTL0_KEY_MASK
+					| PCM_CTL0_AMR_MASK)));
+			} else if (power_mode == PCM_LF_MODE) {
+				PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE0
+					| (reg_value & ~(PCM_CTL0_KEY_MASK
+					| PCM_CTL0_AMR_MASK)));
+			} else {
+				return false;
 			}
-			default:
-				break;
+			break;
+		default:
+			break;
 		}
 
 		if (blocking) {
@@ -231,8 +231,9 @@ static bool __pcm_set_power_mode_advanced(uint_fast8_t power_mode,
 				if (bool_timeout && !(--time_out))
 					return false;
 			}
-		} else
+		} else {
 			return true;
+		}
 
 		current_power_mode = pcm_get_power_mode();
 		current_power_state = pcm_get_power_state();
@@ -256,76 +257,76 @@ static bool __pcm_set_power_state_advanced(uint_fast8_t power_state,
 		return true;
 
 	switch (power_state) {
-		case PCM_AM_LDO_VCORE0:
-			return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
-					blocking) && __pcm_set_power_mode_advanced(PCM_LDO_MODE,
-					timeout, blocking);
-		case PCM_AM_LDO_VCORE1:
-			return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
-					blocking) && __pcm_set_power_mode_advanced(PCM_LDO_MODE,
-					timeout, blocking);
-		case PCM_AM_DCDC_VCORE0:
-			return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
-					blocking) && __pcm_set_power_mode_advanced(PCM_DCDC_MODE,
-					timeout, blocking);
-		case PCM_AM_DCDC_VCORE1:
-			return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
-					blocking) && __pcm_set_power_mode_advanced(PCM_DCDC_MODE,
-					timeout, blocking);
-		case PCM_AM_LF_VCORE0:
-			return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
-					blocking) && __pcm_set_power_mode_advanced(PCM_LF_MODE,
-					timeout, blocking);
-		case PCM_AM_LF_VCORE1:
-			return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
-					blocking) && __pcm_set_power_mode_advanced(PCM_LF_MODE,
-					timeout, blocking);
-		case PCM_LPM0_LDO_VCORE0:
-			if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
-				blocking) || !__pcm_set_power_mode_advanced(PCM_LDO_MODE,
-				timeout, blocking))
-				break;
-			return pcm_goto_lpm0();
-		case PCM_LPM0_LDO_VCORE1:
-			if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
-				blocking) || !__pcm_set_power_mode_advanced(PCM_LDO_MODE,
-				timeout, blocking))
-				break;
-			return pcm_goto_lpm0();
-		case PCM_LPM0_DCDC_VCORE0:
-			if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
-				blocking) || !__pcm_set_power_mode_advanced(PCM_DCDC_MODE,
-				timeout, blocking))
-				break;
-			return pcm_goto_lpm0();
-		case PCM_LPM0_DCDC_VCORE1:
-			if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
-				blocking) || !__pcm_set_power_mode_advanced(PCM_DCDC_MODE,
-				timeout, blocking))
-				break;
-			return pcm_goto_lpm0();
-		case PCM_LPM0_LF_VCORE0:
-			if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
-				blocking) || !__pcm_set_power_mode_advanced(PCM_LF_MODE,
-				timeout, blocking))
-				break;
-			return pcm_goto_lpm0();
-		case PCM_LPM0_LF_VCORE1:
-			if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
-				blocking) || !__pcm_set_power_mode_advanced(PCM_LF_MODE,
-				timeout, blocking))
-				break;
-			return pcm_goto_lpm0();
-		case PCM_LPM3:
-			return pcm_goto_lpm3();
-		case PCM_LPM4:
-			return pcm_goto_lpm4();
-		case PCM_LPM45:
-			return pcm_shutdown_device(PCM_LPM45);
-		case PCM_LPM35_VCORE0:
-			return pcm_shutdown_device(PCM_LPM35_VCORE0);
-		default:
-			return false;
+	case PCM_AM_LDO_VCORE0:
+		return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
+				blocking) && __pcm_set_power_mode_advanced(PCM_LDO_MODE,
+				timeout, blocking);
+	case PCM_AM_LDO_VCORE1:
+		return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
+				blocking) && __pcm_set_power_mode_advanced(PCM_LDO_MODE,
+				timeout, blocking);
+	case PCM_AM_DCDC_VCORE0:
+		return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
+				blocking) && __pcm_set_power_mode_advanced(PCM_DCDC_MODE,
+				timeout, blocking);
+	case PCM_AM_DCDC_VCORE1:
+		return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
+				blocking) && __pcm_set_power_mode_advanced(PCM_DCDC_MODE,
+				timeout, blocking);
+	case PCM_AM_LF_VCORE0:
+		return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
+				blocking) && __pcm_set_power_mode_advanced(PCM_LF_MODE,
+				timeout, blocking);
+	case PCM_AM_LF_VCORE1:
+		return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
+				blocking) && __pcm_set_power_mode_advanced(PCM_LF_MODE,
+				timeout, blocking);
+	case PCM_LPM0_LDO_VCORE0:
+		if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
+			blocking) || !__pcm_set_power_mode_advanced(PCM_LDO_MODE,
+			timeout, blocking))
+			break;
+		return pcm_goto_lpm0();
+	case PCM_LPM0_LDO_VCORE1:
+		if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
+			blocking) || !__pcm_set_power_mode_advanced(PCM_LDO_MODE,
+			timeout, blocking))
+			break;
+		return pcm_goto_lpm0();
+	case PCM_LPM0_DCDC_VCORE0:
+		if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
+			blocking) || !__pcm_set_power_mode_advanced(PCM_DCDC_MODE,
+			timeout, blocking))
+			break;
+		return pcm_goto_lpm0();
+	case PCM_LPM0_DCDC_VCORE1:
+		if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
+			blocking) || !__pcm_set_power_mode_advanced(PCM_DCDC_MODE,
+			timeout, blocking))
+			break;
+		return pcm_goto_lpm0();
+	case PCM_LPM0_LF_VCORE0:
+		if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
+			blocking) || !__pcm_set_power_mode_advanced(PCM_LF_MODE,
+			timeout, blocking))
+			break;
+		return pcm_goto_lpm0();
+	case PCM_LPM0_LF_VCORE1:
+		if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
+			blocking) || !__pcm_set_power_mode_advanced(PCM_LF_MODE,
+			timeout, blocking))
+			break;
+		return pcm_goto_lpm0();
+	case PCM_LPM3:
+		return pcm_goto_lpm3();
+	case PCM_LPM4:
+		return pcm_goto_lpm4();
+	case PCM_LPM45:
+		return pcm_shutdown_device(PCM_LPM45);
+	case PCM_LPM35_VCORE0:
+		return pcm_shutdown_device(PCM_LPM35_VCORE0);
+	default:
+		return false;
 	}
 
 	return false;

contrib/loaders/flash/msp432/main_msp432e4x.c

@@ -30,37 +30,37 @@ int main(void)
 
 	while (1) {
 		switch (FLASH_LOADER->FLASH_FUNCTION) {
-			case FLASH_INIT:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_init();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_MASS_ERASE:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_mass_erase();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_SECTOR_ERASE:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_sector_erase();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_PROGRAM:
-			case FLASH_CONTINUOUS_PROGRAM:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_continous_write();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_EXIT:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_exit();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_NO_COMMAND:
-				break;
-			default:
-				FLASH_LOADER->RETURN_CODE = FLASH_WRONG_COMMAND;
-				break;
+		case FLASH_INIT:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_init();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_MASS_ERASE:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_mass_erase();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_SECTOR_ERASE:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_sector_erase();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_PROGRAM:
+		case FLASH_CONTINUOUS_PROGRAM:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_continous_write();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_EXIT:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_exit();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_NO_COMMAND:
+			break;
+		default:
+			FLASH_LOADER->RETURN_CODE = FLASH_WRONG_COMMAND;
+			break;
 		}
 	}
 }

contrib/loaders/flash/msp432/main_msp432p401x.c

@@ -49,41 +49,41 @@ int main(void)
 
 	while (1) {
 		switch (FLASH_LOADER->FLASH_FUNCTION) {
-			case FLASH_INIT:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_init();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_MASS_ERASE:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_mass_erase();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_SECTOR_ERASE:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_sector_erase();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_PROGRAM:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_write();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_CONTINUOUS_PROGRAM:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_continous_write();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_EXIT:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_exit();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_NO_COMMAND:
-				break;
-			default:
-				FLASH_LOADER->RETURN_CODE = FLASH_WRONG_COMMAND;
-				break;
+		case FLASH_INIT:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_init();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_MASS_ERASE:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_mass_erase();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_SECTOR_ERASE:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_sector_erase();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_PROGRAM:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_write();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_CONTINUOUS_PROGRAM:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_continous_write();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_EXIT:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_exit();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_NO_COMMAND:
+			break;
+		default:
+			FLASH_LOADER->RETURN_CODE = FLASH_WRONG_COMMAND;
+			break;
 		}
 	}
 }

contrib/loaders/flash/msp432/main_msp432p411x.c

@@ -52,41 +52,41 @@ int main(void)
 
 	while (1) {
 		switch (FLASH_LOADER->FLASH_FUNCTION) {
-			case FLASH_INIT:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_init();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_MASS_ERASE:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_mass_erase();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_SECTOR_ERASE:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_sector_erase();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_PROGRAM:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_write();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_CONTINUOUS_PROGRAM:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_continous_write();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_EXIT:
-				FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
-				msp432_flash_exit();
-				FLASH_LOADER->FLASH_FUNCTION = 0;
-				break;
-			case FLASH_NO_COMMAND:
-				break;
-			default:
-				FLASH_LOADER->RETURN_CODE = FLASH_WRONG_COMMAND;
-				break;
+		case FLASH_INIT:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_init();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_MASS_ERASE:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_mass_erase();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_SECTOR_ERASE:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_sector_erase();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_PROGRAM:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_write();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_CONTINUOUS_PROGRAM:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_continous_write();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_EXIT:
+			FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
+			msp432_flash_exit();
+			FLASH_LOADER->FLASH_FUNCTION = 0;
+			break;
+		case FLASH_NO_COMMAND:
+			break;
+		default:
+			FLASH_LOADER->RETURN_CODE = FLASH_WRONG_COMMAND;
+			break;
 		}
 	}
 }

contrib/loaders/flash/npcx/npcx_algo.inc

@@ -1,60 +1,70 @@
 /* Autogenerated with ../../../../src/helper/bin2char.sh */
-0x08,0xb5,0xdf,0xf8,0x08,0xd0,0x00,0xf0,0x2f,0xf9,0x00,0x00,0x48,0x15,0x0c,0x20,
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-0x16,0x00,0x02,0x40,0x70,0xb5,0x11,0x4c,0x23,0x78,0x03,0xf0,0xfd,0x03,0x23,0x70,
-0xc0,0x21,0x05,0x20,0xff,0xf7,0xec,0xff,0x0d,0x4a,0x0e,0x49,0x6f,0xf0,0x7f,0x43,
-0x6f,0xf0,0x2e,0x05,0x10,0x46,0x15,0x70,0x06,0x78,0xf6,0x09,0xfc,0xd1,0x0e,0x78,
-0xf6,0x07,0x01,0xd5,0x01,0x3b,0xf6,0xd1,0x22,0x78,0x42,0xf0,0x02,0x02,0x00,0x2b,
-0x22,0x70,0x0c,0xbf,0x03,0x20,0x00,0x20,0x70,0xbd,0x00,0xbf,0x1f,0x00,0x02,0x40,
+0x08,0xb5,0xdf,0xf8,0x08,0xd0,0x00,0xf0,0x95,0xf9,0x00,0x00,0xec,0x15,0x0c,0x20,
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+0x1e,0xd0,0x1b,0x68,0x02,0x2b,0x1b,0xd1,0x10,0x4b,0x1a,0x78,0x50,0xb1,0x02,0xf0,
+0xf7,0x02,0x1a,0x70,0x01,0x22,0x08,0x78,0x01,0x23,0x93,0x40,0x03,0x43,0xdb,0xb2,
+0x0b,0x70,0x70,0x47,0x42,0xf0,0x08,0x02,0x1a,0x70,0x01,0x22,0x08,0x78,0x01,0x23,
+0x93,0x40,0x20,0xea,0x03,0x03,0xf3,0xe7,0x01,0x22,0x00,0x28,0xf6,0xd0,0xea,0xe7,
+0x00,0x22,0xfa,0xe7,0x00,0x00,0x0c,0x20,0x1f,0x00,0x02,0x40,0x43,0x00,0x02,0x40,
+0x73,0xb5,0x04,0x46,0x00,0x20,0x15,0x46,0x0e,0x46,0xff,0xf7,0xcb,0xff,0x0f,0x4b,
+0x01,0x94,0xc4,0xf3,0x07,0x44,0x1c,0x70,0x9d,0xf8,0x05,0x20,0x5a,0x70,0x9d,0xf8,
+0x04,0x20,0x9a,0x70,0xf3,0x21,0x02,0x20,0xff,0xf7,0xb2,0xff,0x2c,0x46,0x63,0x1b,
+0xb3,0x42,0x05,0xd3,0x01,0x20,0x02,0xb0,0xbd,0xe8,0x70,0x40,0xff,0xf7,0xb2,0xbf,
+0xe0,0x21,0x14,0xf8,0x01,0x0b,0xff,0xf7,0xa3,0xff,0xf0,0xe7,0x1a,0x00,0x02,0x40,
+0x08,0x4b,0x1b,0x68,0x02,0x2b,0x08,0x4b,0x07,0xd1,0x08,0x4a,0x80,0x21,0x11,0x70,
+0xc0,0x22,0x1a,0x70,0x00,0x22,0x1a,0x71,0x70,0x47,0x1a,0x78,0x42,0xf0,0x80,0x02,
+0x1a,0x70,0x70,0x47,0x00,0x00,0x0c,0x20,0x10,0x30,0x0c,0x40,0x00,0x30,0x0c,0x40,
+0x38,0xb5,0x00,0x20,0xff,0xf7,0x8e,0xff,0xc0,0x21,0x05,0x20,0xff,0xf7,0x80,0xff,
+0x0b,0x4b,0x0c,0x4a,0x6f,0xf0,0x7f,0x44,0x6f,0xf0,0x2e,0x00,0x19,0x46,0x18,0x70,
+0x0d,0x78,0xed,0x09,0xfc,0xd1,0x15,0x78,0xed,0x07,0x01,0xd5,0x01,0x3c,0xf6,0xd1,
+0x01,0x20,0xff,0xf7,0x77,0xff,0x00,0x2c,0x0c,0xbf,0x03,0x20,0x00,0x20,0x38,0xbd,
 0x1e,0x00,0x02,0x40,0x1a,0x00,0x02,0x40,0x08,0xb5,0xc0,0x21,0x06,0x20,0xff,0xf7,
-0xc7,0xff,0xff,0xf7,0xcf,0xff,0x28,0xb9,0x03,0x4b,0x1b,0x78,0x13,0xf0,0x02,0x0f,
-0x08,0xbf,0x02,0x20,0x08,0xbd,0x00,0xbf,0x1a,0x00,0x02,0x40,0xf8,0xb5,0x12,0x4c,
-0x23,0x78,0x03,0xf0,0xfd,0x03,0x23,0x70,0x10,0x4b,0x17,0x46,0xc0,0xf3,0x07,0x42,
-0x1a,0x70,0xc0,0xf3,0x07,0x22,0xc0,0xb2,0x03,0xf8,0x01,0x2c,0x0e,0x46,0x03,0xf8,
-0x02,0x0c,0xe8,0x21,0x02,0x20,0xff,0xf7,0xa3,0xff,0x00,0x25,0xae,0x42,0x04,0xd8,
-0x23,0x78,0x43,0xf0,0x02,0x03,0x23,0x70,0xf8,0xbd,0x78,0x5d,0xe0,0x21,0xff,0xf7,
-0x97,0xff,0x01,0x35,0xf2,0xe7,0x00,0xbf,0x1f,0x00,0x02,0x40,0x19,0x00,0x02,0x40,
-0x70,0x47,0x2d,0xe9,0xf0,0x41,0x00,0xf1,0xff,0x06,0x26,0xf0,0xff,0x06,0x34,0x1a,
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